[deliverable/linux.git] / drivers / clocksource / sh_cmt.c

/*
 * SuperH Timer Support - CMT
 *
 *  Copyright (C) 2008 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/sh_cmt.h>

struct sh_cmt_priv {
	void __iomem *mapbase;
	struct clk *clk;
	unsigned long width; /* 16 or 32 bit version of hardware block */
	unsigned long overflow_bit;
	unsigned long clear_bits;
	struct irqaction irqaction;
	struct platform_device *pdev;

	unsigned long flags;
	unsigned long match_value;
	unsigned long next_match_value;
	unsigned long max_match_value;
	unsigned long rate;
	spinlock_t lock;
	struct clock_event_device ced;
	struct clocksource cs;
	unsigned long total_cycles;
};

static DEFINE_SPINLOCK(sh_cmt_lock);

#define CMSTR -1 /* shared register */
#define CMCSR 0 /* channel register */
#define CMCNT 1 /* channel register */
#define CMCOR 2 /* channel register */

static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
{
	struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
	void __iomem *base = p->mapbase;
	unsigned long offs;

	if (reg_nr == CMSTR) {
		offs = 0;
		base -= cfg->channel_offset;
	} else
		offs = reg_nr;

	if (p->width == 16)
		offs <<= 1;
	else {
		offs <<= 2;
		if ((reg_nr == CMCNT) || (reg_nr == CMCOR))
			return ioread32(base + offs);
	}

	return ioread16(base + offs);
}

static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr,
				unsigned long value)
{
	struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
	void __iomem *base = p->mapbase;
	unsigned long offs;

	if (reg_nr == CMSTR) {
		offs = 0;
		base -= cfg->channel_offset;
	} else
		offs = reg_nr;

	if (p->width == 16)
		offs <<= 1;
	else {
		offs <<= 2;
		if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) {
			iowrite32(value, base + offs);
			return;
		}
	}

	iowrite16(value, base + offs);
}

static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
					int *has_wrapped)
{
	unsigned long v1, v2, v3;
	int o1, o2;

	o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;

	/* Make sure the timer value is stable. Stolen from acpi_pm.c */
	do {
		o2 = o1;
		v1 = sh_cmt_read(p, CMCNT);
		v2 = sh_cmt_read(p, CMCNT);
		v3 = sh_cmt_read(p, CMCNT);
		o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
	} while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
			  || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));

	*has_wrapped = o1;
	return v2;
}


static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
{
	struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
	unsigned long flags, value;

	/* start stop register shared by multiple timer channels */
	spin_lock_irqsave(&sh_cmt_lock, flags);
	value = sh_cmt_read(p, CMSTR);

	if (start)
		value |= 1 << cfg->timer_bit;
	else
		value &= ~(1 << cfg->timer_bit);

	sh_cmt_write(p, CMSTR, value);
	spin_unlock_irqrestore(&sh_cmt_lock, flags);
}

static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
{
	struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
	int ret;

	/* enable clock */
	ret = clk_enable(p->clk);
	if (ret) {
		pr_err("sh_cmt: cannot enable clock \"%s\"\n", cfg->clk);
		return ret;
	}
	*rate = clk_get_rate(p->clk) / 8;

	/* make sure channel is disabled */
	sh_cmt_start_stop_ch(p, 0);

	/* configure channel, periodic mode and maximum timeout */
	if (p->width == 16)
		sh_cmt_write(p, CMCSR, 0);
	else
		sh_cmt_write(p, CMCSR, 0x01a4);

	sh_cmt_write(p, CMCOR, 0xffffffff);
	sh_cmt_write(p, CMCNT, 0);

	/* enable channel */
	sh_cmt_start_stop_ch(p, 1);
	return 0;
}

static void sh_cmt_disable(struct sh_cmt_priv *p)
{
	/* disable channel */
	sh_cmt_start_stop_ch(p, 0);

	/* stop clock */
	clk_disable(p->clk);
}

/* private flags */
#define FLAG_CLOCKEVENT (1 << 0)
#define FLAG_CLOCKSOURCE (1 << 1)
#define FLAG_REPROGRAM (1 << 2)
#define FLAG_SKIPEVENT (1 << 3)
#define FLAG_IRQCONTEXT (1 << 4)

static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p,
					      int absolute)
{
	unsigned long new_match;
	unsigned long value = p->next_match_value;
	unsigned long delay = 0;
	unsigned long now = 0;
	int has_wrapped;

	now = sh_cmt_get_counter(p, &has_wrapped);
	p->flags |= FLAG_REPROGRAM; /* force reprogram */

	if (has_wrapped) {
		/* we're competing with the interrupt handler.
		 *  -> let the interrupt handler reprogram the timer.
		 *  -> interrupt number two handles the event.
		 */
		p->flags |= FLAG_SKIPEVENT;
		return;
	}

	if (absolute)
		now = 0;

	do {
		/* reprogram the timer hardware,
		 * but don't save the new match value yet.
		 */
		new_match = now + value + delay;
		if (new_match > p->max_match_value)
			new_match = p->max_match_value;

		sh_cmt_write(p, CMCOR, new_match);

		now = sh_cmt_get_counter(p, &has_wrapped);
		if (has_wrapped && (new_match > p->match_value)) {
			/* we are changing to a greater match value,
			 * so this wrap must be caused by the counter
			 * matching the old value.
			 * -> first interrupt reprograms the timer.
			 * -> interrupt number two handles the event.
			 */
			p->flags |= FLAG_SKIPEVENT;
			break;
		}

		if (has_wrapped) {
			/* we are changing to a smaller match value,
			 * so the wrap must be caused by the counter
			 * matching the new value.
			 * -> save programmed match value.
			 * -> let isr handle the event.
			 */
			p->match_value = new_match;
			break;
		}

		/* be safe: verify hardware settings */
		if (now < new_match) {
			/* timer value is below match value, all good.
			 * this makes sure we won't miss any match events.
			 * -> save programmed match value.
			 * -> let isr handle the event.
			 */
			p->match_value = new_match;
			break;
		}

		/* the counter has reached a value greater
		 * than our new match value. and since the
		 * has_wrapped flag isn't set we must have
		 * programmed a too close event.
		 * -> increase delay and retry.
		 */
		if (delay)
			delay <<= 1;
		else
			delay = 1;

		if (!delay)
			pr_warning("sh_cmt: too long delay\n");

	} while (delay);
}

static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
{
	unsigned long flags;

	if (delta > p->max_match_value)
		pr_warning("sh_cmt: delta out of range\n");

	spin_lock_irqsave(&p->lock, flags);
	p->next_match_value = delta;
	sh_cmt_clock_event_program_verify(p, 0);
	spin_unlock_irqrestore(&p->lock, flags);
}

static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
{
	struct sh_cmt_priv *p = dev_id;

	/* clear flags */
	sh_cmt_write(p, CMCSR, sh_cmt_read(p, CMCSR) & p->clear_bits);

	/* update clock source counter to begin with if enabled
	 * the wrap flag should be cleared by the timer specific
	 * isr before we end up here.
	 */
	if (p->flags & FLAG_CLOCKSOURCE)
		p->total_cycles += p->match_value;

	if (!(p->flags & FLAG_REPROGRAM))
		p->next_match_value = p->max_match_value;

	p->flags |= FLAG_IRQCONTEXT;

	if (p->flags & FLAG_CLOCKEVENT) {
		if (!(p->flags & FLAG_SKIPEVENT)) {
			if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) {
				p->next_match_value = p->max_match_value;
				p->flags |= FLAG_REPROGRAM;
			}

			p->ced.event_handler(&p->ced);
		}
	}

	p->flags &= ~FLAG_SKIPEVENT;

	if (p->flags & FLAG_REPROGRAM) {
		p->flags &= ~FLAG_REPROGRAM;
		sh_cmt_clock_event_program_verify(p, 1);

		if (p->flags & FLAG_CLOCKEVENT)
			if ((p->ced.mode == CLOCK_EVT_MODE_SHUTDOWN)
			    || (p->match_value == p->next_match_value))
				p->flags &= ~FLAG_REPROGRAM;
	}

	p->flags &= ~FLAG_IRQCONTEXT;

	return IRQ_HANDLED;
}

static int sh_cmt_start(struct sh_cmt_priv *p, unsigned long flag)
{
	int ret = 0;
	unsigned long flags;

	spin_lock_irqsave(&p->lock, flags);

	if (!(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
		ret = sh_cmt_enable(p, &p->rate);

	if (ret)
		goto out;
	p->flags |= flag;

	/* setup timeout if no clockevent */
	if ((flag == FLAG_CLOCKSOURCE) && (!(p->flags & FLAG_CLOCKEVENT)))
		sh_cmt_set_next(p, p->max_match_value);
 out:
	spin_unlock_irqrestore(&p->lock, flags);

	return ret;
}

static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag)
{
	unsigned long flags;
	unsigned long f;

	spin_lock_irqsave(&p->lock, flags);

	f = p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
	p->flags &= ~flag;

	if (f && !(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
		sh_cmt_disable(p);

	/* adjust the timeout to maximum if only clocksource left */
	if ((flag == FLAG_CLOCKEVENT) && (p->flags & FLAG_CLOCKSOURCE))
		sh_cmt_set_next(p, p->max_match_value);

	spin_unlock_irqrestore(&p->lock, flags);
}

static struct sh_cmt_priv *cs_to_sh_cmt(struct clocksource *cs)
{
	return container_of(cs, struct sh_cmt_priv, cs);
}

static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
{
	struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
	unsigned long flags, raw;
	unsigned long value;
	int has_wrapped;

	spin_lock_irqsave(&p->lock, flags);
	value = p->total_cycles;
	raw = sh_cmt_get_counter(p, &has_wrapped);

	if (unlikely(has_wrapped))
		raw += p->match_value;
	spin_unlock_irqrestore(&p->lock, flags);

	return value + raw;
}

static int sh_cmt_clocksource_enable(struct clocksource *cs)
{
	struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
	int ret;

	p->total_cycles = 0;

	ret = sh_cmt_start(p, FLAG_CLOCKSOURCE);
	if (ret)
		return ret;

	/* TODO: calculate good shift from rate and counter bit width */
	cs->shift = 0;
	cs->mult = clocksource_hz2mult(p->rate, cs->shift);
	return 0;
}

static void sh_cmt_clocksource_disable(struct clocksource *cs)
{
	sh_cmt_stop(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
}

static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
				       char *name, unsigned long rating)
{
	struct clocksource *cs = &p->cs;

	cs->name = name;
	cs->rating = rating;
	cs->read = sh_cmt_clocksource_read;
	cs->enable = sh_cmt_clocksource_enable;
	cs->disable = sh_cmt_clocksource_disable;
	cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
	cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
	pr_info("sh_cmt: %s used as clock source\n", cs->name);
	clocksource_register(cs);
	return 0;
}

static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced)
{
	return container_of(ced, struct sh_cmt_priv, ced);
}

static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic)
{
	struct clock_event_device *ced = &p->ced;

	sh_cmt_start(p, FLAG_CLOCKEVENT);

	/* TODO: calculate good shift from rate and counter bit width */

	ced->shift = 32;
	ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
	ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced);
	ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);

	if (periodic)
		sh_cmt_set_next(p, (p->rate + HZ/2) / HZ);
	else
		sh_cmt_set_next(p, p->max_match_value);
}

static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
				    struct clock_event_device *ced)
{
	struct sh_cmt_priv *p = ced_to_sh_cmt(ced);

	/* deal with old setting first */
	switch (ced->mode) {
	case CLOCK_EVT_MODE_PERIODIC:
	case CLOCK_EVT_MODE_ONESHOT:
		sh_cmt_stop(p, FLAG_CLOCKEVENT);
		break;
	default:
		break;
	}

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		pr_info("sh_cmt: %s used for periodic clock events\n",
			ced->name);
		sh_cmt_clock_event_start(p, 1);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		pr_info("sh_cmt: %s used for oneshot clock events\n",
			ced->name);
		sh_cmt_clock_event_start(p, 0);
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
		sh_cmt_stop(p, FLAG_CLOCKEVENT);
		break;
	default:
		break;
	}
}

static int sh_cmt_clock_event_next(unsigned long delta,
				   struct clock_event_device *ced)
{
	struct sh_cmt_priv *p = ced_to_sh_cmt(ced);

	BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
	if (likely(p->flags & FLAG_IRQCONTEXT))
		p->next_match_value = delta;
	else
		sh_cmt_set_next(p, delta);

	return 0;
}

static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
				       char *name, unsigned long rating)
{
	struct clock_event_device *ced = &p->ced;

	memset(ced, 0, sizeof(*ced));

	ced->name = name;
	ced->features = CLOCK_EVT_FEAT_PERIODIC;
	ced->features |= CLOCK_EVT_FEAT_ONESHOT;
	ced->rating = rating;
	ced->cpumask = cpumask_of(0);
	ced->set_next_event = sh_cmt_clock_event_next;
	ced->set_mode = sh_cmt_clock_event_mode;

	pr_info("sh_cmt: %s used for clock events\n", ced->name);
	clockevents_register_device(ced);
}

int sh_cmt_register(struct sh_cmt_priv *p, char *name,
		    unsigned long clockevent_rating,
		    unsigned long clocksource_rating)
{
	if (p->width == (sizeof(p->max_match_value) * 8))
		p->max_match_value = ~0;
	else
		p->max_match_value = (1 << p->width) - 1;

	p->match_value = p->max_match_value;
	spin_lock_init(&p->lock);

	if (clockevent_rating)
		sh_cmt_register_clockevent(p, name, clockevent_rating);

	if (clocksource_rating)
		sh_cmt_register_clocksource(p, name, clocksource_rating);

	return 0;
}

static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
{
	struct sh_cmt_config *cfg = pdev->dev.platform_data;
	struct resource *res;
	int irq, ret;
	ret = -ENXIO;

	memset(p, 0, sizeof(*p));
	p->pdev = pdev;

	if (!cfg) {
		dev_err(&p->pdev->dev, "missing platform data\n");
		goto err0;
	}

	platform_set_drvdata(pdev, p);

	res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&p->pdev->dev, "failed to get I/O memory\n");
		goto err0;
	}

	irq = platform_get_irq(p->pdev, 0);
	if (irq < 0) {
		dev_err(&p->pdev->dev, "failed to get irq\n");
		goto err0;
	}

	/* map memory, let mapbase point to our channel */
	p->mapbase = ioremap_nocache(res->start, resource_size(res));
	if (p->mapbase == NULL) {
		pr_err("sh_cmt: failed to remap I/O memory\n");
		goto err0;
	}

	/* request irq using setup_irq() (too early for request_irq()) */
	p->irqaction.name = cfg->name;
	p->irqaction.handler = sh_cmt_interrupt;
	p->irqaction.dev_id = p;
	p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
	p->irqaction.mask = CPU_MASK_NONE;
	ret = setup_irq(irq, &p->irqaction);
	if (ret) {
		pr_err("sh_cmt: failed to request irq %d\n", irq);
		goto err1;
	}

	/* get hold of clock */
	p->clk = clk_get(&p->pdev->dev, cfg->clk);
	if (IS_ERR(p->clk)) {
		pr_err("sh_cmt: cannot get clock \"%s\"\n", cfg->clk);
		ret = PTR_ERR(p->clk);
		goto err2;
	}

	if (resource_size(res) == 6) {
		p->width = 16;
		p->overflow_bit = 0x80;
		p->clear_bits = ~0xc0;
	} else {
		p->width = 32;
		p->overflow_bit = 0x8000;
		p->clear_bits = ~0xc000;
	}

	return sh_cmt_register(p, cfg->name,
			       cfg->clockevent_rating,
			       cfg->clocksource_rating);
 err2:
	remove_irq(irq, &p->irqaction);
 err1:
	iounmap(p->mapbase);
 err0:
	return ret;
}

static int __devinit sh_cmt_probe(struct platform_device *pdev)
{
	struct sh_cmt_priv *p = platform_get_drvdata(pdev);
	struct sh_cmt_config *cfg = pdev->dev.platform_data;
	int ret;

	if (p) {
		pr_info("sh_cmt: %s kept as earlytimer\n", cfg->name);
		return 0;
	}

	p = kmalloc(sizeof(*p), GFP_KERNEL);
	if (p == NULL) {
		dev_err(&pdev->dev, "failed to allocate driver data\n");
		return -ENOMEM;
	}

	ret = sh_cmt_setup(p, pdev);
	if (ret) {
		kfree(p);
		platform_set_drvdata(pdev, NULL);
	}
	return ret;
}

static int __devexit sh_cmt_remove(struct platform_device *pdev)
{
	return -EBUSY; /* cannot unregister clockevent and clocksource */
}

static struct platform_driver sh_cmt_device_driver = {
	.probe		= sh_cmt_probe,
	.remove		= __devexit_p(sh_cmt_remove),
	.driver		= {
		.name	= "sh_cmt",
	}
};

static int __init sh_cmt_init(void)
{
	return platform_driver_register(&sh_cmt_device_driver);
}

static void __exit sh_cmt_exit(void)
{
	platform_driver_unregister(&sh_cmt_device_driver);
}

early_platform_init("earlytimer", &sh_cmt_device_driver);
module_init(sh_cmt_init);
module_exit(sh_cmt_exit);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("SuperH CMT Timer Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
3fb1b6ad MD	1	/*
	2	* SuperH Timer Support - CMT
	3	*
	4	* Copyright (C) 2008 Magnus Damm
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
	20	#include <linux/init.h>
3fb1b6ad MD	21	#include <linux/platform_device.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/ioport.h>
	25	#include <linux/io.h>
	26	#include <linux/clk.h>
	27	#include <linux/irq.h>
	28	#include <linux/err.h>
	29	#include <linux/clocksource.h>
	30	#include <linux/clockchips.h>
	31	#include <linux/sh_cmt.h>
	32
	33	struct sh_cmt_priv {
	34	void __iomem *mapbase;
	35	struct clk *clk;
	36	unsigned long width; /* 16 or 32 bit version of hardware block */
	37	unsigned long overflow_bit;
	38	unsigned long clear_bits;
	39	struct irqaction irqaction;
	40	struct platform_device *pdev;
	41
	42	unsigned long flags;
	43	unsigned long match_value;
	44	unsigned long next_match_value;
	45	unsigned long max_match_value;
	46	unsigned long rate;
	47	spinlock_t lock;
	48	struct clock_event_device ced;
19bdc9d0	49	struct clocksource cs;
3fb1b6ad MD	50	unsigned long total_cycles;
	51	};
	52
	53	static DEFINE_SPINLOCK(sh_cmt_lock);
	54
	55	#define CMSTR -1 /* shared register */
	56	#define CMCSR 0 /* channel register */
	57	#define CMCNT 1 /* channel register */
	58	#define CMCOR 2 /* channel register */
	59
	60	static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
	61	{
	62	struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
	63	void __iomem *base = p->mapbase;
	64	unsigned long offs;
	65
	66	if (reg_nr == CMSTR) {
	67	offs = 0;
	68	base -= cfg->channel_offset;
	69	} else
	70	offs = reg_nr;
	71
	72	if (p->width == 16)
	73	offs <<= 1;
	74	else {
	75	offs <<= 2;
	76	if ((reg_nr == CMCNT) \|\| (reg_nr == CMCOR))
	77	return ioread32(base + offs);
	78	}
	79
	80	return ioread16(base + offs);
	81	}
	82
	83	static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr,
	84	unsigned long value)
	85	{
	86	struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
	87	void __iomem *base = p->mapbase;
	88	unsigned long offs;
	89
	90	if (reg_nr == CMSTR) {
	91	offs = 0;
	92	base -= cfg->channel_offset;
	93	} else
	94	offs = reg_nr;
	95
	96	if (p->width == 16)
	97	offs <<= 1;
	98	else {
	99	offs <<= 2;
	100	if ((reg_nr == CMCNT) \|\| (reg_nr == CMCOR)) {
	101	iowrite32(value, base + offs);
	102	return;
	103	}
	104	}
	105
	106	iowrite16(value, base + offs);
	107	}
	108
	109	static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
	110	int *has_wrapped)
	111	{
	112	unsigned long v1, v2, v3;
5b644c7a MD	113	int o1, o2;
	114
	115	o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
3fb1b6ad MD	116
	117	/* Make sure the timer value is stable. Stolen from acpi_pm.c */
	118	do {
5b644c7a	119	o2 = o1;
3fb1b6ad MD	120	v1 = sh_cmt_read(p, CMCNT);
	121	v2 = sh_cmt_read(p, CMCNT);
	122	v3 = sh_cmt_read(p, CMCNT);
5b644c7a MD	123	o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
	124	} while (unlikely((o1 != o2) \|\| (v1 > v2 && v1 < v3)
	125	\|\| (v2 > v3 && v2 < v1) \|\| (v3 > v1 && v3 < v2)));
3fb1b6ad	126
5b644c7a	127	*has_wrapped = o1;
3fb1b6ad MD	128	return v2;
	129	}
	130
	131
	132	static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
	133	{
	134	struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
	135	unsigned long flags, value;
	136
	137	/* start stop register shared by multiple timer channels */
	138	spin_lock_irqsave(&sh_cmt_lock, flags);
	139	value = sh_cmt_read(p, CMSTR);
	140
	141	if (start)
	142	value \|= 1 << cfg->timer_bit;
	143	else
	144	value &= ~(1 << cfg->timer_bit);
	145
	146	sh_cmt_write(p, CMSTR, value);
	147	spin_unlock_irqrestore(&sh_cmt_lock, flags);
	148	}
	149
	150	static int sh_cmt_enable(struct sh_cmt_priv p, unsigned long rate)
	151	{
	152	struct sh_cmt_config *cfg = p->pdev->dev.platform_data;
	153	int ret;
	154
	155	/* enable clock */
	156	ret = clk_enable(p->clk);
	157	if (ret) {
	158	pr_err("sh_cmt: cannot enable clock \"%s\"\n", cfg->clk);
	159	return ret;
	160	}
	161	*rate = clk_get_rate(p->clk) / 8;
	162
	163	/* make sure channel is disabled */
	164	sh_cmt_start_stop_ch(p, 0);
	165
	166	/* configure channel, periodic mode and maximum timeout */
	167	if (p->width == 16)
	168	sh_cmt_write(p, CMCSR, 0);
	169	else
	170	sh_cmt_write(p, CMCSR, 0x01a4);
	171
	172	sh_cmt_write(p, CMCOR, 0xffffffff);
	173	sh_cmt_write(p, CMCNT, 0);
	174
	175	/* enable channel */
	176	sh_cmt_start_stop_ch(p, 1);
	177	return 0;
	178	}
	179
	180	static void sh_cmt_disable(struct sh_cmt_priv *p)
	181	{
	182	/* disable channel */
	183	sh_cmt_start_stop_ch(p, 0);
	184
	185	/* stop clock */
	186	clk_disable(p->clk);
	187	}
	188
	189	/* private flags */
	190	#define FLAG_CLOCKEVENT (1 << 0)
	191	#define FLAG_CLOCKSOURCE (1 << 1)
192	#define FLAG_REPROGRAM (1 << 2)
193	#define FLAG_SKIPEVENT (1 << 3)
194	#define FLAG_IRQCONTEXT (1 << 4)
195
196	static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p,
197	int absolute)
198	{
199	unsigned long new_match;
200	unsigned long value = p->next_match_value;
201	unsigned long delay = 0;
202	unsigned long now = 0;
203	int has_wrapped;
204
205	now = sh_cmt_get_counter(p, &has_wrapped);
206	p->flags \|= FLAG_REPROGRAM; /* force reprogram */
207
208	if (has_wrapped) {
209	/* we're competing with the interrupt handler.
210	* -> let the interrupt handler reprogram the timer.
211	* -> interrupt number two handles the event.
212	*/
213	p->flags \|= FLAG_SKIPEVENT;
214	return;
215	}
216
217	if (absolute)
218	now = 0;
219
220	do {
221	/* reprogram the timer hardware,
222	* but don't save the new match value yet.
223	*/
224	new_match = now + value + delay;
225	if (new_match > p->max_match_value)
226	new_match = p->max_match_value;
227
228	sh_cmt_write(p, CMCOR, new_match);
229
230	now = sh_cmt_get_counter(p, &has_wrapped);
231	if (has_wrapped && (new_match > p->match_value)) {
232	/* we are changing to a greater match value,
233	* so this wrap must be caused by the counter
234	* matching the old value.
235	* -> first interrupt reprograms the timer.
236	* -> interrupt number two handles the event.
237	*/
238	p->flags \|= FLAG_SKIPEVENT;
239	break;
240	}
241
242	if (has_wrapped) {
243	/* we are changing to a smaller match value,
244	* so the wrap must be caused by the counter
245	* matching the new value.
246	* -> save programmed match value.
247	* -> let isr handle the event.
248	*/
249	p->match_value = new_match;
250	break;
251	}
252
253	/* be safe: verify hardware settings */
254	if (now < new_match) {
255	/* timer value is below match value, all good.
256	* this makes sure we won't miss any match events.
257	* -> save programmed match value.
258	* -> let isr handle the event.
259	*/
260	p->match_value = new_match;
261	break;
262	}
263
264	/* the counter has reached a value greater
265	* than our new match value. and since the
266	* has_wrapped flag isn't set we must have
267	* programmed a too close event.
268	* -> increase delay and retry.
269	*/
270	if (delay)
271	delay <<= 1;
272	else
273	delay = 1;
274
275	if (!delay)
276	pr_warning("sh_cmt: too long delay\n");
277
278	} while (delay);
279	}
280
281	static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
282	{
283	unsigned long flags;
284
285	if (delta > p->max_match_value)
286	pr_warning("sh_cmt: delta out of range\n");
287
288	spin_lock_irqsave(&p->lock, flags);
289	p->next_match_value = delta;
290	sh_cmt_clock_event_program_verify(p, 0);
291	spin_unlock_irqrestore(&p->lock, flags);
292	}
293
294	static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
295	{
296	struct sh_cmt_priv *p = dev_id;
297
298	/* clear flags */
299	sh_cmt_write(p, CMCSR, sh_cmt_read(p, CMCSR) & p->clear_bits);
300
301	/* update clock source counter to begin with if enabled
302	* the wrap flag should be cleared by the timer specific
303	* isr before we end up here.
304	*/
305	if (p->flags & FLAG_CLOCKSOURCE)
306	p->total_cycles += p->match_value;
307
308	if (!(p->flags & FLAG_REPROGRAM))
309	p->next_match_value = p->max_match_value;
310
311	p->flags \|= FLAG_IRQCONTEXT;
312
313	if (p->flags & FLAG_CLOCKEVENT) {
314	if (!(p->flags & FLAG_SKIPEVENT)) {
315	if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) {
316	p->next_match_value = p->max_match_value;
317	p->flags \|= FLAG_REPROGRAM;
318	}
319
320	p->ced.event_handler(&p->ced);
321	}
322	}
323
324	p->flags &= ~FLAG_SKIPEVENT;
325
326	if (p->flags & FLAG_REPROGRAM) {
327	p->flags &= ~FLAG_REPROGRAM;
328	sh_cmt_clock_event_program_verify(p, 1);
329
330	if (p->flags & FLAG_CLOCKEVENT)
331	if ((p->ced.mode == CLOCK_EVT_MODE_SHUTDOWN)
332	\|\| (p->match_value == p->next_match_value))
333	p->flags &= ~FLAG_REPROGRAM;
334	}
335
336	p->flags &= ~FLAG_IRQCONTEXT;
337
338	return IRQ_HANDLED;
339	}
340
341	static int sh_cmt_start(struct sh_cmt_priv *p, unsigned long flag)
342	{
343	int ret = 0;
344	unsigned long flags;
345
346	spin_lock_irqsave(&p->lock, flags);
347
348	if (!(p->flags & (FLAG_CLOCKEVENT \| FLAG_CLOCKSOURCE)))
349	ret = sh_cmt_enable(p, &p->rate);
350
351	if (ret)
352	goto out;
353	p->flags \|= flag;
354
355	/* setup timeout if no clockevent */
356	if ((flag == FLAG_CLOCKSOURCE) && (!(p->flags & FLAG_CLOCKEVENT)))
357	sh_cmt_set_next(p, p->max_match_value);
358	out:
359	spin_unlock_irqrestore(&p->lock, flags);
360
361	return ret;
362	}
363
364	static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag)
365	{
366	unsigned long flags;
367	unsigned long f;
368
369	spin_lock_irqsave(&p->lock, flags);
370
371	f = p->flags & (FLAG_CLOCKEVENT \| FLAG_CLOCKSOURCE);
372	p->flags &= ~flag;
373
374	if (f && !(p->flags & (FLAG_CLOCKEVENT \| FLAG_CLOCKSOURCE)))
375	sh_cmt_disable(p);
376
377	/* adjust the timeout to maximum if only clocksource left */
378	if ((flag == FLAG_CLOCKEVENT) && (p->flags & FLAG_CLOCKSOURCE))
379	sh_cmt_set_next(p, p->max_match_value);
380
381	spin_unlock_irqrestore(&p->lock, flags);
382	}
383
19bdc9d0 MD	384	static struct sh_cmt_priv cs_to_sh_cmt(struct clocksource cs)
	385	{
	386	return container_of(cs, struct sh_cmt_priv, cs);
	387	}
	388
	389	static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
	390	{
	391	struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
	392	unsigned long flags, raw;
	393	unsigned long value;
	394	int has_wrapped;
	395
	396	spin_lock_irqsave(&p->lock, flags);
	397	value = p->total_cycles;
	398	raw = sh_cmt_get_counter(p, &has_wrapped);
	399
	400	if (unlikely(has_wrapped))
5b644c7a	401	raw += p->match_value;
19bdc9d0 MD	402	spin_unlock_irqrestore(&p->lock, flags);
	403
	404	return value + raw;
	405	}
	406
	407	static int sh_cmt_clocksource_enable(struct clocksource *cs)
	408	{
	409	struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
	410	int ret;
	411
	412	p->total_cycles = 0;
	413
	414	ret = sh_cmt_start(p, FLAG_CLOCKSOURCE);
	415	if (ret)
	416	return ret;
	417
	418	/* TODO: calculate good shift from rate and counter bit width */
	419	cs->shift = 0;
	420	cs->mult = clocksource_hz2mult(p->rate, cs->shift);
	421	return 0;
	422	}
	423
	424	static void sh_cmt_clocksource_disable(struct clocksource *cs)
	425	{
	426	sh_cmt_stop(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
	427	}
	428
	429	static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
	430	char *name, unsigned long rating)
	431	{
	432	struct clocksource *cs = &p->cs;
	433
	434	cs->name = name;
	435	cs->rating = rating;
	436	cs->read = sh_cmt_clocksource_read;
	437	cs->enable = sh_cmt_clocksource_enable;
	438	cs->disable = sh_cmt_clocksource_disable;
	439	cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
	440	cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
	441	pr_info("sh_cmt: %s used as clock source\n", cs->name);
	442	clocksource_register(cs);
	443	return 0;
	444	}
	445
3fb1b6ad MD	446	static struct sh_cmt_priv ced_to_sh_cmt(struct clock_event_device ced)
	447	{
	448	return container_of(ced, struct sh_cmt_priv, ced);
	449	}
	450
	451	static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic)
	452	{
	453	struct clock_event_device *ced = &p->ced;
	454
	455	sh_cmt_start(p, FLAG_CLOCKEVENT);
	456
	457	/* TODO: calculate good shift from rate and counter bit width */
	458
	459	ced->shift = 32;
	460	ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
	461	ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced);
	462	ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
	463
	464	if (periodic)
	465	sh_cmt_set_next(p, (p->rate + HZ/2) / HZ);
	466	else
	467	sh_cmt_set_next(p, p->max_match_value);
	468	}
	469
	470	static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
	471	struct clock_event_device *ced)
	472	{
	473	struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
	474
	475	/* deal with old setting first */
	476	switch (ced->mode) {
	477	case CLOCK_EVT_MODE_PERIODIC:
	478	case CLOCK_EVT_MODE_ONESHOT:
	479	sh_cmt_stop(p, FLAG_CLOCKEVENT);
	480	break;
	481	default:
	482	break;
	483	}
	484
	485	switch (mode) {
	486	case CLOCK_EVT_MODE_PERIODIC:
	487	pr_info("sh_cmt: %s used for periodic clock events\n",
	488	ced->name);
	489	sh_cmt_clock_event_start(p, 1);
	490	break;
	491	case CLOCK_EVT_MODE_ONESHOT:
	492	pr_info("sh_cmt: %s used for oneshot clock events\n",
	493	ced->name);
	494	sh_cmt_clock_event_start(p, 0);
	495	break;
	496	case CLOCK_EVT_MODE_SHUTDOWN:
	497	case CLOCK_EVT_MODE_UNUSED:
	498	sh_cmt_stop(p, FLAG_CLOCKEVENT);
	499	break;
	500	default:
	501	break;
	502	}
	503	}
	504
	505	static int sh_cmt_clock_event_next(unsigned long delta,
	506	struct clock_event_device *ced)
	507	{
	508	struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
	509
510	BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
511	if (likely(p->flags & FLAG_IRQCONTEXT))
512	p->next_match_value = delta;
513	else
514	sh_cmt_set_next(p, delta);
515
516	return 0;
517	}
518
519	static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
520	char *name, unsigned long rating)
521	{
522	struct clock_event_device *ced = &p->ced;
523
524	memset(ced, 0, sizeof(*ced));
525
526	ced->name = name;
527	ced->features = CLOCK_EVT_FEAT_PERIODIC;
528	ced->features \|= CLOCK_EVT_FEAT_ONESHOT;
529	ced->rating = rating;
530	ced->cpumask = cpumask_of(0);
531	ced->set_next_event = sh_cmt_clock_event_next;
532	ced->set_mode = sh_cmt_clock_event_mode;
533
534	pr_info("sh_cmt: %s used for clock events\n", ced->name);
3fb1b6ad MD	535	clockevents_register_device(ced);
	536	}
	537
	538	int sh_cmt_register(struct sh_cmt_priv p, char name,
	539	unsigned long clockevent_rating,
	540	unsigned long clocksource_rating)
	541	{
	542	if (p->width == (sizeof(p->max_match_value) * 8))
	543	p->max_match_value = ~0;
	544	else
	545	p->max_match_value = (1 << p->width) - 1;
	546
	547	p->match_value = p->max_match_value;
	548	spin_lock_init(&p->lock);
	549
	550	if (clockevent_rating)
	551	sh_cmt_register_clockevent(p, name, clockevent_rating);
	552
19bdc9d0 MD	553	if (clocksource_rating)
	554	sh_cmt_register_clocksource(p, name, clocksource_rating);
	555
3fb1b6ad MD	556	return 0;
	557	}
	558
	559	static int sh_cmt_setup(struct sh_cmt_priv p, struct platform_device pdev)
	560	{
	561	struct sh_cmt_config *cfg = pdev->dev.platform_data;
	562	struct resource *res;
	563	int irq, ret;
	564	ret = -ENXIO;
	565
	566	memset(p, 0, sizeof(*p));
	567	p->pdev = pdev;
	568
	569	if (!cfg) {
	570	dev_err(&p->pdev->dev, "missing platform data\n");
	571	goto err0;
	572	}
	573
	574	platform_set_drvdata(pdev, p);
	575
	576	res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
	577	if (!res) {
	578	dev_err(&p->pdev->dev, "failed to get I/O memory\n");
	579	goto err0;
	580	}
	581
	582	irq = platform_get_irq(p->pdev, 0);
	583	if (irq < 0) {
	584	dev_err(&p->pdev->dev, "failed to get irq\n");
	585	goto err0;
	586	}
	587
	588	/* map memory, let mapbase point to our channel */
	589	p->mapbase = ioremap_nocache(res->start, resource_size(res));
	590	if (p->mapbase == NULL) {
	591	pr_err("sh_cmt: failed to remap I/O memory\n");
	592	goto err0;
	593	}
	594
	595	/* request irq using setup_irq() (too early for request_irq()) */
	596	p->irqaction.name = cfg->name;
	597	p->irqaction.handler = sh_cmt_interrupt;
	598	p->irqaction.dev_id = p;
	599	p->irqaction.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL;
	600	p->irqaction.mask = CPU_MASK_NONE;
	601	ret = setup_irq(irq, &p->irqaction);
	602	if (ret) {
	603	pr_err("sh_cmt: failed to request irq %d\n", irq);
	604	goto err1;
	605	}
	606
	607	/* get hold of clock */
	608	p->clk = clk_get(&p->pdev->dev, cfg->clk);
	609	if (IS_ERR(p->clk)) {
	610	pr_err("sh_cmt: cannot get clock \"%s\"\n", cfg->clk);
	611	ret = PTR_ERR(p->clk);
	612	goto err2;
	613	}
	614
	615	if (resource_size(res) == 6) {
	616	p->width = 16;
	617	p->overflow_bit = 0x80;
	618	p->clear_bits = ~0xc0;
	619	} else {
620	p->width = 32;
621	p->overflow_bit = 0x8000;
622	p->clear_bits = ~0xc000;
623	}
624
625	return sh_cmt_register(p, cfg->name,
626	cfg->clockevent_rating,
627	cfg->clocksource_rating);
628	err2:
3093e78e	629	remove_irq(irq, &p->irqaction);
3fb1b6ad MD	630	err1:
	631	iounmap(p->mapbase);
	632	err0:
	633	return ret;
	634	}
	635
	636	static int __devinit sh_cmt_probe(struct platform_device *pdev)
	637	{
	638	struct sh_cmt_priv *p = platform_get_drvdata(pdev);
e475eedb	639	struct sh_cmt_config *cfg = pdev->dev.platform_data;
3fb1b6ad MD	640	int ret;
3fb1b6ad MD	641
e475eedb MD	642	if (p) {
	643	pr_info("sh_cmt: %s kept as earlytimer\n", cfg->name);
	644	return 0;
	645	}
	646
8e0b8429	647	p = kmalloc(sizeof(*p), GFP_KERNEL);
3fb1b6ad MD	648	if (p == NULL) {
	649	dev_err(&pdev->dev, "failed to allocate driver data\n");
	650	return -ENOMEM;
	651	}
	652
	653	ret = sh_cmt_setup(p, pdev);
	654	if (ret) {
8e0b8429	655	kfree(p);
3fb1b6ad MD	656	platform_set_drvdata(pdev, NULL);
	657	}
	658	return ret;
	659	}
	660
	661	static int __devexit sh_cmt_remove(struct platform_device *pdev)
	662	{
	663	return -EBUSY; /* cannot unregister clockevent and clocksource */
	664	}
	665
	666	static struct platform_driver sh_cmt_device_driver = {
	667	.probe = sh_cmt_probe,
	668	.remove = __devexit_p(sh_cmt_remove),
	669	.driver = {
	670	.name = "sh_cmt",
	671	}
	672	};
	673
	674	static int __init sh_cmt_init(void)
	675	{
	676	return platform_driver_register(&sh_cmt_device_driver);
	677	}
	678
	679	static void __exit sh_cmt_exit(void)
	680	{
	681	platform_driver_unregister(&sh_cmt_device_driver);
	682	}
	683
e475eedb	684	early_platform_init("earlytimer", &sh_cmt_device_driver);
3fb1b6ad MD	685	module_init(sh_cmt_init);
	686	module_exit(sh_cmt_exit);
	687
	688	MODULE_AUTHOR("Magnus Damm");
	689	MODULE_DESCRIPTION("SuperH CMT Timer Driver");
	690	MODULE_LICENSE("GPL v2");