[deliverable/linux.git] / drivers / clocksource / sun4i_timer.c

/*
 * Allwinner A1X SoCs timer handling.
 *
 * Copyright (C) 2012 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * Based on code from
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Benn Huang <benn@allwinnertech.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqreturn.h>
#include <linux/sched_clock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#define TIMER_IRQ_EN_REG	0x00
#define TIMER_IRQ_EN(val)		BIT(val)
#define TIMER_IRQ_ST_REG	0x04
#define TIMER_CTL_REG(val)	(0x10 * val + 0x10)
#define TIMER_CTL_ENABLE		BIT(0)
#define TIMER_CTL_RELOAD		BIT(1)
#define TIMER_CTL_CLK_SRC(val)		(((val) & 0x3) << 2)
#define TIMER_CTL_CLK_SRC_OSC24M		(1)
#define TIMER_CTL_CLK_PRES(val)		(((val) & 0x7) << 4)
#define TIMER_CTL_ONESHOT		BIT(7)
#define TIMER_INTVAL_REG(val)	(0x10 * (val) + 0x14)
#define TIMER_CNTVAL_REG(val)	(0x10 * (val) + 0x18)

static void __iomem *timer_base;
static u32 ticks_per_jiffy;

/*
 * When we disable a timer, we need to wait at least for 2 cycles of
 * the timer source clock. We will use for that the clocksource timer
 * that is already setup and runs at the same frequency than the other
 * timers, and we never will be disabled.
 */
static void sun4i_clkevt_sync(void)
{
	u32 old = readl(timer_base + TIMER_CNTVAL_REG(1));

	while ((old - readl(timer_base + TIMER_CNTVAL_REG(1))) < 3)
		cpu_relax();
}

static void sun4i_clkevt_time_stop(u8 timer)
{
	u32 val = readl(timer_base + TIMER_CTL_REG(timer));
	writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
	sun4i_clkevt_sync();
}

static void sun4i_clkevt_time_setup(u8 timer, unsigned long delay)
{
	writel(delay, timer_base + TIMER_INTVAL_REG(timer));
}

static void sun4i_clkevt_time_start(u8 timer, bool periodic)
{
	u32 val = readl(timer_base + TIMER_CTL_REG(timer));

	if (periodic)
		val &= ~TIMER_CTL_ONESHOT;
	else
		val |= TIMER_CTL_ONESHOT;

	writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
	       timer_base + TIMER_CTL_REG(timer));
}

static void sun4i_clkevt_mode(enum clock_event_mode mode,
			      struct clock_event_device *clk)
{
	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		sun4i_clkevt_time_stop(0);
		sun4i_clkevt_time_setup(0, ticks_per_jiffy);
		sun4i_clkevt_time_start(0, true);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		sun4i_clkevt_time_stop(0);
		sun4i_clkevt_time_start(0, false);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	default:
		sun4i_clkevt_time_stop(0);
		break;
	}
}

static int sun4i_clkevt_next_event(unsigned long evt,
				   struct clock_event_device *unused)
{
	sun4i_clkevt_time_stop(0);
	sun4i_clkevt_time_setup(0, evt);
	sun4i_clkevt_time_start(0, false);

	return 0;
}

static struct clock_event_device sun4i_clockevent = {
	.name = "sun4i_tick",
	.rating = 300,
	.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode = sun4i_clkevt_mode,
	.set_next_event = sun4i_clkevt_next_event,
};


static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = (struct clock_event_device *)dev_id;

	writel(0x1, timer_base + TIMER_IRQ_ST_REG);
	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction sun4i_timer_irq = {
	.name = "sun4i_timer0",
	.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.handler = sun4i_timer_interrupt,
	.dev_id = &sun4i_clockevent,
};

static u32 sun4i_timer_sched_read(void)
{
	return ~readl(timer_base + TIMER_CNTVAL_REG(1));
}

static void __init sun4i_timer_init(struct device_node *node)
{
	unsigned long rate = 0;
	struct clk *clk;
	int ret, irq;
	u32 val;

	timer_base = of_iomap(node, 0);
	if (!timer_base)
		panic("Can't map registers");

	irq = irq_of_parse_and_map(node, 0);
	if (irq <= 0)
		panic("Can't parse IRQ");

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk))
		panic("Can't get timer clock");
	clk_prepare_enable(clk);

	rate = clk_get_rate(clk);

	writel(~0, timer_base + TIMER_INTVAL_REG(1));
	writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD |
	       TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
	       timer_base + TIMER_CTL_REG(1));

	setup_sched_clock(sun4i_timer_sched_read, 32, rate);
	clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
			      rate, 300, 32, clocksource_mmio_readl_down);

	ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);

	writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
	       timer_base + TIMER_CTL_REG(0));

	ret = setup_irq(irq, &sun4i_timer_irq);
	if (ret)
		pr_warn("failed to setup irq %d\n", irq);

	/* Enable timer0 interrupt */
	val = readl(timer_base + TIMER_IRQ_EN_REG);
	writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);

	sun4i_clockevent.cpumask = cpumask_of(0);

	clockevents_config_and_register(&sun4i_clockevent, rate, 0x1,
					0xffffffff);
}
CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
		       sun4i_timer_init);
Commit	Line	Data
b2ac5d75 MR	1	/*
	2	* Allwinner A1X SoCs timer handling.
	3	*
	4	* Copyright (C) 2012 Maxime Ripard
	5	*
	6	* Maxime Ripard <maxime.ripard@free-electrons.com>
	7	*
	8	* Based on code from
	9	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	10	* Benn Huang <benn@allwinnertech.com>
	11	*
	12	* This file is licensed under the terms of the GNU General Public
	13	* License version 2. This program is licensed "as is" without any
	14	* warranty of any kind, whether express or implied.
	15	*/
	16
	17	#include <linux/clk.h>
	18	#include <linux/clockchips.h>
	19	#include <linux/interrupt.h>
	20	#include <linux/irq.h>
	21	#include <linux/irqreturn.h>
137c6b3c	22	#include <linux/sched_clock.h>
b2ac5d75 MR	23	#include <linux/of.h>
	24	#include <linux/of_address.h>
	25	#include <linux/of_irq.h>
b2ac5d75	26
04981731	27	#define TIMER_IRQ_EN_REG 0x00
40777645	28	#define TIMER_IRQ_EN(val) BIT(val)
b2ac5d75	29	#define TIMER_IRQ_ST_REG 0x04
04981731	30	#define TIMER_CTL_REG(val) (0x10 * val + 0x10)
40777645	31	#define TIMER_CTL_ENABLE BIT(0)
9eded232	32	#define TIMER_CTL_RELOAD BIT(1)
a2c49e7b MR	33	#define TIMER_CTL_CLK_SRC(val) (((val) & 0x3) << 2)
	34	#define TIMER_CTL_CLK_SRC_OSC24M (1)
	35	#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
40777645	36	#define TIMER_CTL_ONESHOT BIT(7)
bb008b9e MR	37	#define TIMER_INTVAL_REG(val) (0x10 * (val) + 0x14)
bb008b9e MR	38	#define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18)
b2ac5d75	39
b2ac5d75	40	static void __iomem *timer_base;
7e141834	41	static u32 ticks_per_jiffy;
b2ac5d75	42
63d88f1a MR	43	/*
	44	* When we disable a timer, we need to wait at least for 2 cycles of
	45	* the timer source clock. We will use for that the clocksource timer
	46	* that is already setup and runs at the same frequency than the other
	47	* timers, and we never will be disabled.
	48	*/
	49	static void sun4i_clkevt_sync(void)
	50	{
	51	u32 old = readl(timer_base + TIMER_CNTVAL_REG(1));
	52
	53	while ((old - readl(timer_base + TIMER_CNTVAL_REG(1))) < 3)
	54	cpu_relax();
	55	}
	56
96651a07 MR	57	static void sun4i_clkevt_time_stop(u8 timer)
	58	{
	59	u32 val = readl(timer_base + TIMER_CTL_REG(timer));
	60	writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
	61	sun4i_clkevt_sync();
	62	}
	63
	64	static void sun4i_clkevt_time_setup(u8 timer, unsigned long delay)
	65	{
	66	writel(delay, timer_base + TIMER_INTVAL_REG(timer));
	67	}
	68
	69	static void sun4i_clkevt_time_start(u8 timer, bool periodic)
	70	{
	71	u32 val = readl(timer_base + TIMER_CTL_REG(timer));
	72
	73	if (periodic)
	74	val &= ~TIMER_CTL_ONESHOT;
	75	else
	76	val \|= TIMER_CTL_ONESHOT;
	77
7e141834 MR	78	writel(val \| TIMER_CTL_ENABLE \| TIMER_CTL_RELOAD,
7e141834 MR	79	timer_base + TIMER_CTL_REG(timer));
96651a07 MR	80	}
96651a07 MR	81
119fd635	82	static void sun4i_clkevt_mode(enum clock_event_mode mode,
b2ac5d75 MR	83	struct clock_event_device *clk)
b2ac5d75 MR	84	{
b2ac5d75 MR	85	switch (mode) {
b2ac5d75 MR	86	case CLOCK_EVT_MODE_PERIODIC:
96651a07	87	sun4i_clkevt_time_stop(0);
7e141834	88	sun4i_clkevt_time_setup(0, ticks_per_jiffy);
96651a07	89	sun4i_clkevt_time_start(0, true);
b2ac5d75	90	break;
b2ac5d75	91	case CLOCK_EVT_MODE_ONESHOT:
96651a07 MR	92	sun4i_clkevt_time_stop(0);
96651a07 MR	93	sun4i_clkevt_time_start(0, false);
b2ac5d75 MR	94	break;
	95	case CLOCK_EVT_MODE_UNUSED:
	96	case CLOCK_EVT_MODE_SHUTDOWN:
	97	default:
96651a07	98	sun4i_clkevt_time_stop(0);
b2ac5d75 MR	99	break;
	100	}
	101	}
	102
119fd635	103	static int sun4i_clkevt_next_event(unsigned long evt,
b2ac5d75 MR	104	struct clock_event_device *unused)
b2ac5d75 MR	105	{
96651a07 MR	106	sun4i_clkevt_time_stop(0);
	107	sun4i_clkevt_time_setup(0, evt);
	108	sun4i_clkevt_time_start(0, false);
b2ac5d75 MR	109
	110	return 0;
	111	}
	112
119fd635 MR	113	static struct clock_event_device sun4i_clockevent = {
119fd635 MR	114	.name = "sun4i_tick",
b2ac5d75 MR	115	.rating = 300,
b2ac5d75 MR	116	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
119fd635 MR	117	.set_mode = sun4i_clkevt_mode,
119fd635 MR	118	.set_next_event = sun4i_clkevt_next_event,
b2ac5d75 MR	119	};
	120
	121
119fd635	122	static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
b2ac5d75 MR	123	{
	124	struct clock_event_device evt = (struct clock_event_device )dev_id;
	125
	126	writel(0x1, timer_base + TIMER_IRQ_ST_REG);
	127	evt->event_handler(evt);
	128
	129	return IRQ_HANDLED;
	130	}
	131
119fd635 MR	132	static struct irqaction sun4i_timer_irq = {
119fd635 MR	133	.name = "sun4i_timer0",
b2ac5d75	134	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
119fd635 MR	135	.handler = sun4i_timer_interrupt,
119fd635 MR	136	.dev_id = &sun4i_clockevent,
b2ac5d75 MR	137	};
b2ac5d75 MR	138
137c6b3c MR	139	static u32 sun4i_timer_sched_read(void)
	140	{
	141	return ~readl(timer_base + TIMER_CNTVAL_REG(1));
	142	}
	143
119fd635	144	static void __init sun4i_timer_init(struct device_node *node)
b2ac5d75	145	{
b2ac5d75 MR	146	unsigned long rate = 0;
	147	struct clk *clk;
	148	int ret, irq;
	149	u32 val;
	150
b2ac5d75 MR	151	timer_base = of_iomap(node, 0);
	152	if (!timer_base)
	153	panic("Can't map registers");
	154
	155	irq = irq_of_parse_and_map(node, 0);
	156	if (irq <= 0)
	157	panic("Can't parse IRQ");
	158
b2ac5d75 MR	159	clk = of_clk_get(node, 0);
	160	if (IS_ERR(clk))
	161	panic("Can't get timer clock");
8c31bec2	162	clk_prepare_enable(clk);
b2ac5d75 MR	163
	164	rate = clk_get_rate(clk);
	165
137c6b3c MR	166	writel(~0, timer_base + TIMER_INTVAL_REG(1));
	167	writel(TIMER_CTL_ENABLE \| TIMER_CTL_RELOAD \|
	168	TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
	169	timer_base + TIMER_CTL_REG(1));
	170
	171	setup_sched_clock(sun4i_timer_sched_read, 32, rate);
	172	clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name,
	173	rate, 300, 32, clocksource_mmio_readl_down);
	174
7e141834	175	ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
b2ac5d75	176
7e141834	177	writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M),
a2c49e7b	178	timer_base + TIMER_CTL_REG(0));
b2ac5d75	179
119fd635	180	ret = setup_irq(irq, &sun4i_timer_irq);
b2ac5d75 MR	181	if (ret)
	182	pr_warn("failed to setup irq %d\n", irq);
	183
	184	/* Enable timer0 interrupt */
04981731 MR	185	val = readl(timer_base + TIMER_IRQ_EN_REG);
04981731 MR	186	writel(val \| TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
b2ac5d75	187
119fd635	188	sun4i_clockevent.cpumask = cpumask_of(0);
b2ac5d75	189
c2b852f7 MR	190	clockevents_config_and_register(&sun4i_clockevent, rate, 0x1,
c2b852f7 MR	191	0xffffffff);
b2ac5d75	192	}
119fd635 MR	193	CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
119fd635 MR	194	sun4i_timer_init);