Commit | Line | Data |
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6fe9cbd1 GC |
1 | /* |
2 | * Marvell Armada 370/XP SoC timer handling. | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Lior Amsalem <alior@marvell.com> | |
7 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
8 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
9 | * | |
10 | * This file is licensed under the terms of the GNU General Public | |
11 | * License version 2. This program is licensed "as is" without any | |
12 | * warranty of any kind, whether express or implied. | |
13 | * | |
14 | * Timer 0 is used as free-running clocksource, while timer 1 is | |
15 | * used as clock_event_device. | |
7cd6392c EG |
16 | * |
17 | * --- | |
18 | * Clocksource driver for Armada 370 and Armada XP SoC. | |
19 | * This driver implements one compatible string for each SoC, given | |
20 | * each has its own characteristics: | |
21 | * | |
22 | * * Armada 370 has no 25 MHz fixed timer. | |
23 | * | |
24 | * * Armada XP cannot work properly without such 25 MHz fixed timer as | |
25 | * doing otherwise leads to using a clocksource whose frequency varies | |
26 | * when doing cpufreq frequency changes. | |
27 | * | |
28 | * See Documentation/devicetree/bindings/timer/marvell,armada-370-xp-timer.txt | |
6fe9cbd1 GC |
29 | */ |
30 | ||
31 | #include <linux/init.h> | |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/kernel.h> | |
307c2bf4 | 34 | #include <linux/clk.h> |
5ddb6d21 | 35 | #include <linux/cpu.h> |
6fe9cbd1 GC |
36 | #include <linux/timer.h> |
37 | #include <linux/clockchips.h> | |
38 | #include <linux/interrupt.h> | |
39 | #include <linux/of.h> | |
40 | #include <linux/of_irq.h> | |
41 | #include <linux/of_address.h> | |
42 | #include <linux/irq.h> | |
43 | #include <linux/module.h> | |
38ff87f7 | 44 | #include <linux/sched_clock.h> |
ddd3f69f | 45 | #include <linux/percpu.h> |
f9a49ab5 | 46 | #include <linux/syscore_ops.h> |
6fe9cbd1 | 47 | |
cb0f2538 RK |
48 | #include <asm/delay.h> |
49 | ||
6fe9cbd1 GC |
50 | /* |
51 | * Timer block registers. | |
52 | */ | |
53 | #define TIMER_CTRL_OFF 0x0000 | |
ad48bd61 EG |
54 | #define TIMER0_EN BIT(0) |
55 | #define TIMER0_RELOAD_EN BIT(1) | |
56 | #define TIMER0_25MHZ BIT(11) | |
6fe9cbd1 | 57 | #define TIMER0_DIV(div) ((div) << 19) |
ad48bd61 EG |
58 | #define TIMER1_EN BIT(2) |
59 | #define TIMER1_RELOAD_EN BIT(3) | |
60 | #define TIMER1_25MHZ BIT(12) | |
6fe9cbd1 GC |
61 | #define TIMER1_DIV(div) ((div) << 22) |
62 | #define TIMER_EVENTS_STATUS 0x0004 | |
63 | #define TIMER0_CLR_MASK (~0x1) | |
64 | #define TIMER1_CLR_MASK (~0x100) | |
65 | #define TIMER0_RELOAD_OFF 0x0010 | |
66 | #define TIMER0_VAL_OFF 0x0014 | |
67 | #define TIMER1_RELOAD_OFF 0x0018 | |
68 | #define TIMER1_VAL_OFF 0x001c | |
69 | ||
ddd3f69f | 70 | #define LCL_TIMER_EVENTS_STATUS 0x0028 |
6fe9cbd1 GC |
71 | /* Global timers are connected to the coherency fabric clock, and the |
72 | below divider reduces their incrementing frequency. */ | |
73 | #define TIMER_DIVIDER_SHIFT 5 | |
74 | #define TIMER_DIVIDER (1 << TIMER_DIVIDER_SHIFT) | |
75 | ||
76 | /* | |
77 | * SoC-specific data. | |
78 | */ | |
ddd3f69f GC |
79 | static void __iomem *timer_base, *local_base; |
80 | static unsigned int timer_clk; | |
81 | static bool timer25Mhz = true; | |
08cb8e46 | 82 | static u32 enable_mask; |
6fe9cbd1 GC |
83 | |
84 | /* | |
85 | * Number of timer ticks per jiffy. | |
86 | */ | |
87 | static u32 ticks_per_jiffy; | |
88 | ||
5ddb6d21 | 89 | static struct clock_event_device __percpu *armada_370_xp_evt; |
ddd3f69f | 90 | |
3579698e EG |
91 | static void local_timer_ctrl_clrset(u32 clr, u32 set) |
92 | { | |
93 | writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set, | |
94 | local_base + TIMER_CTRL_OFF); | |
95 | } | |
ddd3f69f | 96 | |
d9dbcbe0 | 97 | static u64 notrace armada_370_xp_read_sched_clock(void) |
6fe9cbd1 GC |
98 | { |
99 | return ~readl(timer_base + TIMER0_VAL_OFF); | |
100 | } | |
101 | ||
102 | /* | |
103 | * Clockevent handling. | |
104 | */ | |
105 | static int | |
106 | armada_370_xp_clkevt_next_event(unsigned long delta, | |
107 | struct clock_event_device *dev) | |
108 | { | |
6fe9cbd1 GC |
109 | /* |
110 | * Clear clockevent timer interrupt. | |
111 | */ | |
ddd3f69f | 112 | writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS); |
6fe9cbd1 GC |
113 | |
114 | /* | |
115 | * Setup new clockevent timer value. | |
116 | */ | |
ddd3f69f | 117 | writel(delta, local_base + TIMER0_VAL_OFF); |
6fe9cbd1 GC |
118 | |
119 | /* | |
120 | * Enable the timer. | |
121 | */ | |
08cb8e46 | 122 | local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask); |
6fe9cbd1 GC |
123 | return 0; |
124 | } | |
125 | ||
d96f4412 | 126 | static int armada_370_xp_clkevt_shutdown(struct clock_event_device *evt) |
6fe9cbd1 | 127 | { |
d96f4412 VK |
128 | /* |
129 | * Disable timer. | |
130 | */ | |
131 | local_timer_ctrl_clrset(TIMER0_EN, 0); | |
132 | ||
133 | /* | |
134 | * ACK pending timer interrupt. | |
135 | */ | |
136 | writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS); | |
137 | return 0; | |
138 | } | |
139 | ||
140 | static int armada_370_xp_clkevt_set_periodic(struct clock_event_device *evt) | |
141 | { | |
142 | /* | |
143 | * Setup timer to fire at 1/HZ intervals. | |
144 | */ | |
145 | writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF); | |
146 | writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF); | |
147 | ||
148 | /* | |
149 | * Enable timer. | |
150 | */ | |
151 | local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask); | |
152 | return 0; | |
6fe9cbd1 GC |
153 | } |
154 | ||
5ddb6d21 | 155 | static int armada_370_xp_clkevt_irq; |
6fe9cbd1 GC |
156 | |
157 | static irqreturn_t armada_370_xp_timer_interrupt(int irq, void *dev_id) | |
158 | { | |
159 | /* | |
160 | * ACK timer interrupt and call event handler. | |
161 | */ | |
5ddb6d21 | 162 | struct clock_event_device *evt = dev_id; |
6fe9cbd1 | 163 | |
ddd3f69f GC |
164 | writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS); |
165 | evt->event_handler(evt); | |
6fe9cbd1 GC |
166 | |
167 | return IRQ_HANDLED; | |
168 | } | |
169 | ||
ddd3f69f GC |
170 | /* |
171 | * Setup the local clock events for a CPU. | |
172 | */ | |
8c37bb3a | 173 | static int armada_370_xp_timer_setup(struct clock_event_device *evt) |
ddd3f69f | 174 | { |
3579698e | 175 | u32 clr = 0, set = 0; |
ddd3f69f GC |
176 | int cpu = smp_processor_id(); |
177 | ||
ddd3f69f | 178 | if (timer25Mhz) |
3579698e | 179 | set = TIMER0_25MHZ; |
ddd3f69f | 180 | else |
3579698e EG |
181 | clr = TIMER0_25MHZ; |
182 | local_timer_ctrl_clrset(clr, set); | |
ddd3f69f | 183 | |
5ddb6d21 SB |
184 | evt->name = "armada_370_xp_per_cpu_tick", |
185 | evt->features = CLOCK_EVT_FEAT_ONESHOT | | |
186 | CLOCK_EVT_FEAT_PERIODIC; | |
187 | evt->shift = 32, | |
188 | evt->rating = 300, | |
ddd3f69f | 189 | evt->set_next_event = armada_370_xp_clkevt_next_event, |
d96f4412 VK |
190 | evt->set_state_shutdown = armada_370_xp_clkevt_shutdown; |
191 | evt->set_state_periodic = armada_370_xp_clkevt_set_periodic; | |
192 | evt->set_state_oneshot = armada_370_xp_clkevt_shutdown; | |
193 | evt->tick_resume = armada_370_xp_clkevt_shutdown; | |
5ddb6d21 | 194 | evt->irq = armada_370_xp_clkevt_irq; |
ddd3f69f GC |
195 | evt->cpumask = cpumask_of(cpu); |
196 | ||
ddd3f69f GC |
197 | clockevents_config_and_register(evt, timer_clk, 1, 0xfffffffe); |
198 | enable_percpu_irq(evt->irq, 0); | |
199 | ||
200 | return 0; | |
201 | } | |
202 | ||
47dcd356 | 203 | static void armada_370_xp_timer_stop(struct clock_event_device *evt) |
ddd3f69f | 204 | { |
d96f4412 | 205 | evt->set_state_shutdown(evt); |
ddd3f69f GC |
206 | disable_percpu_irq(evt->irq); |
207 | } | |
208 | ||
47dcd356 | 209 | static int armada_370_xp_timer_cpu_notify(struct notifier_block *self, |
5ddb6d21 SB |
210 | unsigned long action, void *hcpu) |
211 | { | |
212 | /* | |
213 | * Grab cpu pointer in each case to avoid spurious | |
214 | * preemptible warnings | |
215 | */ | |
216 | switch (action & ~CPU_TASKS_FROZEN) { | |
217 | case CPU_STARTING: | |
218 | armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt)); | |
219 | break; | |
220 | case CPU_DYING: | |
221 | armada_370_xp_timer_stop(this_cpu_ptr(armada_370_xp_evt)); | |
222 | break; | |
223 | } | |
224 | ||
225 | return NOTIFY_OK; | |
226 | } | |
227 | ||
47dcd356 | 228 | static struct notifier_block armada_370_xp_timer_cpu_nb = { |
5ddb6d21 | 229 | .notifier_call = armada_370_xp_timer_cpu_notify, |
6fe9cbd1 GC |
230 | }; |
231 | ||
f9a49ab5 TP |
232 | static u32 timer0_ctrl_reg, timer0_local_ctrl_reg; |
233 | ||
234 | static int armada_370_xp_timer_suspend(void) | |
235 | { | |
236 | timer0_ctrl_reg = readl(timer_base + TIMER_CTRL_OFF); | |
237 | timer0_local_ctrl_reg = readl(local_base + TIMER_CTRL_OFF); | |
238 | return 0; | |
239 | } | |
240 | ||
241 | static void armada_370_xp_timer_resume(void) | |
242 | { | |
243 | writel(0xffffffff, timer_base + TIMER0_VAL_OFF); | |
244 | writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); | |
245 | writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF); | |
246 | writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF); | |
247 | } | |
248 | ||
2c436e46 | 249 | static struct syscore_ops armada_370_xp_timer_syscore_ops = { |
f9a49ab5 TP |
250 | .suspend = armada_370_xp_timer_suspend, |
251 | .resume = armada_370_xp_timer_resume, | |
252 | }; | |
253 | ||
cb0f2538 RK |
254 | static unsigned long armada_370_delay_timer_read(void) |
255 | { | |
256 | return ~readl(timer_base + TIMER0_VAL_OFF); | |
257 | } | |
258 | ||
259 | static struct delay_timer armada_370_delay_timer = { | |
260 | .read_current_timer = armada_370_delay_timer_read, | |
261 | }; | |
262 | ||
12549e27 | 263 | static int __init armada_370_xp_timer_common_init(struct device_node *np) |
6fe9cbd1 | 264 | { |
3579698e | 265 | u32 clr = 0, set = 0; |
ddd3f69f GC |
266 | int res; |
267 | ||
6fe9cbd1 | 268 | timer_base = of_iomap(np, 0); |
12549e27 DL |
269 | if (!timer_base) { |
270 | pr_err("Failed to iomap"); | |
271 | return -ENXIO; | |
272 | } | |
273 | ||
ddd3f69f | 274 | local_base = of_iomap(np, 1); |
12549e27 DL |
275 | if (!local_base) { |
276 | pr_err("Failed to iomap"); | |
277 | return -ENXIO; | |
278 | } | |
6fe9cbd1 | 279 | |
08cb8e46 | 280 | if (timer25Mhz) { |
a4ae54f9 | 281 | set = TIMER0_25MHZ; |
08cb8e46 EG |
282 | enable_mask = TIMER0_EN; |
283 | } else { | |
3579698e | 284 | clr = TIMER0_25MHZ; |
08cb8e46 EG |
285 | enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT); |
286 | } | |
c8af34b4 | 287 | atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set); |
3579698e | 288 | local_timer_ctrl_clrset(clr, set); |
6fe9cbd1 | 289 | |
ddd3f69f GC |
290 | /* |
291 | * We use timer 0 as clocksource, and private(local) timer 0 | |
292 | * for clockevents | |
293 | */ | |
5ddb6d21 | 294 | armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4); |
6fe9cbd1 GC |
295 | |
296 | ticks_per_jiffy = (timer_clk + HZ / 2) / HZ; | |
297 | ||
6fe9cbd1 GC |
298 | /* |
299 | * Setup free-running clocksource timer (interrupts | |
300 | * disabled). | |
301 | */ | |
302 | writel(0xffffffff, timer_base + TIMER0_VAL_OFF); | |
303 | writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); | |
304 | ||
c8af34b4 EG |
305 | atomic_io_modify(timer_base + TIMER_CTRL_OFF, |
306 | TIMER0_RELOAD_EN | enable_mask, | |
307 | TIMER0_RELOAD_EN | enable_mask); | |
6fe9cbd1 | 308 | |
cb0f2538 RK |
309 | armada_370_delay_timer.freq = timer_clk; |
310 | register_current_timer_delay(&armada_370_delay_timer); | |
311 | ||
c813eff0 EG |
312 | /* |
313 | * Set scale and timer for sched_clock. | |
314 | */ | |
315 | sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk); | |
316 | ||
12549e27 DL |
317 | res = clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, |
318 | "armada_370_xp_clocksource", | |
319 | timer_clk, 300, 32, clocksource_mmio_readl_down); | |
320 | if (res) { | |
321 | pr_err("Failed to initialize clocksource mmio"); | |
322 | return res; | |
323 | } | |
6fe9cbd1 | 324 | |
5ddb6d21 | 325 | register_cpu_notifier(&armada_370_xp_timer_cpu_nb); |
6fe9cbd1 | 326 | |
5ddb6d21 | 327 | armada_370_xp_evt = alloc_percpu(struct clock_event_device); |
12549e27 DL |
328 | if (!armada_370_xp_evt) |
329 | return -ENOMEM; | |
ddd3f69f GC |
330 | |
331 | /* | |
332 | * Setup clockevent timer (interrupt-driven). | |
333 | */ | |
5ddb6d21 | 334 | res = request_percpu_irq(armada_370_xp_clkevt_irq, |
ddd3f69f | 335 | armada_370_xp_timer_interrupt, |
5ddb6d21 SB |
336 | "armada_370_xp_per_cpu_tick", |
337 | armada_370_xp_evt); | |
338 | /* Immediately configure the timer on the boot CPU */ | |
12549e27 DL |
339 | if (res) { |
340 | pr_err("Failed to request percpu irq"); | |
341 | return res; | |
342 | } | |
343 | ||
344 | res = armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt)); | |
1d661bf5 | 345 | if (res) { |
12549e27 DL |
346 | pr_err("Failed to setup timer"); |
347 | return res; | |
348 | } | |
f9a49ab5 TP |
349 | |
350 | register_syscore_ops(&armada_370_xp_timer_syscore_ops); | |
12549e27 DL |
351 | |
352 | return 0; | |
ddd3f69f | 353 | } |
7cd6392c | 354 | |
12549e27 | 355 | static int __init armada_xp_timer_init(struct device_node *np) |
7cd6392c | 356 | { |
5e9fe6cb | 357 | struct clk *clk = of_clk_get_by_name(np, "fixed"); |
12549e27 DL |
358 | int ret; |
359 | ||
360 | clk = of_clk_get(np, 0); | |
361 | if (IS_ERR(clk)) { | |
362 | pr_err("Failed to get clock"); | |
363 | return PTR_ERR(clk); | |
364 | } | |
365 | ||
366 | ret = clk_prepare_enable(clk); | |
367 | if (ret) | |
368 | return ret; | |
5e9fe6cb | 369 | |
5e9fe6cb | 370 | timer_clk = clk_get_rate(clk); |
7cd6392c | 371 | |
12549e27 | 372 | return armada_370_xp_timer_common_init(np); |
7cd6392c | 373 | } |
177cf6e5 | 374 | CLOCKSOURCE_OF_DECLARE(armada_xp, "marvell,armada-xp-timer", |
7cd6392c EG |
375 | armada_xp_timer_init); |
376 | ||
12549e27 | 377 | static int __init armada_375_timer_init(struct device_node *np) |
4a22d9c9 EG |
378 | { |
379 | struct clk *clk; | |
12549e27 | 380 | int ret; |
4a22d9c9 EG |
381 | |
382 | clk = of_clk_get_by_name(np, "fixed"); | |
383 | if (!IS_ERR(clk)) { | |
12549e27 DL |
384 | ret = clk_prepare_enable(clk); |
385 | if (ret) | |
386 | return ret; | |
4a22d9c9 EG |
387 | timer_clk = clk_get_rate(clk); |
388 | } else { | |
389 | ||
390 | /* | |
391 | * This fallback is required in order to retain proper | |
392 | * devicetree backwards compatibility. | |
393 | */ | |
394 | clk = of_clk_get(np, 0); | |
395 | ||
396 | /* Must have at least a clock */ | |
12549e27 DL |
397 | if (IS_ERR(clk)) { |
398 | pr_err("Failed to get clock"); | |
399 | return PTR_ERR(clk); | |
400 | } | |
401 | ||
402 | ret = clk_prepare_enable(clk); | |
403 | if (ret) | |
404 | return ret; | |
405 | ||
4a22d9c9 EG |
406 | timer_clk = clk_get_rate(clk) / TIMER_DIVIDER; |
407 | timer25Mhz = false; | |
408 | } | |
409 | ||
12549e27 | 410 | return armada_370_xp_timer_common_init(np); |
4a22d9c9 | 411 | } |
177cf6e5 | 412 | CLOCKSOURCE_OF_DECLARE(armada_375, "marvell,armada-375-timer", |
4a22d9c9 EG |
413 | armada_375_timer_init); |
414 | ||
12549e27 | 415 | static int __init armada_370_timer_init(struct device_node *np) |
7cd6392c | 416 | { |
12549e27 DL |
417 | struct clk *clk; |
418 | int ret; | |
419 | ||
420 | clk = of_clk_get(np, 0); | |
421 | if (IS_ERR(clk)) { | |
422 | pr_err("Failed to get clock"); | |
423 | return PTR_ERR(clk); | |
424 | } | |
425 | ||
426 | ret = clk_prepare_enable(clk); | |
427 | if (ret) | |
428 | return ret; | |
7cd6392c | 429 | |
7cd6392c EG |
430 | timer_clk = clk_get_rate(clk) / TIMER_DIVIDER; |
431 | timer25Mhz = false; | |
432 | ||
12549e27 | 433 | return armada_370_xp_timer_common_init(np); |
ddd3f69f | 434 | } |
177cf6e5 | 435 | CLOCKSOURCE_OF_DECLARE(armada_370, "marvell,armada-370-timer", |
7cd6392c | 436 | armada_370_timer_init); |