Commit | Line | Data |
---|---|---|
1a0ed732 | 1 | /* |
ad48ce74 | 2 | * at91sam926x_time.c - Periodic Interval Timer (PIT) for at91sam926x |
1a0ed732 AV |
3 | * |
4 | * Copyright (C) 2005-2006 M. Amine SAYA, ATMEL Rousset, France | |
5 | * Revision 2005 M. Nicolas Diremdjian, ATMEL Rousset, France | |
ad48ce74 | 6 | * Converted to ClockSource/ClockEvents by David Brownell. |
1a0ed732 AV |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
52c3ffb0 | 12 | |
cffbfe63 MR |
13 | #define pr_fmt(fmt) "AT91: PIT: " fmt |
14 | ||
52c3ffb0 MR |
15 | #include <linux/clk.h> |
16 | #include <linux/clockchips.h> | |
1a0ed732 AV |
17 | #include <linux/interrupt.h> |
18 | #include <linux/irq.h> | |
19 | #include <linux/kernel.h> | |
23fa648f JCPV |
20 | #include <linux/of.h> |
21 | #include <linux/of_address.h> | |
22 | #include <linux/of_irq.h> | |
64568d1d | 23 | #include <linux/slab.h> |
1a0ed732 | 24 | |
ffe5cd8e | 25 | #define AT91_PIT_MR 0x00 /* Mode Register */ |
52c3ffb0 MR |
26 | #define AT91_PIT_PITIEN BIT(25) /* Timer Interrupt Enable */ |
27 | #define AT91_PIT_PITEN BIT(24) /* Timer Enabled */ | |
28 | #define AT91_PIT_PIV GENMASK(19, 0) /* Periodic Interval Value */ | |
ffe5cd8e JCPV |
29 | |
30 | #define AT91_PIT_SR 0x04 /* Status Register */ | |
52c3ffb0 | 31 | #define AT91_PIT_PITS BIT(0) /* Timer Status */ |
ffe5cd8e JCPV |
32 | |
33 | #define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */ | |
34 | #define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */ | |
52c3ffb0 MR |
35 | #define AT91_PIT_PICNT GENMASK(31, 20) /* Interval Counter */ |
36 | #define AT91_PIT_CPIV GENMASK(19, 0) /* Inverval Value */ | |
1a0ed732 AV |
37 | |
38 | #define PIT_CPIV(x) ((x) & AT91_PIT_CPIV) | |
39 | #define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20) | |
40 | ||
64568d1d MR |
41 | struct pit_data { |
42 | struct clock_event_device clkevt; | |
43 | struct clocksource clksrc; | |
ad48ce74 | 44 | |
64568d1d MR |
45 | void __iomem *base; |
46 | u32 cycle; | |
47 | u32 cnt; | |
48 | unsigned int irq; | |
49 | struct clk *mck; | |
50 | }; | |
51 | ||
52 | static inline struct pit_data *clksrc_to_pit_data(struct clocksource *clksrc) | |
4ab0c599 | 53 | { |
64568d1d | 54 | return container_of(clksrc, struct pit_data, clksrc); |
4ab0c599 JCPV |
55 | } |
56 | ||
64568d1d | 57 | static inline struct pit_data *clkevt_to_pit_data(struct clock_event_device *clkevt) |
4ab0c599 | 58 | { |
64568d1d MR |
59 | return container_of(clkevt, struct pit_data, clkevt); |
60 | } | |
61 | ||
62 | static inline unsigned int pit_read(void __iomem *base, unsigned int reg_offset) | |
63 | { | |
4806c87f | 64 | return readl_relaxed(base + reg_offset); |
64568d1d MR |
65 | } |
66 | ||
67 | static inline void pit_write(void __iomem *base, unsigned int reg_offset, unsigned long value) | |
68 | { | |
4806c87f | 69 | writel_relaxed(value, base + reg_offset); |
4ab0c599 | 70 | } |
ad48ce74 | 71 | |
1a0ed732 | 72 | /* |
ad48ce74 AV |
73 | * Clocksource: just a monotonic counter of MCK/16 cycles. |
74 | * We don't care whether or not PIT irqs are enabled. | |
1a0ed732 | 75 | */ |
8e19608e | 76 | static cycle_t read_pit_clk(struct clocksource *cs) |
1a0ed732 | 77 | { |
64568d1d | 78 | struct pit_data *data = clksrc_to_pit_data(cs); |
ad48ce74 AV |
79 | unsigned long flags; |
80 | u32 elapsed; | |
81 | u32 t; | |
82 | ||
83 | raw_local_irq_save(flags); | |
64568d1d MR |
84 | elapsed = data->cnt; |
85 | t = pit_read(data->base, AT91_PIT_PIIR); | |
ad48ce74 AV |
86 | raw_local_irq_restore(flags); |
87 | ||
64568d1d | 88 | elapsed += PIT_PICNT(t) * data->cycle; |
ad48ce74 AV |
89 | elapsed += PIT_CPIV(t); |
90 | return elapsed; | |
91 | } | |
92 | ||
85250fb8 VK |
93 | static int pit_clkevt_shutdown(struct clock_event_device *dev) |
94 | { | |
95 | struct pit_data *data = clkevt_to_pit_data(dev); | |
96 | ||
97 | /* disable irq, leaving the clocksource active */ | |
98 | pit_write(data->base, AT91_PIT_MR, (data->cycle - 1) | AT91_PIT_PITEN); | |
99 | return 0; | |
100 | } | |
101 | ||
ad48ce74 AV |
102 | /* |
103 | * Clockevent device: interrupts every 1/HZ (== pit_cycles * MCK/16) | |
104 | */ | |
85250fb8 | 105 | static int pit_clkevt_set_periodic(struct clock_event_device *dev) |
ad48ce74 | 106 | { |
64568d1d MR |
107 | struct pit_data *data = clkevt_to_pit_data(dev); |
108 | ||
85250fb8 VK |
109 | /* update clocksource counter */ |
110 | data->cnt += data->cycle * PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR)); | |
111 | pit_write(data->base, AT91_PIT_MR, | |
112 | (data->cycle - 1) | AT91_PIT_PITEN | AT91_PIT_PITIEN); | |
113 | return 0; | |
1a0ed732 AV |
114 | } |
115 | ||
49356ae9 SW |
116 | static void at91sam926x_pit_suspend(struct clock_event_device *cedev) |
117 | { | |
64568d1d MR |
118 | struct pit_data *data = clkevt_to_pit_data(cedev); |
119 | ||
49356ae9 | 120 | /* Disable timer */ |
64568d1d | 121 | pit_write(data->base, AT91_PIT_MR, 0); |
49356ae9 SW |
122 | } |
123 | ||
64568d1d | 124 | static void at91sam926x_pit_reset(struct pit_data *data) |
49356ae9 SW |
125 | { |
126 | /* Disable timer and irqs */ | |
64568d1d | 127 | pit_write(data->base, AT91_PIT_MR, 0); |
49356ae9 SW |
128 | |
129 | /* Clear any pending interrupts, wait for PIT to stop counting */ | |
64568d1d | 130 | while (PIT_CPIV(pit_read(data->base, AT91_PIT_PIVR)) != 0) |
49356ae9 SW |
131 | cpu_relax(); |
132 | ||
133 | /* Start PIT but don't enable IRQ */ | |
64568d1d MR |
134 | pit_write(data->base, AT91_PIT_MR, |
135 | (data->cycle - 1) | AT91_PIT_PITEN); | |
49356ae9 SW |
136 | } |
137 | ||
138 | static void at91sam926x_pit_resume(struct clock_event_device *cedev) | |
139 | { | |
64568d1d | 140 | struct pit_data *data = clkevt_to_pit_data(cedev); |
ad48ce74 | 141 | |
64568d1d MR |
142 | at91sam926x_pit_reset(data); |
143 | } | |
ad48ce74 | 144 | |
1a0ed732 AV |
145 | /* |
146 | * IRQ handler for the timer. | |
147 | */ | |
ad48ce74 | 148 | static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id) |
1a0ed732 | 149 | { |
64568d1d MR |
150 | struct pit_data *data = dev_id; |
151 | ||
501d7038 UKK |
152 | /* |
153 | * irqs should be disabled here, but as the irq is shared they are only | |
154 | * guaranteed to be off if the timer irq is registered first. | |
155 | */ | |
156 | WARN_ON_ONCE(!irqs_disabled()); | |
1a0ed732 | 157 | |
ad48ce74 | 158 | /* The PIT interrupt may be disabled, and is shared */ |
85250fb8 | 159 | if (clockevent_state_periodic(&data->clkevt) && |
64568d1d | 160 | (pit_read(data->base, AT91_PIT_SR) & AT91_PIT_PITS)) { |
ad48ce74 AV |
161 | unsigned nr_ticks; |
162 | ||
163 | /* Get number of ticks performed before irq, and ack it */ | |
64568d1d | 164 | nr_ticks = PIT_PICNT(pit_read(data->base, AT91_PIT_PIVR)); |
1a0ed732 | 165 | do { |
64568d1d MR |
166 | data->cnt += data->cycle; |
167 | data->clkevt.event_handler(&data->clkevt); | |
1a0ed732 AV |
168 | nr_ticks--; |
169 | } while (nr_ticks); | |
170 | ||
1a0ed732 | 171 | return IRQ_HANDLED; |
ad48ce74 AV |
172 | } |
173 | ||
174 | return IRQ_NONE; | |
1a0ed732 AV |
175 | } |
176 | ||
1a0ed732 | 177 | /* |
ad48ce74 | 178 | * Set up both clocksource and clockevent support. |
1a0ed732 | 179 | */ |
64568d1d | 180 | static void __init at91sam926x_pit_common_init(struct pit_data *data) |
1a0ed732 | 181 | { |
ad48ce74 AV |
182 | unsigned long pit_rate; |
183 | unsigned bits; | |
986c2657 | 184 | int ret; |
ad48ce74 AV |
185 | |
186 | /* | |
187 | * Use our actual MCK to figure out how many MCK/16 ticks per | |
188 | * 1/HZ period (instead of a compile-time constant LATCH). | |
189 | */ | |
64568d1d MR |
190 | pit_rate = clk_get_rate(data->mck) / 16; |
191 | data->cycle = DIV_ROUND_CLOSEST(pit_rate, HZ); | |
192 | WARN_ON(((data->cycle - 1) & ~AT91_PIT_PIV) != 0); | |
1a0ed732 | 193 | |
ad48ce74 | 194 | /* Initialize and enable the timer */ |
64568d1d | 195 | at91sam926x_pit_reset(data); |
ad48ce74 AV |
196 | |
197 | /* | |
198 | * Register clocksource. The high order bits of PIV are unused, | |
199 | * so this isn't a 32-bit counter unless we get clockevent irqs. | |
200 | */ | |
64568d1d MR |
201 | bits = 12 /* PICNT */ + ilog2(data->cycle) /* PIV */; |
202 | data->clksrc.mask = CLOCKSOURCE_MASK(bits); | |
203 | data->clksrc.name = "pit"; | |
204 | data->clksrc.rating = 175; | |
005e5627 DL |
205 | data->clksrc.read = read_pit_clk; |
206 | data->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; | |
64568d1d | 207 | clocksource_register_hz(&data->clksrc, pit_rate); |
ad48ce74 AV |
208 | |
209 | /* Set up irq handler */ | |
64568d1d | 210 | ret = request_irq(data->irq, at91sam926x_pit_interrupt, |
7f282e01 | 211 | IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL, |
64568d1d | 212 | "at91_tick", data); |
986c2657 | 213 | if (ret) |
cffbfe63 | 214 | panic(pr_fmt("Unable to setup IRQ\n")); |
ad48ce74 AV |
215 | |
216 | /* Set up and register clockevents */ | |
64568d1d MR |
217 | data->clkevt.name = "pit"; |
218 | data->clkevt.features = CLOCK_EVT_FEAT_PERIODIC; | |
219 | data->clkevt.shift = 32; | |
220 | data->clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, data->clkevt.shift); | |
221 | data->clkevt.rating = 100; | |
222 | data->clkevt.cpumask = cpumask_of(0); | |
223 | ||
85250fb8 VK |
224 | data->clkevt.set_state_shutdown = pit_clkevt_shutdown; |
225 | data->clkevt.set_state_periodic = pit_clkevt_set_periodic; | |
64568d1d MR |
226 | data->clkevt.resume = at91sam926x_pit_resume; |
227 | data->clkevt.suspend = at91sam926x_pit_suspend; | |
228 | clockevents_register_device(&data->clkevt); | |
1a0ed732 AV |
229 | } |
230 | ||
f807a89c MR |
231 | static void __init at91sam926x_pit_dt_init(struct device_node *node) |
232 | { | |
64568d1d | 233 | struct pit_data *data; |
f807a89c | 234 | |
64568d1d MR |
235 | data = kzalloc(sizeof(*data), GFP_KERNEL); |
236 | if (!data) | |
237 | panic(pr_fmt("Unable to allocate memory\n")); | |
238 | ||
239 | data->base = of_iomap(node, 0); | |
240 | if (!data->base) | |
cffbfe63 | 241 | panic(pr_fmt("Could not map PIT address\n")); |
f807a89c | 242 | |
64568d1d MR |
243 | data->mck = of_clk_get(node, 0); |
244 | if (IS_ERR(data->mck)) | |
f807a89c | 245 | /* Fallback on clkdev for !CCF-based boards */ |
64568d1d | 246 | data->mck = clk_get(NULL, "mck"); |
f807a89c | 247 | |
64568d1d | 248 | if (IS_ERR(data->mck)) |
cffbfe63 | 249 | panic(pr_fmt("Unable to get mck clk\n")); |
f807a89c MR |
250 | |
251 | /* Get the interrupts property */ | |
64568d1d MR |
252 | data->irq = irq_of_parse_and_map(node, 0); |
253 | if (!data->irq) | |
cffbfe63 | 254 | panic(pr_fmt("Unable to get IRQ from DT\n")); |
f807a89c | 255 | |
64568d1d | 256 | at91sam926x_pit_common_init(data); |
f807a89c MR |
257 | } |
258 | CLOCKSOURCE_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit", | |
259 | at91sam926x_pit_dt_init); |