Commit | Line | Data |
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73a59c1c | 1 | /* |
9d041268 | 2 | * linux/arch/arm/mach-at91/at91rm9200_time.c |
73a59c1c SP |
3 | * |
4 | * Copyright (C) 2003 SAN People | |
5 | * Copyright (C) 2003 ATMEL | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
5e802dfa | 22 | #include <linux/kernel.h> |
73a59c1c | 23 | #include <linux/interrupt.h> |
07d265dd | 24 | #include <linux/irq.h> |
5e802dfa | 25 | #include <linux/clockchips.h> |
9fce85c7 | 26 | #include <linux/export.h> |
adf2edfd AB |
27 | #include <linux/mfd/syscon.h> |
28 | #include <linux/mfd/syscon/atmel-st.h> | |
454c46df | 29 | #include <linux/of_irq.h> |
adf2edfd | 30 | #include <linux/regmap.h> |
73a59c1c | 31 | |
963151f2 | 32 | static unsigned long last_crtr; |
5e802dfa DB |
33 | static u32 irqmask; |
34 | static struct clock_event_device clkevt; | |
adf2edfd | 35 | static struct regmap *regmap_st; |
963151f2 | 36 | |
0afb46b2 | 37 | #define AT91_SLOW_CLOCK 32768 |
2f5893cf JCPV |
38 | #define RM9200_TIMER_LATCH ((AT91_SLOW_CLOCK + HZ/2) / HZ) |
39 | ||
73a59c1c | 40 | /* |
5e802dfa DB |
41 | * The ST_CRTR is updated asynchronously to the master clock ... but |
42 | * the updates as seen by the CPU don't seem to be strictly monotonic. | |
43 | * Waiting until we read the same value twice avoids glitching. | |
73a59c1c | 44 | */ |
5e802dfa DB |
45 | static inline unsigned long read_CRTR(void) |
46 | { | |
adf2edfd | 47 | unsigned int x1, x2; |
73a59c1c | 48 | |
adf2edfd | 49 | regmap_read(regmap_st, AT91_ST_CRTR, &x1); |
73a59c1c | 50 | do { |
adf2edfd | 51 | regmap_read(regmap_st, AT91_ST_CRTR, &x2); |
5e802dfa DB |
52 | if (x1 == x2) |
53 | break; | |
54 | x1 = x2; | |
55 | } while (1); | |
73a59c1c SP |
56 | return x1; |
57 | } | |
58 | ||
73a59c1c SP |
59 | /* |
60 | * IRQ handler for the timer. | |
61 | */ | |
0cd61b68 | 62 | static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id) |
73a59c1c | 63 | { |
adf2edfd AB |
64 | u32 sr; |
65 | ||
66 | regmap_read(regmap_st, AT91_ST_SR, &sr); | |
67 | sr &= irqmask; | |
73a59c1c | 68 | |
501d7038 UKK |
69 | /* |
70 | * irqs should be disabled here, but as the irq is shared they are only | |
71 | * guaranteed to be off if the timer irq is registered first. | |
72 | */ | |
73 | WARN_ON_ONCE(!irqs_disabled()); | |
74 | ||
5e802dfa DB |
75 | /* simulate "oneshot" timer with alarm */ |
76 | if (sr & AT91_ST_ALMS) { | |
77 | clkevt.event_handler(&clkevt); | |
78 | return IRQ_HANDLED; | |
79 | } | |
73a59c1c | 80 | |
5e802dfa DB |
81 | /* periodic mode should handle delayed ticks */ |
82 | if (sr & AT91_ST_PITS) { | |
83 | u32 crtr = read_CRTR(); | |
73a59c1c | 84 | |
2f5893cf JCPV |
85 | while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) { |
86 | last_crtr += RM9200_TIMER_LATCH; | |
5e802dfa DB |
87 | clkevt.event_handler(&clkevt); |
88 | } | |
73a59c1c SP |
89 | return IRQ_HANDLED; |
90 | } | |
5e802dfa DB |
91 | |
92 | /* this irq is shared ... */ | |
93 | return IRQ_NONE; | |
73a59c1c SP |
94 | } |
95 | ||
8e19608e | 96 | static cycle_t read_clk32k(struct clocksource *cs) |
2a6f9902 | 97 | { |
5e802dfa DB |
98 | return read_CRTR(); |
99 | } | |
2a6f9902 | 100 | |
5e802dfa DB |
101 | static struct clocksource clk32k = { |
102 | .name = "32k_counter", | |
103 | .rating = 150, | |
104 | .read = read_clk32k, | |
105 | .mask = CLOCKSOURCE_MASK(20), | |
5e802dfa DB |
106 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
107 | }; | |
108 | ||
109 | static void | |
110 | clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev) | |
111 | { | |
adf2edfd AB |
112 | unsigned int val; |
113 | ||
5e802dfa | 114 | /* Disable and flush pending timer interrupts */ |
adf2edfd AB |
115 | regmap_write(regmap_st, AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS); |
116 | regmap_read(regmap_st, AT91_ST_SR, &val); | |
2a6f9902 | 117 | |
5e802dfa DB |
118 | last_crtr = read_CRTR(); |
119 | switch (mode) { | |
120 | case CLOCK_EVT_MODE_PERIODIC: | |
121 | /* PIT for periodic irqs; fixed rate of 1/HZ */ | |
122 | irqmask = AT91_ST_PITS; | |
adf2edfd | 123 | regmap_write(regmap_st, AT91_ST_PIMR, RM9200_TIMER_LATCH); |
5e802dfa DB |
124 | break; |
125 | case CLOCK_EVT_MODE_ONESHOT: | |
126 | /* ALM for oneshot irqs, set by next_event() | |
127 | * before 32 seconds have passed | |
128 | */ | |
129 | irqmask = AT91_ST_ALMS; | |
adf2edfd | 130 | regmap_write(regmap_st, AT91_ST_RTAR, last_crtr); |
5e802dfa DB |
131 | break; |
132 | case CLOCK_EVT_MODE_SHUTDOWN: | |
133 | case CLOCK_EVT_MODE_UNUSED: | |
134 | case CLOCK_EVT_MODE_RESUME: | |
135 | irqmask = 0; | |
136 | break; | |
137 | } | |
adf2edfd | 138 | regmap_write(regmap_st, AT91_ST_IER, irqmask); |
5e802dfa | 139 | } |
2a6f9902 | 140 | |
5e802dfa DB |
141 | static int |
142 | clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) | |
143 | { | |
5e802dfa DB |
144 | u32 alm; |
145 | int status = 0; | |
adf2edfd | 146 | unsigned int val; |
5e802dfa DB |
147 | |
148 | BUG_ON(delta < 2); | |
149 | ||
5e802dfa DB |
150 | /* The alarm IRQ uses absolute time (now+delta), not the relative |
151 | * time (delta) in our calling convention. Like all clockevents | |
152 | * using such "match" hardware, we have a race to defend against. | |
153 | * | |
154 | * Our defense here is to have set up the clockevent device so the | |
155 | * delta is at least two. That way we never end up writing RTAR | |
156 | * with the value then held in CRTR ... which would mean the match | |
157 | * wouldn't trigger until 32 seconds later, after CRTR wraps. | |
158 | */ | |
159 | alm = read_CRTR(); | |
160 | ||
161 | /* Cancel any pending alarm; flush any pending IRQ */ | |
adf2edfd AB |
162 | regmap_write(regmap_st, AT91_ST_RTAR, alm); |
163 | regmap_read(regmap_st, AT91_ST_SR, &val); | |
d100f259 | 164 | |
5e802dfa DB |
165 | /* Schedule alarm by writing RTAR. */ |
166 | alm += delta; | |
adf2edfd | 167 | regmap_write(regmap_st, AT91_ST_RTAR, alm); |
5e802dfa | 168 | |
5e802dfa | 169 | return status; |
2a6f9902 AV |
170 | } |
171 | ||
5e802dfa DB |
172 | static struct clock_event_device clkevt = { |
173 | .name = "at91_tick", | |
174 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
5e802dfa | 175 | .rating = 150, |
5e802dfa DB |
176 | .set_next_event = clkevt32k_next_event, |
177 | .set_mode = clkevt32k_mode, | |
178 | }; | |
179 | ||
73a59c1c | 180 | /* |
5e802dfa | 181 | * ST (system timer) module supports both clockevents and clocksource. |
73a59c1c | 182 | */ |
bbfc97e1 | 183 | static void __init atmel_st_timer_init(struct device_node *node) |
73a59c1c | 184 | { |
adf2edfd | 185 | unsigned int val; |
0afb46b2 | 186 | int irq, ret; |
adf2edfd AB |
187 | |
188 | regmap_st = syscon_node_to_regmap(node); | |
189 | if (IS_ERR(regmap_st)) | |
190 | panic(pr_fmt("Unable to get regmap\n")); | |
454c46df | 191 | |
5e802dfa | 192 | /* Disable all timer interrupts, and clear any pending ones */ |
adf2edfd | 193 | regmap_write(regmap_st, AT91_ST_IDR, |
5e802dfa | 194 | AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS); |
adf2edfd AB |
195 | regmap_read(regmap_st, AT91_ST_SR, &val); |
196 | ||
197 | /* Get the interrupts property */ | |
0afb46b2 AB |
198 | irq = irq_of_parse_and_map(node, 0); |
199 | if (!irq) | |
adf2edfd | 200 | panic(pr_fmt("Unable to get IRQ from DT\n")); |
73a59c1c | 201 | |
2a6f9902 | 202 | /* Make IRQs happen for the system timer */ |
0afb46b2 AB |
203 | ret = request_irq(irq, at91rm9200_timer_interrupt, |
204 | IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL, | |
205 | "at91_tick", regmap_st); | |
206 | if (ret) | |
207 | panic(pr_fmt("Unable to setup IRQ\n")); | |
73a59c1c | 208 | |
5e802dfa DB |
209 | /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used |
210 | * directly for the clocksource and all clockevents, after adjusting | |
211 | * its prescaler from the 1 Hz default. | |
212 | */ | |
adf2edfd | 213 | regmap_write(regmap_st, AT91_ST_RTMR, 1); |
73a59c1c | 214 | |
5e802dfa | 215 | /* Setup timer clockevent, with minimum of two ticks (important!!) */ |
320ab2b0 | 216 | clkevt.cpumask = cpumask_of(0); |
1c283531 UKK |
217 | clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK, |
218 | 2, AT91_ST_ALMV); | |
2a6f9902 | 219 | |
5e802dfa | 220 | /* register clocksource */ |
132b1632 | 221 | clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK); |
73a59c1c | 222 | } |
bbfc97e1 AB |
223 | CLOCKSOURCE_OF_DECLARE(atmel_st_timer, "atmel,at91rm9200-st", |
224 | atmel_st_timer_init); |