Commit | Line | Data |
---|---|---|
73a59c1c | 1 | /* |
9d041268 | 2 | * linux/arch/arm/mach-at91/at91rm9200_time.c |
73a59c1c SP |
3 | * |
4 | * Copyright (C) 2003 SAN People | |
5 | * Copyright (C) 2003 ATMEL | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
5e802dfa | 22 | #include <linux/kernel.h> |
73a59c1c | 23 | #include <linux/interrupt.h> |
07d265dd | 24 | #include <linux/irq.h> |
216ab8f1 | 25 | #include <linux/clk.h> |
5e802dfa | 26 | #include <linux/clockchips.h> |
9fce85c7 | 27 | #include <linux/export.h> |
adf2edfd AB |
28 | #include <linux/mfd/syscon.h> |
29 | #include <linux/mfd/syscon/atmel-st.h> | |
454c46df | 30 | #include <linux/of_irq.h> |
adf2edfd | 31 | #include <linux/regmap.h> |
73a59c1c | 32 | |
963151f2 | 33 | static unsigned long last_crtr; |
5e802dfa DB |
34 | static u32 irqmask; |
35 | static struct clock_event_device clkevt; | |
adf2edfd | 36 | static struct regmap *regmap_st; |
216ab8f1 | 37 | static int timer_latch; |
2f5893cf | 38 | |
73a59c1c | 39 | /* |
5e802dfa DB |
40 | * The ST_CRTR is updated asynchronously to the master clock ... but |
41 | * the updates as seen by the CPU don't seem to be strictly monotonic. | |
42 | * Waiting until we read the same value twice avoids glitching. | |
73a59c1c | 43 | */ |
5e802dfa DB |
44 | static inline unsigned long read_CRTR(void) |
45 | { | |
adf2edfd | 46 | unsigned int x1, x2; |
73a59c1c | 47 | |
adf2edfd | 48 | regmap_read(regmap_st, AT91_ST_CRTR, &x1); |
73a59c1c | 49 | do { |
adf2edfd | 50 | regmap_read(regmap_st, AT91_ST_CRTR, &x2); |
5e802dfa DB |
51 | if (x1 == x2) |
52 | break; | |
53 | x1 = x2; | |
54 | } while (1); | |
73a59c1c SP |
55 | return x1; |
56 | } | |
57 | ||
73a59c1c SP |
58 | /* |
59 | * IRQ handler for the timer. | |
60 | */ | |
0cd61b68 | 61 | static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id) |
73a59c1c | 62 | { |
adf2edfd AB |
63 | u32 sr; |
64 | ||
65 | regmap_read(regmap_st, AT91_ST_SR, &sr); | |
66 | sr &= irqmask; | |
73a59c1c | 67 | |
501d7038 UKK |
68 | /* |
69 | * irqs should be disabled here, but as the irq is shared they are only | |
70 | * guaranteed to be off if the timer irq is registered first. | |
71 | */ | |
72 | WARN_ON_ONCE(!irqs_disabled()); | |
73 | ||
5e802dfa DB |
74 | /* simulate "oneshot" timer with alarm */ |
75 | if (sr & AT91_ST_ALMS) { | |
76 | clkevt.event_handler(&clkevt); | |
77 | return IRQ_HANDLED; | |
78 | } | |
73a59c1c | 79 | |
5e802dfa DB |
80 | /* periodic mode should handle delayed ticks */ |
81 | if (sr & AT91_ST_PITS) { | |
82 | u32 crtr = read_CRTR(); | |
73a59c1c | 83 | |
216ab8f1 AB |
84 | while (((crtr - last_crtr) & AT91_ST_CRTV) >= timer_latch) { |
85 | last_crtr += timer_latch; | |
5e802dfa DB |
86 | clkevt.event_handler(&clkevt); |
87 | } | |
73a59c1c SP |
88 | return IRQ_HANDLED; |
89 | } | |
5e802dfa DB |
90 | |
91 | /* this irq is shared ... */ | |
92 | return IRQ_NONE; | |
73a59c1c SP |
93 | } |
94 | ||
8e19608e | 95 | static cycle_t read_clk32k(struct clocksource *cs) |
2a6f9902 | 96 | { |
5e802dfa DB |
97 | return read_CRTR(); |
98 | } | |
2a6f9902 | 99 | |
5e802dfa DB |
100 | static struct clocksource clk32k = { |
101 | .name = "32k_counter", | |
102 | .rating = 150, | |
103 | .read = read_clk32k, | |
104 | .mask = CLOCKSOURCE_MASK(20), | |
5e802dfa DB |
105 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
106 | }; | |
107 | ||
8ab28230 | 108 | static void clkdev32k_disable_and_flush_irq(void) |
5e802dfa | 109 | { |
adf2edfd AB |
110 | unsigned int val; |
111 | ||
5e802dfa | 112 | /* Disable and flush pending timer interrupts */ |
adf2edfd AB |
113 | regmap_write(regmap_st, AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS); |
114 | regmap_read(regmap_st, AT91_ST_SR, &val); | |
5e802dfa | 115 | last_crtr = read_CRTR(); |
8ab28230 VK |
116 | } |
117 | ||
118 | static int clkevt32k_shutdown(struct clock_event_device *evt) | |
119 | { | |
120 | clkdev32k_disable_and_flush_irq(); | |
121 | irqmask = 0; | |
122 | regmap_write(regmap_st, AT91_ST_IER, irqmask); | |
123 | return 0; | |
124 | } | |
125 | ||
126 | static int clkevt32k_set_oneshot(struct clock_event_device *dev) | |
127 | { | |
128 | clkdev32k_disable_and_flush_irq(); | |
129 | ||
130 | /* | |
131 | * ALM for oneshot irqs, set by next_event() | |
132 | * before 32 seconds have passed. | |
133 | */ | |
134 | irqmask = AT91_ST_ALMS; | |
135 | regmap_write(regmap_st, AT91_ST_RTAR, last_crtr); | |
adf2edfd | 136 | regmap_write(regmap_st, AT91_ST_IER, irqmask); |
8ab28230 VK |
137 | return 0; |
138 | } | |
139 | ||
140 | static int clkevt32k_set_periodic(struct clock_event_device *dev) | |
141 | { | |
142 | clkdev32k_disable_and_flush_irq(); | |
143 | ||
144 | /* PIT for periodic irqs; fixed rate of 1/HZ */ | |
145 | irqmask = AT91_ST_PITS; | |
216ab8f1 | 146 | regmap_write(regmap_st, AT91_ST_PIMR, timer_latch); |
8ab28230 VK |
147 | regmap_write(regmap_st, AT91_ST_IER, irqmask); |
148 | return 0; | |
5e802dfa | 149 | } |
2a6f9902 | 150 | |
5e802dfa DB |
151 | static int |
152 | clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) | |
153 | { | |
5e802dfa DB |
154 | u32 alm; |
155 | int status = 0; | |
adf2edfd | 156 | unsigned int val; |
5e802dfa DB |
157 | |
158 | BUG_ON(delta < 2); | |
159 | ||
5e802dfa DB |
160 | /* The alarm IRQ uses absolute time (now+delta), not the relative |
161 | * time (delta) in our calling convention. Like all clockevents | |
162 | * using such "match" hardware, we have a race to defend against. | |
163 | * | |
164 | * Our defense here is to have set up the clockevent device so the | |
165 | * delta is at least two. That way we never end up writing RTAR | |
166 | * with the value then held in CRTR ... which would mean the match | |
167 | * wouldn't trigger until 32 seconds later, after CRTR wraps. | |
168 | */ | |
169 | alm = read_CRTR(); | |
170 | ||
171 | /* Cancel any pending alarm; flush any pending IRQ */ | |
adf2edfd AB |
172 | regmap_write(regmap_st, AT91_ST_RTAR, alm); |
173 | regmap_read(regmap_st, AT91_ST_SR, &val); | |
d100f259 | 174 | |
5e802dfa DB |
175 | /* Schedule alarm by writing RTAR. */ |
176 | alm += delta; | |
adf2edfd | 177 | regmap_write(regmap_st, AT91_ST_RTAR, alm); |
5e802dfa | 178 | |
5e802dfa | 179 | return status; |
2a6f9902 AV |
180 | } |
181 | ||
5e802dfa | 182 | static struct clock_event_device clkevt = { |
8ab28230 VK |
183 | .name = "at91_tick", |
184 | .features = CLOCK_EVT_FEAT_PERIODIC | | |
185 | CLOCK_EVT_FEAT_ONESHOT, | |
186 | .rating = 150, | |
187 | .set_next_event = clkevt32k_next_event, | |
188 | .set_state_shutdown = clkevt32k_shutdown, | |
189 | .set_state_periodic = clkevt32k_set_periodic, | |
190 | .set_state_oneshot = clkevt32k_set_oneshot, | |
191 | .tick_resume = clkevt32k_shutdown, | |
5e802dfa DB |
192 | }; |
193 | ||
73a59c1c | 194 | /* |
5e802dfa | 195 | * ST (system timer) module supports both clockevents and clocksource. |
73a59c1c | 196 | */ |
bbfc97e1 | 197 | static void __init atmel_st_timer_init(struct device_node *node) |
73a59c1c | 198 | { |
216ab8f1 AB |
199 | struct clk *sclk; |
200 | unsigned int sclk_rate, val; | |
0afb46b2 | 201 | int irq, ret; |
adf2edfd AB |
202 | |
203 | regmap_st = syscon_node_to_regmap(node); | |
204 | if (IS_ERR(regmap_st)) | |
205 | panic(pr_fmt("Unable to get regmap\n")); | |
454c46df | 206 | |
5e802dfa | 207 | /* Disable all timer interrupts, and clear any pending ones */ |
adf2edfd | 208 | regmap_write(regmap_st, AT91_ST_IDR, |
5e802dfa | 209 | AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS); |
adf2edfd AB |
210 | regmap_read(regmap_st, AT91_ST_SR, &val); |
211 | ||
212 | /* Get the interrupts property */ | |
0afb46b2 AB |
213 | irq = irq_of_parse_and_map(node, 0); |
214 | if (!irq) | |
adf2edfd | 215 | panic(pr_fmt("Unable to get IRQ from DT\n")); |
73a59c1c | 216 | |
2a6f9902 | 217 | /* Make IRQs happen for the system timer */ |
0afb46b2 AB |
218 | ret = request_irq(irq, at91rm9200_timer_interrupt, |
219 | IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL, | |
220 | "at91_tick", regmap_st); | |
221 | if (ret) | |
222 | panic(pr_fmt("Unable to setup IRQ\n")); | |
73a59c1c | 223 | |
216ab8f1 AB |
224 | sclk = of_clk_get(node, 0); |
225 | if (IS_ERR(sclk)) | |
226 | panic(pr_fmt("Unable to get slow clock\n")); | |
227 | ||
228 | clk_prepare_enable(sclk); | |
229 | if (ret) | |
230 | panic(pr_fmt("Could not enable slow clock\n")); | |
231 | ||
232 | sclk_rate = clk_get_rate(sclk); | |
233 | if (!sclk_rate) | |
234 | panic(pr_fmt("Invalid slow clock rate\n")); | |
235 | timer_latch = (sclk_rate + HZ / 2) / HZ; | |
236 | ||
5e802dfa DB |
237 | /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used |
238 | * directly for the clocksource and all clockevents, after adjusting | |
239 | * its prescaler from the 1 Hz default. | |
240 | */ | |
adf2edfd | 241 | regmap_write(regmap_st, AT91_ST_RTMR, 1); |
73a59c1c | 242 | |
5e802dfa | 243 | /* Setup timer clockevent, with minimum of two ticks (important!!) */ |
320ab2b0 | 244 | clkevt.cpumask = cpumask_of(0); |
216ab8f1 | 245 | clockevents_config_and_register(&clkevt, sclk_rate, |
1c283531 | 246 | 2, AT91_ST_ALMV); |
2a6f9902 | 247 | |
5e802dfa | 248 | /* register clocksource */ |
216ab8f1 | 249 | clocksource_register_hz(&clk32k, sclk_rate); |
73a59c1c | 250 | } |
bbfc97e1 AB |
251 | CLOCKSOURCE_OF_DECLARE(atmel_st_timer, "atmel,at91rm9200-st", |
252 | atmel_st_timer_init); |