Commit | Line | Data |
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73a59c1c | 1 | /* |
9d041268 | 2 | * linux/arch/arm/mach-at91/at91rm9200_time.c |
73a59c1c SP |
3 | * |
4 | * Copyright (C) 2003 SAN People | |
5 | * Copyright (C) 2003 ATMEL | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
5e802dfa | 22 | #include <linux/kernel.h> |
73a59c1c | 23 | #include <linux/interrupt.h> |
07d265dd | 24 | #include <linux/irq.h> |
5e802dfa | 25 | #include <linux/clockchips.h> |
9fce85c7 | 26 | #include <linux/export.h> |
adf2edfd AB |
27 | #include <linux/mfd/syscon.h> |
28 | #include <linux/mfd/syscon/atmel-st.h> | |
454c46df | 29 | #include <linux/of_irq.h> |
adf2edfd | 30 | #include <linux/regmap.h> |
73a59c1c | 31 | |
73a59c1c SP |
32 | #include <asm/mach/time.h> |
33 | ||
ac11a1d4 | 34 | #include <mach/hardware.h> |
55d8baee | 35 | |
963151f2 | 36 | static unsigned long last_crtr; |
5e802dfa DB |
37 | static u32 irqmask; |
38 | static struct clock_event_device clkevt; | |
adf2edfd | 39 | static struct regmap *regmap_st; |
963151f2 | 40 | |
2f5893cf JCPV |
41 | #define RM9200_TIMER_LATCH ((AT91_SLOW_CLOCK + HZ/2) / HZ) |
42 | ||
73a59c1c | 43 | /* |
5e802dfa DB |
44 | * The ST_CRTR is updated asynchronously to the master clock ... but |
45 | * the updates as seen by the CPU don't seem to be strictly monotonic. | |
46 | * Waiting until we read the same value twice avoids glitching. | |
73a59c1c | 47 | */ |
5e802dfa DB |
48 | static inline unsigned long read_CRTR(void) |
49 | { | |
adf2edfd | 50 | unsigned int x1, x2; |
73a59c1c | 51 | |
adf2edfd | 52 | regmap_read(regmap_st, AT91_ST_CRTR, &x1); |
73a59c1c | 53 | do { |
adf2edfd | 54 | regmap_read(regmap_st, AT91_ST_CRTR, &x2); |
5e802dfa DB |
55 | if (x1 == x2) |
56 | break; | |
57 | x1 = x2; | |
58 | } while (1); | |
73a59c1c SP |
59 | return x1; |
60 | } | |
61 | ||
73a59c1c SP |
62 | /* |
63 | * IRQ handler for the timer. | |
64 | */ | |
0cd61b68 | 65 | static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id) |
73a59c1c | 66 | { |
adf2edfd AB |
67 | u32 sr; |
68 | ||
69 | regmap_read(regmap_st, AT91_ST_SR, &sr); | |
70 | sr &= irqmask; | |
73a59c1c | 71 | |
501d7038 UKK |
72 | /* |
73 | * irqs should be disabled here, but as the irq is shared they are only | |
74 | * guaranteed to be off if the timer irq is registered first. | |
75 | */ | |
76 | WARN_ON_ONCE(!irqs_disabled()); | |
77 | ||
5e802dfa DB |
78 | /* simulate "oneshot" timer with alarm */ |
79 | if (sr & AT91_ST_ALMS) { | |
80 | clkevt.event_handler(&clkevt); | |
81 | return IRQ_HANDLED; | |
82 | } | |
73a59c1c | 83 | |
5e802dfa DB |
84 | /* periodic mode should handle delayed ticks */ |
85 | if (sr & AT91_ST_PITS) { | |
86 | u32 crtr = read_CRTR(); | |
73a59c1c | 87 | |
2f5893cf JCPV |
88 | while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) { |
89 | last_crtr += RM9200_TIMER_LATCH; | |
5e802dfa DB |
90 | clkevt.event_handler(&clkevt); |
91 | } | |
73a59c1c SP |
92 | return IRQ_HANDLED; |
93 | } | |
5e802dfa DB |
94 | |
95 | /* this irq is shared ... */ | |
96 | return IRQ_NONE; | |
73a59c1c SP |
97 | } |
98 | ||
99 | static struct irqaction at91rm9200_timer_irq = { | |
100 | .name = "at91_tick", | |
9ceb389d | 101 | .flags = IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL, |
454c46df JE |
102 | .handler = at91rm9200_timer_interrupt, |
103 | .irq = NR_IRQS_LEGACY + AT91_ID_SYS, | |
73a59c1c SP |
104 | }; |
105 | ||
8e19608e | 106 | static cycle_t read_clk32k(struct clocksource *cs) |
2a6f9902 | 107 | { |
5e802dfa DB |
108 | return read_CRTR(); |
109 | } | |
2a6f9902 | 110 | |
5e802dfa DB |
111 | static struct clocksource clk32k = { |
112 | .name = "32k_counter", | |
113 | .rating = 150, | |
114 | .read = read_clk32k, | |
115 | .mask = CLOCKSOURCE_MASK(20), | |
5e802dfa DB |
116 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
117 | }; | |
118 | ||
119 | static void | |
120 | clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev) | |
121 | { | |
adf2edfd AB |
122 | unsigned int val; |
123 | ||
5e802dfa | 124 | /* Disable and flush pending timer interrupts */ |
adf2edfd AB |
125 | regmap_write(regmap_st, AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS); |
126 | regmap_read(regmap_st, AT91_ST_SR, &val); | |
2a6f9902 | 127 | |
5e802dfa DB |
128 | last_crtr = read_CRTR(); |
129 | switch (mode) { | |
130 | case CLOCK_EVT_MODE_PERIODIC: | |
131 | /* PIT for periodic irqs; fixed rate of 1/HZ */ | |
132 | irqmask = AT91_ST_PITS; | |
adf2edfd | 133 | regmap_write(regmap_st, AT91_ST_PIMR, RM9200_TIMER_LATCH); |
5e802dfa DB |
134 | break; |
135 | case CLOCK_EVT_MODE_ONESHOT: | |
136 | /* ALM for oneshot irqs, set by next_event() | |
137 | * before 32 seconds have passed | |
138 | */ | |
139 | irqmask = AT91_ST_ALMS; | |
adf2edfd | 140 | regmap_write(regmap_st, AT91_ST_RTAR, last_crtr); |
5e802dfa DB |
141 | break; |
142 | case CLOCK_EVT_MODE_SHUTDOWN: | |
143 | case CLOCK_EVT_MODE_UNUSED: | |
144 | case CLOCK_EVT_MODE_RESUME: | |
145 | irqmask = 0; | |
146 | break; | |
147 | } | |
adf2edfd | 148 | regmap_write(regmap_st, AT91_ST_IER, irqmask); |
5e802dfa | 149 | } |
2a6f9902 | 150 | |
5e802dfa DB |
151 | static int |
152 | clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) | |
153 | { | |
5e802dfa DB |
154 | u32 alm; |
155 | int status = 0; | |
adf2edfd | 156 | unsigned int val; |
5e802dfa DB |
157 | |
158 | BUG_ON(delta < 2); | |
159 | ||
5e802dfa DB |
160 | /* The alarm IRQ uses absolute time (now+delta), not the relative |
161 | * time (delta) in our calling convention. Like all clockevents | |
162 | * using such "match" hardware, we have a race to defend against. | |
163 | * | |
164 | * Our defense here is to have set up the clockevent device so the | |
165 | * delta is at least two. That way we never end up writing RTAR | |
166 | * with the value then held in CRTR ... which would mean the match | |
167 | * wouldn't trigger until 32 seconds later, after CRTR wraps. | |
168 | */ | |
169 | alm = read_CRTR(); | |
170 | ||
171 | /* Cancel any pending alarm; flush any pending IRQ */ | |
adf2edfd AB |
172 | regmap_write(regmap_st, AT91_ST_RTAR, alm); |
173 | regmap_read(regmap_st, AT91_ST_SR, &val); | |
d100f259 | 174 | |
5e802dfa DB |
175 | /* Schedule alarm by writing RTAR. */ |
176 | alm += delta; | |
adf2edfd | 177 | regmap_write(regmap_st, AT91_ST_RTAR, alm); |
5e802dfa | 178 | |
5e802dfa | 179 | return status; |
2a6f9902 AV |
180 | } |
181 | ||
5e802dfa DB |
182 | static struct clock_event_device clkevt = { |
183 | .name = "at91_tick", | |
184 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
5e802dfa | 185 | .rating = 150, |
5e802dfa DB |
186 | .set_next_event = clkevt32k_next_event, |
187 | .set_mode = clkevt32k_mode, | |
188 | }; | |
189 | ||
73a59c1c | 190 | /* |
5e802dfa | 191 | * ST (system timer) module supports both clockevents and clocksource. |
73a59c1c | 192 | */ |
bbfc97e1 | 193 | static void __init atmel_st_timer_init(struct device_node *node) |
73a59c1c | 194 | { |
adf2edfd AB |
195 | unsigned int val; |
196 | ||
197 | regmap_st = syscon_node_to_regmap(node); | |
198 | if (IS_ERR(regmap_st)) | |
199 | panic(pr_fmt("Unable to get regmap\n")); | |
454c46df | 200 | |
5e802dfa | 201 | /* Disable all timer interrupts, and clear any pending ones */ |
adf2edfd | 202 | regmap_write(regmap_st, AT91_ST_IDR, |
5e802dfa | 203 | AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS); |
adf2edfd AB |
204 | regmap_read(regmap_st, AT91_ST_SR, &val); |
205 | ||
206 | /* Get the interrupts property */ | |
207 | at91rm9200_timer_irq.irq = irq_of_parse_and_map(node, 0); | |
208 | if (!at91rm9200_timer_irq.irq) | |
209 | panic(pr_fmt("Unable to get IRQ from DT\n")); | |
73a59c1c | 210 | |
2a6f9902 | 211 | /* Make IRQs happen for the system timer */ |
454c46df | 212 | setup_irq(at91rm9200_timer_irq.irq, &at91rm9200_timer_irq); |
73a59c1c | 213 | |
5e802dfa DB |
214 | /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used |
215 | * directly for the clocksource and all clockevents, after adjusting | |
216 | * its prescaler from the 1 Hz default. | |
217 | */ | |
adf2edfd | 218 | regmap_write(regmap_st, AT91_ST_RTMR, 1); |
73a59c1c | 219 | |
5e802dfa | 220 | /* Setup timer clockevent, with minimum of two ticks (important!!) */ |
320ab2b0 | 221 | clkevt.cpumask = cpumask_of(0); |
1c283531 UKK |
222 | clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK, |
223 | 2, AT91_ST_ALMV); | |
2a6f9902 | 224 | |
5e802dfa | 225 | /* register clocksource */ |
132b1632 | 226 | clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK); |
73a59c1c | 227 | } |
bbfc97e1 AB |
228 | CLOCKSOURCE_OF_DECLARE(atmel_st_timer, "atmel,at91rm9200-st", |
229 | atmel_st_timer_init); |