[deliverable/linux.git] / drivers / clocksource / timer-imx-gpt.c

/*
 *  linux/arch/arm/plat-mxc/time.c
 *
 *  Copyright (C) 2000-2001 Deep Blue Solutions
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
 *  Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */

#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/sched_clock.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <soc/imx/timer.h>

/*
 * There are 4 versions of the timer hardware on Freescale MXC hardware.
 *  - MX1/MXL
 *  - MX21, MX27.
 *  - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
 *  - MX6DL, MX6SX, MX6Q(rev1.1+)
 */

/* defines common for all i.MX */
#define MXC_TCTL		0x00
#define MXC_TCTL_TEN		(1 << 0) /* Enable module */
#define MXC_TPRER		0x04

/* MX1, MX21, MX27 */
#define MX1_2_TCTL_CLK_PCLK1	(1 << 1)
#define MX1_2_TCTL_IRQEN	(1 << 4)
#define MX1_2_TCTL_FRR		(1 << 8)
#define MX1_2_TCMP		0x08
#define MX1_2_TCN		0x10
#define MX1_2_TSTAT		0x14

/* MX21, MX27 */
#define MX2_TSTAT_CAPT		(1 << 1)
#define MX2_TSTAT_COMP		(1 << 0)

/* MX31, MX35, MX25, MX5, MX6 */
#define V2_TCTL_WAITEN		(1 << 3) /* Wait enable mode */
#define V2_TCTL_CLK_IPG		(1 << 6)
#define V2_TCTL_CLK_PER		(2 << 6)
#define V2_TCTL_CLK_OSC_DIV8	(5 << 6)
#define V2_TCTL_FRR		(1 << 9)
#define V2_TCTL_24MEN		(1 << 10)
#define V2_TPRER_PRE24M		12
#define V2_IR			0x0c
#define V2_TSTAT		0x08
#define V2_TSTAT_OF1		(1 << 0)
#define V2_TCN			0x24
#define V2_TCMP			0x10

#define V2_TIMER_RATE_OSC_DIV8	3000000

struct imx_timer {
	enum imx_gpt_type type;
	void __iomem *base;
	int irq;
	struct clk *clk_per;
	struct clk *clk_ipg;
	const struct imx_gpt_data *gpt;
	struct clock_event_device ced;
	enum clock_event_mode cem;
	struct irqaction act;
};

struct imx_gpt_data {
	int reg_tstat;
	int reg_tcn;
	int reg_tcmp;
	void (*gpt_setup_tctl)(struct imx_timer *imxtm);
	void (*gpt_irq_enable)(struct imx_timer *imxtm);
	void (*gpt_irq_disable)(struct imx_timer *imxtm);
	void (*gpt_irq_acknowledge)(struct imx_timer *imxtm);
	int (*set_next_event)(unsigned long evt,
			      struct clock_event_device *ced);
};

static inline struct imx_timer *to_imx_timer(struct clock_event_device *ced)
{
	return container_of(ced, struct imx_timer, ced);
}

static void imx1_gpt_irq_disable(struct imx_timer *imxtm)
{
	unsigned int tmp;

	tmp = readl_relaxed(imxtm->base + MXC_TCTL);
	writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
}
#define imx21_gpt_irq_disable imx1_gpt_irq_disable

static void imx31_gpt_irq_disable(struct imx_timer *imxtm)
{
	writel_relaxed(0, imxtm->base + V2_IR);
}
#define imx6dl_gpt_irq_disable imx31_gpt_irq_disable

static void imx1_gpt_irq_enable(struct imx_timer *imxtm)
{
	unsigned int tmp;

	tmp = readl_relaxed(imxtm->base + MXC_TCTL);
	writel_relaxed(tmp | MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
}
#define imx21_gpt_irq_enable imx1_gpt_irq_enable

static void imx31_gpt_irq_enable(struct imx_timer *imxtm)
{
	writel_relaxed(1<<0, imxtm->base + V2_IR);
}
#define imx6dl_gpt_irq_enable imx31_gpt_irq_enable

static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm)
{
	writel_relaxed(0, imxtm->base + MX1_2_TSTAT);
}

static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm)
{
	writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP,
				imxtm->base + MX1_2_TSTAT);
}

static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm)
{
	writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT);
}
#define imx6dl_gpt_irq_acknowledge imx31_gpt_irq_acknowledge

static void __iomem *sched_clock_reg;

static u64 notrace mxc_read_sched_clock(void)
{
	return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0;
}

static struct delay_timer imx_delay_timer;

static unsigned long imx_read_current_timer(void)
{
	return readl_relaxed(sched_clock_reg);
}

static int __init mxc_clocksource_init(struct imx_timer *imxtm)
{
	unsigned int c = clk_get_rate(imxtm->clk_per);
	void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn;

	imx_delay_timer.read_current_timer = &imx_read_current_timer;
	imx_delay_timer.freq = c;
	register_current_timer_delay(&imx_delay_timer);

	sched_clock_reg = reg;

	sched_clock_register(mxc_read_sched_clock, 32, c);
	return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
			clocksource_mmio_readl_up);
}

/* clock event */

static int mx1_2_set_next_event(unsigned long evt,
			      struct clock_event_device *ced)
{
	struct imx_timer *imxtm = to_imx_timer(ced);
	unsigned long tcmp;

	tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt;

	writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP);

	return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ?
				-ETIME : 0;
}

static int v2_set_next_event(unsigned long evt,
			      struct clock_event_device *ced)
{
	struct imx_timer *imxtm = to_imx_timer(ced);
	unsigned long tcmp;

	tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt;

	writel_relaxed(tcmp, imxtm->base + V2_TCMP);

	return evt < 0x7fffffff &&
		(int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ?
				-ETIME : 0;
}

#ifdef DEBUG
static const char *clock_event_mode_label[] = {
	[CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
	[CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
	[CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
	[CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED",
	[CLOCK_EVT_MODE_RESUME]   = "CLOCK_EVT_MODE_RESUME",
};
#endif /* DEBUG */

static void mxc_set_mode(enum clock_event_mode mode,
				struct clock_event_device *ced)
{
	struct imx_timer *imxtm = to_imx_timer(ced);
	unsigned long flags;

	/*
	 * The timer interrupt generation is disabled at least
	 * for enough time to call mxc_set_next_event()
	 */
	local_irq_save(flags);

	/* Disable interrupt in GPT module */
	imxtm->gpt->gpt_irq_disable(imxtm);

	if (mode != imxtm->cem) {
		u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
		/* Set event time into far-far future */
		writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);

		/* Clear pending interrupt */
		imxtm->gpt->gpt_irq_acknowledge(imxtm);
	}

#ifdef DEBUG
	printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
		clock_event_mode_label[imxtm->cem],
		clock_event_mode_label[mode]);
#endif /* DEBUG */

	/* Remember timer mode */
	imxtm->cem = mode;
	local_irq_restore(flags);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
				"supported for i.MX\n");
		break;
	case CLOCK_EVT_MODE_ONESHOT:
	/*
	 * Do not put overhead of interrupt enable/disable into
	 * mxc_set_next_event(), the core has about 4 minutes
	 * to call mxc_set_next_event() or shutdown clock after
	 * mode switching
	 */
		local_irq_save(flags);
		imxtm->gpt->gpt_irq_enable(imxtm);
		local_irq_restore(flags);
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_RESUME:
		/* Left event sources disabled, no more interrupts appear */
		break;
	}
}

/*
 * IRQ handler for the timer
 */
static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *ced = dev_id;
	struct imx_timer *imxtm = to_imx_timer(ced);
	uint32_t tstat;

	tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat);

	imxtm->gpt->gpt_irq_acknowledge(imxtm);

	ced->event_handler(ced);

	return IRQ_HANDLED;
}

static int __init mxc_clockevent_init(struct imx_timer *imxtm)
{
	struct clock_event_device *ced = &imxtm->ced;
	struct irqaction *act = &imxtm->act;

	imxtm->cem = CLOCK_EVT_MODE_UNUSED;

	ced->name = "mxc_timer1";
	ced->features = CLOCK_EVT_FEAT_ONESHOT;
	ced->set_mode = mxc_set_mode;
	ced->set_next_event = imxtm->gpt->set_next_event;
	ced->rating = 200;
	ced->cpumask = cpumask_of(0);
	clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per),
					0xff, 0xfffffffe);

	act->name = "i.MX Timer Tick";
	act->flags = IRQF_TIMER | IRQF_IRQPOLL;
	act->handler = mxc_timer_interrupt;
	act->dev_id = ced;

	return setup_irq(imxtm->irq, act);
}

static void imx1_gpt_setup_tctl(struct imx_timer *imxtm)
{
	u32 tctl_val;

	tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}
#define imx21_gpt_setup_tctl imx1_gpt_setup_tctl

static void imx31_gpt_setup_tctl(struct imx_timer *imxtm)
{
	u32 tctl_val;

	tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8)
		tctl_val |= V2_TCTL_CLK_OSC_DIV8;
	else
		tctl_val |= V2_TCTL_CLK_PER;

	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}

static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm)
{
	u32 tctl_val;

	tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) {
		tctl_val |= V2_TCTL_CLK_OSC_DIV8;
		/* 24 / 8 = 3 MHz */
		writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);
		tctl_val |= V2_TCTL_24MEN;
	} else {
		tctl_val |= V2_TCTL_CLK_PER;
	}

	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
}

static const struct imx_gpt_data imx1_gpt_data = {
	.reg_tstat = MX1_2_TSTAT,
	.reg_tcn = MX1_2_TCN,
	.reg_tcmp = MX1_2_TCMP,
	.gpt_irq_enable = imx1_gpt_irq_enable,
	.gpt_irq_disable = imx1_gpt_irq_disable,
	.gpt_irq_acknowledge = imx1_gpt_irq_acknowledge,
	.gpt_setup_tctl = imx1_gpt_setup_tctl,
	.set_next_event = mx1_2_set_next_event,
};

static const struct imx_gpt_data imx21_gpt_data = {
	.reg_tstat = MX1_2_TSTAT,
	.reg_tcn = MX1_2_TCN,
	.reg_tcmp = MX1_2_TCMP,
	.gpt_irq_enable = imx21_gpt_irq_enable,
	.gpt_irq_disable = imx21_gpt_irq_disable,
	.gpt_irq_acknowledge = imx21_gpt_irq_acknowledge,
	.gpt_setup_tctl = imx21_gpt_setup_tctl,
	.set_next_event = mx1_2_set_next_event,
};

static const struct imx_gpt_data imx31_gpt_data = {
	.reg_tstat = V2_TSTAT,
	.reg_tcn = V2_TCN,
	.reg_tcmp = V2_TCMP,
	.gpt_irq_enable = imx31_gpt_irq_enable,
	.gpt_irq_disable = imx31_gpt_irq_disable,
	.gpt_irq_acknowledge = imx31_gpt_irq_acknowledge,
	.gpt_setup_tctl = imx31_gpt_setup_tctl,
	.set_next_event = v2_set_next_event,
};

static const struct imx_gpt_data imx6dl_gpt_data = {
	.reg_tstat = V2_TSTAT,
	.reg_tcn = V2_TCN,
	.reg_tcmp = V2_TCMP,
	.gpt_irq_enable = imx6dl_gpt_irq_enable,
	.gpt_irq_disable = imx6dl_gpt_irq_disable,
	.gpt_irq_acknowledge = imx6dl_gpt_irq_acknowledge,
	.gpt_setup_tctl = imx6dl_gpt_setup_tctl,
	.set_next_event = v2_set_next_event,
};

static void __init _mxc_timer_init(struct imx_timer *imxtm)
{
	switch (imxtm->type) {
	case GPT_TYPE_IMX1:
		imxtm->gpt = &imx1_gpt_data;
		break;
	case GPT_TYPE_IMX21:
		imxtm->gpt = &imx21_gpt_data;
		break;
	case GPT_TYPE_IMX31:
		imxtm->gpt = &imx31_gpt_data;
		break;
	case GPT_TYPE_IMX6DL:
		imxtm->gpt = &imx6dl_gpt_data;
		break;
	default:
		BUG();
	}

	if (IS_ERR(imxtm->clk_per)) {
		pr_err("i.MX timer: unable to get clk\n");
		return;
	}

	if (!IS_ERR(imxtm->clk_ipg))
		clk_prepare_enable(imxtm->clk_ipg);

	clk_prepare_enable(imxtm->clk_per);

	/*
	 * Initialise to a known state (all timers off, and timing reset)
	 */

	writel_relaxed(0, imxtm->base + MXC_TCTL);
	writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */

	imxtm->gpt->gpt_setup_tctl(imxtm);

	/* init and register the timer to the framework */
	mxc_clocksource_init(imxtm);
	mxc_clockevent_init(imxtm);
}

void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type)
{
	struct imx_timer *imxtm;

	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
	BUG_ON(!imxtm);

	imxtm->clk_per = clk_get_sys("imx-gpt.0", "per");
	imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg");

	imxtm->base = ioremap(pbase, SZ_4K);
	BUG_ON(!imxtm->base);

	imxtm->type = type;

	_mxc_timer_init(imxtm);
}

static void __init mxc_timer_init_dt(struct device_node *np,  enum imx_gpt_type type)
{
	struct imx_timer *imxtm;
	static int initialized;

	/* Support one instance only */
	if (initialized)
		return;

	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
	BUG_ON(!imxtm);

	imxtm->base = of_iomap(np, 0);
	WARN_ON(!imxtm->base);
	imxtm->irq = irq_of_parse_and_map(np, 0);

	imxtm->clk_ipg = of_clk_get_by_name(np, "ipg");

	/* Try osc_per first, and fall back to per otherwise */
	imxtm->clk_per = of_clk_get_by_name(np, "osc_per");
	if (IS_ERR(imxtm->clk_per))
		imxtm->clk_per = of_clk_get_by_name(np, "per");

	imxtm->type = type;

	_mxc_timer_init(imxtm);

	initialized = 1;
}

static void __init imx1_timer_init_dt(struct device_node *np)
{
	mxc_timer_init_dt(np, GPT_TYPE_IMX1);
}

static void __init imx21_timer_init_dt(struct device_node *np)
{
	mxc_timer_init_dt(np, GPT_TYPE_IMX21);
}

static void __init imx31_timer_init_dt(struct device_node *np)
{
	enum imx_gpt_type type = GPT_TYPE_IMX31;

	/*
	 * We were using the same compatible string for i.MX6Q/D and i.MX6DL/S
	 * GPT device, while they actually have different programming model.
	 * This is a workaround to keep the existing i.MX6DL/S DTBs continue
	 * working with the new kernel.
	 */
	if (of_machine_is_compatible("fsl,imx6dl"))
		type = GPT_TYPE_IMX6DL;

	mxc_timer_init_dt(np, type);
}

static void __init imx6dl_timer_init_dt(struct device_node *np)
{
	mxc_timer_init_dt(np, GPT_TYPE_IMX6DL);
}

CLOCKSOURCE_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);
Commit	Line	Data
d0f349fb JB	1	/*
	2	* linux/arch/arm/plat-mxc/time.c
	3	*
	4	* Copyright (C) 2000-2001 Deep Blue Solutions
	5	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	6	* Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
	7	* Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version 2
	12	* of the License, or (at your option) any later version.
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	21	* MA 02110-1301, USA.
	22	*/
	23
	24	#include <linux/interrupt.h>
	25	#include <linux/irq.h>
	26	#include <linux/clockchips.h>
	27	#include <linux/clk.h>
1119c84a	28	#include <linux/delay.h>
821dc4df	29	#include <linux/err.h>
38ff87f7	30	#include <linux/sched_clock.h>
6dd74782	31	#include <linux/slab.h>
876292d6 GC	32	#include <linux/of.h>
	33	#include <linux/of_address.h>
	34	#include <linux/of_irq.h>
0931aff7	35	#include <soc/imx/timer.h>
d0f349fb	36
0f3332c4	37	/*
65d0a16d SW	38	* There are 4 versions of the timer hardware on Freescale MXC hardware.
	39	* - MX1/MXL
	40	* - MX21, MX27.
	41	* - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0)
	42	* - MX6DL, MX6SX, MX6Q(rev1.1+)
0f3332c4 SH	43	*/
0f3332c4 SH	44
ec996ba9 SH	45	/* defines common for all i.MX */
ec996ba9 SH	46	#define MXC_TCTL 0x00
0f3332c4	47	#define MXC_TCTL_TEN (1 << 0) /* Enable module */
ec996ba9 SH	48	#define MXC_TPRER 0x04
	49
	50	/* MX1, MX21, MX27 */
	51	#define MX1_2_TCTL_CLK_PCLK1 (1 << 1)
	52	#define MX1_2_TCTL_IRQEN (1 << 4)
	53	#define MX1_2_TCTL_FRR (1 << 8)
	54	#define MX1_2_TCMP 0x08
	55	#define MX1_2_TCN 0x10
	56	#define MX1_2_TSTAT 0x14
	57
	58	/* MX21, MX27 */
	59	#define MX2_TSTAT_CAPT (1 << 1)
	60	#define MX2_TSTAT_COMP (1 << 0)
	61
bad3db10	62	/* MX31, MX35, MX25, MX5, MX6 */
38a66f51 AK	63	#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
38a66f51 AK	64	#define V2_TCTL_CLK_IPG (1 << 6)
1f152b48	65	#define V2_TCTL_CLK_PER (2 << 6)
bad3db10	66	#define V2_TCTL_CLK_OSC_DIV8 (5 << 6)
38a66f51	67	#define V2_TCTL_FRR (1 << 9)
bad3db10 AH	68	#define V2_TCTL_24MEN (1 << 10)
bad3db10 AH	69	#define V2_TPRER_PRE24M 12
38a66f51 AK	70	#define V2_IR 0x0c
	71	#define V2_TSTAT 0x08
	72	#define V2_TSTAT_OF1 (1 << 0)
	73	#define V2_TCN 0x24
	74	#define V2_TCMP 0x10
d0f349fb	75
bad3db10 AH	76	#define V2_TIMER_RATE_OSC_DIV8 3000000
bad3db10 AH	77
6dd74782	78	struct imx_timer {
0931aff7	79	enum imx_gpt_type type;
6dd74782 SG	80	void __iomem *base;
	81	int irq;
	82	struct clk *clk_per;
	83	struct clk *clk_ipg;
9c8694bd	84	const struct imx_gpt_data *gpt;
e510d201 SG	85	struct clock_event_device ced;
	86	enum clock_event_mode cem;
	87	struct irqaction act;
9c8694bd SG	88	};
	89
	90	struct imx_gpt_data {
24f74ad1 SG	91	int reg_tstat;
	92	int reg_tcn;
	93	int reg_tcmp;
9c8694bd	94	void (gpt_setup_tctl)(struct imx_timer imxtm);
db2ae4b4 SG	95	void (gpt_irq_enable)(struct imx_timer imxtm);
	96	void (gpt_irq_disable)(struct imx_timer imxtm);
	97	void (gpt_irq_acknowledge)(struct imx_timer imxtm);
5ab0475b SG	98	int (*set_next_event)(unsigned long evt,
5ab0475b SG	99	struct clock_event_device *ced);
6dd74782 SG	100	};
6dd74782 SG	101
e510d201 SG	102	static inline struct imx_timer to_imx_timer(struct clock_event_device ced)
	103	{
	104	return container_of(ced, struct imx_timer, ced);
	105	}
	106
db2ae4b4	107	static void imx1_gpt_irq_disable(struct imx_timer *imxtm)
d0f349fb	108	{
ec996ba9 SH	109	unsigned int tmp;
ec996ba9 SH	110
db2ae4b4 SG	111	tmp = readl_relaxed(imxtm->base + MXC_TCTL);
db2ae4b4 SG	112	writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
ec996ba9	113	}
db2ae4b4	114	#define imx21_gpt_irq_disable imx1_gpt_irq_disable
ec996ba9	115
db2ae4b4	116	static void imx31_gpt_irq_disable(struct imx_timer *imxtm)
ec996ba9	117	{
db2ae4b4 SG	118	writel_relaxed(0, imxtm->base + V2_IR);
	119	}
	120	#define imx6dl_gpt_irq_disable imx31_gpt_irq_disable
	121
	122	static void imx1_gpt_irq_enable(struct imx_timer *imxtm)
	123	{
	124	unsigned int tmp;
	125
	126	tmp = readl_relaxed(imxtm->base + MXC_TCTL);
	127	writel_relaxed(tmp \| MX1_2_TCTL_IRQEN, imxtm->base + MXC_TCTL);
	128	}
	129	#define imx21_gpt_irq_enable imx1_gpt_irq_enable
	130
	131	static void imx31_gpt_irq_enable(struct imx_timer *imxtm)
	132	{
	133	writel_relaxed(1<<0, imxtm->base + V2_IR);
	134	}
	135	#define imx6dl_gpt_irq_enable imx31_gpt_irq_enable
	136
	137	static void imx1_gpt_irq_acknowledge(struct imx_timer *imxtm)
	138	{
	139	writel_relaxed(0, imxtm->base + MX1_2_TSTAT);
ec996ba9 SH	140	}
ec996ba9 SH	141
db2ae4b4	142	static void imx21_gpt_irq_acknowledge(struct imx_timer *imxtm)
ec996ba9	143	{
db2ae4b4	144	writel_relaxed(MX2_TSTAT_CAPT \| MX2_TSTAT_COMP,
89955520	145	imxtm->base + MX1_2_TSTAT);
ec996ba9 SH	146	}
ec996ba9 SH	147
db2ae4b4 SG	148	static void imx31_gpt_irq_acknowledge(struct imx_timer *imxtm)
	149	{
	150	writel_relaxed(V2_TSTAT_OF1, imxtm->base + V2_TSTAT);
	151	}
	152	#define imx6dl_gpt_irq_acknowledge imx31_gpt_irq_acknowledge
	153
234b6ced	154	static void __iomem *sched_clock_reg;
d0f349fb	155
b93767e3	156	static u64 notrace mxc_read_sched_clock(void)
c124befc	157	{
c7770bba	158	return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0;
c124befc JW	159	}
c124befc JW	160
1119c84a SAS	161	static struct delay_timer imx_delay_timer;
	162
	163	static unsigned long imx_read_current_timer(void)
	164	{
c7770bba	165	return readl_relaxed(sched_clock_reg);
1119c84a SAS	166	}
1119c84a SAS	167
6dd74782	168	static int __init mxc_clocksource_init(struct imx_timer *imxtm)
d0f349fb	169	{
6dd74782	170	unsigned int c = clk_get_rate(imxtm->clk_per);
24f74ad1	171	void __iomem *reg = imxtm->base + imxtm->gpt->reg_tcn;
d0f349fb	172
1119c84a SAS	173	imx_delay_timer.read_current_timer = &imx_read_current_timer;
	174	imx_delay_timer.freq = c;
	175	register_current_timer_delay(&imx_delay_timer);
	176
234b6ced	177	sched_clock_reg = reg;
ec996ba9	178
b93767e3	179	sched_clock_register(mxc_read_sched_clock, 32, c);
234b6ced RK	180	return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
234b6ced RK	181	clocksource_mmio_readl_up);
d0f349fb JB	182	}
	183
	184	/* clock event */
	185
ec996ba9	186	static int mx1_2_set_next_event(unsigned long evt,
89955520	187	struct clock_event_device *ced)
d0f349fb	188	{
89955520	189	struct imx_timer *imxtm = to_imx_timer(ced);
d0f349fb JB	190	unsigned long tcmp;
d0f349fb JB	191
89955520	192	tcmp = readl_relaxed(imxtm->base + MX1_2_TCN) + evt;
d0f349fb	193
89955520	194	writel_relaxed(tcmp, imxtm->base + MX1_2_TCMP);
ec996ba9	195
89955520	196	return (int)(tcmp - readl_relaxed(imxtm->base + MX1_2_TCN)) < 0 ?
ec996ba9 SH	197	-ETIME : 0;
	198	}
	199
38a66f51	200	static int v2_set_next_event(unsigned long evt,
89955520	201	struct clock_event_device *ced)
ec996ba9	202	{
89955520	203	struct imx_timer *imxtm = to_imx_timer(ced);
ec996ba9 SH	204	unsigned long tcmp;
ec996ba9 SH	205
89955520	206	tcmp = readl_relaxed(imxtm->base + V2_TCN) + evt;
ec996ba9	207
89955520	208	writel_relaxed(tcmp, imxtm->base + V2_TCMP);
ec996ba9	209
eea8e326	210	return evt < 0x7fffffff &&
89955520	211	(int)(tcmp - readl_relaxed(imxtm->base + V2_TCN)) < 0 ?
d0f349fb JB	212	-ETIME : 0;
	213	}
	214
	215	#ifdef DEBUG
	216	static const char *clock_event_mode_label[] = {
	217	[CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
	218	[CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
	219	[CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
de9c5159 UKK	220	[CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED",
de9c5159 UKK	221	[CLOCK_EVT_MODE_RESUME] = "CLOCK_EVT_MODE_RESUME",
d0f349fb JB	222	};
	223	#endif /* DEBUG */
	224
	225	static void mxc_set_mode(enum clock_event_mode mode,
e510d201	226	struct clock_event_device *ced)
d0f349fb	227	{
e510d201	228	struct imx_timer *imxtm = to_imx_timer(ced);
d0f349fb JB	229	unsigned long flags;
	230
	231	/*
	232	* The timer interrupt generation is disabled at least
	233	* for enough time to call mxc_set_next_event()
	234	*/
	235	local_irq_save(flags);
	236
	237	/* Disable interrupt in GPT module */
db2ae4b4	238	imxtm->gpt->gpt_irq_disable(imxtm);
d0f349fb	239
e510d201	240	if (mode != imxtm->cem) {
24f74ad1	241	u32 tcn = readl_relaxed(imxtm->base + imxtm->gpt->reg_tcn);
d0f349fb	242	/* Set event time into far-far future */
24f74ad1	243	writel_relaxed(tcn - 3, imxtm->base + imxtm->gpt->reg_tcmp);
ec996ba9	244
d0f349fb	245	/* Clear pending interrupt */
db2ae4b4	246	imxtm->gpt->gpt_irq_acknowledge(imxtm);
d0f349fb JB	247	}
	248
	249	#ifdef DEBUG
	250	printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
e510d201	251	clock_event_mode_label[imxtm->cem],
d0f349fb JB	252	clock_event_mode_label[mode]);
	253	#endif /* DEBUG */
	254
	255	/* Remember timer mode */
e510d201	256	imxtm->cem = mode;
d0f349fb JB	257	local_irq_restore(flags);
	258
	259	switch (mode) {
	260	case CLOCK_EVT_MODE_PERIODIC:
	261	printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
	262	"supported for i.MX\n");
	263	break;
	264	case CLOCK_EVT_MODE_ONESHOT:
	265	/*
	266	* Do not put overhead of interrupt enable/disable into
	267	* mxc_set_next_event(), the core has about 4 minutes
	268	* to call mxc_set_next_event() or shutdown clock after
	269	* mode switching
	270	*/
	271	local_irq_save(flags);
db2ae4b4	272	imxtm->gpt->gpt_irq_enable(imxtm);
d0f349fb JB	273	local_irq_restore(flags);
	274	break;
	275	case CLOCK_EVT_MODE_SHUTDOWN:
	276	case CLOCK_EVT_MODE_UNUSED:
	277	case CLOCK_EVT_MODE_RESUME:
	278	/* Left event sources disabled, no more interrupts appear */
	279	break;
	280	}
	281	}
	282
	283	/*
	284	* IRQ handler for the timer
	285	*/
	286	static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
	287	{
e510d201	288	struct clock_event_device *ced = dev_id;
24f74ad1	289	struct imx_timer *imxtm = to_imx_timer(ced);
d0f349fb JB	290	uint32_t tstat;
d0f349fb JB	291
24f74ad1	292	tstat = readl_relaxed(imxtm->base + imxtm->gpt->reg_tstat);
d0f349fb	293
db2ae4b4	294	imxtm->gpt->gpt_irq_acknowledge(imxtm);
d0f349fb	295
e510d201	296	ced->event_handler(ced);
d0f349fb JB	297
	298	return IRQ_HANDLED;
	299	}
	300
6dd74782	301	static int __init mxc_clockevent_init(struct imx_timer *imxtm)
d0f349fb	302	{
e510d201 SG	303	struct clock_event_device *ced = &imxtm->ced;
	304	struct irqaction *act = &imxtm->act;
	305
	306	imxtm->cem = CLOCK_EVT_MODE_UNUSED;
	307
	308	ced->name = "mxc_timer1";
	309	ced->features = CLOCK_EVT_FEAT_ONESHOT;
	310	ced->set_mode = mxc_set_mode;
	311	ced->set_next_event = imxtm->gpt->set_next_event;
	312	ced->rating = 200;
	313	ced->cpumask = cpumask_of(0);
	314	clockevents_config_and_register(ced, clk_get_rate(imxtm->clk_per),
838a2ae8	315	0xff, 0xfffffffe);
d0f349fb	316
e510d201 SG	317	act->name = "i.MX Timer Tick";
	318	act->flags = IRQF_TIMER \| IRQF_IRQPOLL;
	319	act->handler = mxc_timer_interrupt;
	320	act->dev_id = ced;
	321
	322	return setup_irq(imxtm->irq, act);
d0f349fb JB	323	}
d0f349fb JB	324
9c8694bd SG	325	static void imx1_gpt_setup_tctl(struct imx_timer *imxtm)
	326	{
	327	u32 tctl_val;
	328
	329	tctl_val = MX1_2_TCTL_FRR \| MX1_2_TCTL_CLK_PCLK1 \| MXC_TCTL_TEN;
	330	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
	331	}
	332	#define imx21_gpt_setup_tctl imx1_gpt_setup_tctl
	333
	334	static void imx31_gpt_setup_tctl(struct imx_timer *imxtm)
	335	{
	336	u32 tctl_val;
	337
	338	tctl_val = V2_TCTL_FRR \| V2_TCTL_WAITEN \| MXC_TCTL_TEN;
	339	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8)
	340	tctl_val \|= V2_TCTL_CLK_OSC_DIV8;
	341	else
	342	tctl_val \|= V2_TCTL_CLK_PER;
	343
	344	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
	345	}
	346
	347	static void imx6dl_gpt_setup_tctl(struct imx_timer *imxtm)
d0f349fb	348	{
9c8694bd SG	349	u32 tctl_val;
	350
	351	tctl_val = V2_TCTL_FRR \| V2_TCTL_WAITEN \| MXC_TCTL_TEN;
	352	if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) {
	353	tctl_val \|= V2_TCTL_CLK_OSC_DIV8;
	354	/* 24 / 8 = 3 MHz */
	355	writel_relaxed(7 << V2_TPRER_PRE24M, imxtm->base + MXC_TPRER);
	356	tctl_val \|= V2_TCTL_24MEN;
	357	} else {
	358	tctl_val \|= V2_TCTL_CLK_PER;
	359	}
	360
	361	writel_relaxed(tctl_val, imxtm->base + MXC_TCTL);
	362	}
821dc4df	363
9c8694bd	364	static const struct imx_gpt_data imx1_gpt_data = {
24f74ad1 SG	365	.reg_tstat = MX1_2_TSTAT,
	366	.reg_tcn = MX1_2_TCN,
	367	.reg_tcmp = MX1_2_TCMP,
db2ae4b4 SG	368	.gpt_irq_enable = imx1_gpt_irq_enable,
	369	.gpt_irq_disable = imx1_gpt_irq_disable,
	370	.gpt_irq_acknowledge = imx1_gpt_irq_acknowledge,
9c8694bd	371	.gpt_setup_tctl = imx1_gpt_setup_tctl,
5ab0475b	372	.set_next_event = mx1_2_set_next_event,
9c8694bd SG	373	};
	374
	375	static const struct imx_gpt_data imx21_gpt_data = {
24f74ad1 SG	376	.reg_tstat = MX1_2_TSTAT,
	377	.reg_tcn = MX1_2_TCN,
	378	.reg_tcmp = MX1_2_TCMP,
db2ae4b4 SG	379	.gpt_irq_enable = imx21_gpt_irq_enable,
	380	.gpt_irq_disable = imx21_gpt_irq_disable,
	381	.gpt_irq_acknowledge = imx21_gpt_irq_acknowledge,
9c8694bd	382	.gpt_setup_tctl = imx21_gpt_setup_tctl,
5ab0475b	383	.set_next_event = mx1_2_set_next_event,
9c8694bd SG	384	};
	385
	386	static const struct imx_gpt_data imx31_gpt_data = {
24f74ad1 SG	387	.reg_tstat = V2_TSTAT,
	388	.reg_tcn = V2_TCN,
	389	.reg_tcmp = V2_TCMP,
db2ae4b4 SG	390	.gpt_irq_enable = imx31_gpt_irq_enable,
	391	.gpt_irq_disable = imx31_gpt_irq_disable,
	392	.gpt_irq_acknowledge = imx31_gpt_irq_acknowledge,
9c8694bd	393	.gpt_setup_tctl = imx31_gpt_setup_tctl,
5ab0475b	394	.set_next_event = v2_set_next_event,
9c8694bd SG	395	};
	396
	397	static const struct imx_gpt_data imx6dl_gpt_data = {
24f74ad1 SG	398	.reg_tstat = V2_TSTAT,
	399	.reg_tcn = V2_TCN,
	400	.reg_tcmp = V2_TCMP,
db2ae4b4 SG	401	.gpt_irq_enable = imx6dl_gpt_irq_enable,
	402	.gpt_irq_disable = imx6dl_gpt_irq_disable,
	403	.gpt_irq_acknowledge = imx6dl_gpt_irq_acknowledge,
9c8694bd	404	.gpt_setup_tctl = imx6dl_gpt_setup_tctl,
5ab0475b	405	.set_next_event = v2_set_next_event,
9c8694bd SG	406	};
	407
	408	static void __init _mxc_timer_init(struct imx_timer *imxtm)
	409	{
9c8694bd SG	410	switch (imxtm->type) {
	411	case GPT_TYPE_IMX1:
	412	imxtm->gpt = &imx1_gpt_data;
	413	break;
	414	case GPT_TYPE_IMX21:
	415	imxtm->gpt = &imx21_gpt_data;
	416	break;
	417	case GPT_TYPE_IMX31:
	418	imxtm->gpt = &imx31_gpt_data;
	419	break;
	420	case GPT_TYPE_IMX6DL:
	421	imxtm->gpt = &imx6dl_gpt_data;
	422	break;
	423	default:
	424	BUG();
	425	}
	426
6dd74782	427	if (IS_ERR(imxtm->clk_per)) {
2cfb4518 SH	428	pr_err("i.MX timer: unable to get clk\n");
2cfb4518 SH	429	return;
821dc4df	430	}
ec996ba9	431
6dd74782 SG	432	if (!IS_ERR(imxtm->clk_ipg))
6dd74782 SG	433	clk_prepare_enable(imxtm->clk_ipg);
2cfb4518	434
6dd74782	435	clk_prepare_enable(imxtm->clk_per);
d0f349fb JB	436
	437	/*
	438	* Initialise to a known state (all timers off, and timing reset)
	439	*/
d0f349fb	440
6dd74782 SG	441	writel_relaxed(0, imxtm->base + MXC_TCTL);
6dd74782 SG	442	writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */
ec996ba9	443
9c8694bd	444	imxtm->gpt->gpt_setup_tctl(imxtm);
d0f349fb JB	445
d0f349fb JB	446	/* init and register the timer to the framework */
6dd74782 SG	447	mxc_clocksource_init(imxtm);
6dd74782 SG	448	mxc_clockevent_init(imxtm);
d0f349fb	449	}
876292d6	450
0931aff7	451	void __init mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type)
f4696752	452	{
6dd74782 SG	453	struct imx_timer *imxtm;
	454
	455	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
	456	BUG_ON(!imxtm);
f4696752	457
6dd74782 SG	458	imxtm->clk_per = clk_get_sys("imx-gpt.0", "per");
6dd74782 SG	459	imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg");
d7f98915	460
6dd74782 SG	461	imxtm->base = ioremap(pbase, SZ_4K);
	462	BUG_ON(!imxtm->base);
	463
0931aff7 SG	464	imxtm->type = type;
0931aff7 SG	465
6dd74782	466	_mxc_timer_init(imxtm);
f4696752 AS	467	}
f4696752 AS	468
bef11c88	469	static void __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type type)
876292d6	470	{
6dd74782 SG	471	struct imx_timer *imxtm;
6dd74782 SG	472	static int initialized;
876292d6	473
6dd74782 SG	474	/* Support one instance only */
6dd74782 SG	475	if (initialized)
fd4959d8 AS	476	return;
fd4959d8 AS	477
6dd74782 SG	478	imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL);
6dd74782 SG	479	BUG_ON(!imxtm);
876292d6	480
6dd74782 SG	481	imxtm->base = of_iomap(np, 0);
	482	WARN_ON(!imxtm->base);
	483	imxtm->irq = irq_of_parse_and_map(np, 0);
	484
	485	imxtm->clk_ipg = of_clk_get_by_name(np, "ipg");
f4696752	486
bad3db10	487	/* Try osc_per first, and fall back to per otherwise */
6dd74782 SG	488	imxtm->clk_per = of_clk_get_by_name(np, "osc_per");
	489	if (IS_ERR(imxtm->clk_per))
	490	imxtm->clk_per = of_clk_get_by_name(np, "per");
	491
bef11c88 SG	492	imxtm->type = type;
bef11c88 SG	493
6dd74782	494	_mxc_timer_init(imxtm);
bad3db10	495
6dd74782	496	initialized = 1;
876292d6	497	}
bef11c88 SG	498
	499	static void __init imx1_timer_init_dt(struct device_node *np)
	500	{
	501	mxc_timer_init_dt(np, GPT_TYPE_IMX1);
	502	}
	503
	504	static void __init imx21_timer_init_dt(struct device_node *np)
	505	{
	506	mxc_timer_init_dt(np, GPT_TYPE_IMX21);
	507	}
	508
	509	static void __init imx31_timer_init_dt(struct device_node *np)
	510	{
	511	enum imx_gpt_type type = GPT_TYPE_IMX31;
	512
	513	/*
	514	* We were using the same compatible string for i.MX6Q/D and i.MX6DL/S
	515	* GPT device, while they actually have different programming model.
	516	* This is a workaround to keep the existing i.MX6DL/S DTBs continue
	517	* working with the new kernel.
	518	*/
	519	if (of_machine_is_compatible("fsl,imx6dl"))
	520	type = GPT_TYPE_IMX6DL;
	521
	522	mxc_timer_init_dt(np, type);
	523	}
	524
	525	static void __init imx6dl_timer_init_dt(struct device_node *np)
	526	{
	527	mxc_timer_init_dt(np, GPT_TYPE_IMX6DL);
	528	}
	529
	530	CLOCKSOURCE_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
	531	CLOCKSOURCE_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
	532	CLOCKSOURCE_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
	533	CLOCKSOURCE_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
	534	CLOCKSOURCE_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
	535	CLOCKSOURCE_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
	536	CLOCKSOURCE_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
	537	CLOCKSOURCE_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
	538	CLOCKSOURCE_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
	539	CLOCKSOURCE_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
	540	CLOCKSOURCE_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);