[deliverable/linux.git] / drivers / clocksource / timer-marco.c

/*
 * System timer for CSR SiRFprimaII
 *
 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
 *
 * Licensed under GPLv2 or later.
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/cpu.h>
#include <linux/bitops.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/sched_clock.h>

#define MARCO_CLOCK_FREQ 1000000

#define SIRFSOC_TIMER_32COUNTER_0_CTRL			0x0000
#define SIRFSOC_TIMER_32COUNTER_1_CTRL			0x0004
#define SIRFSOC_TIMER_MATCH_0				0x0018
#define SIRFSOC_TIMER_MATCH_1				0x001c
#define SIRFSOC_TIMER_COUNTER_0				0x0048
#define SIRFSOC_TIMER_COUNTER_1				0x004c
#define SIRFSOC_TIMER_INTR_STATUS			0x0060
#define SIRFSOC_TIMER_WATCHDOG_EN			0x0064
#define SIRFSOC_TIMER_64COUNTER_CTRL			0x0068
#define SIRFSOC_TIMER_64COUNTER_LO			0x006c
#define SIRFSOC_TIMER_64COUNTER_HI			0x0070
#define SIRFSOC_TIMER_64COUNTER_LOAD_LO			0x0074
#define SIRFSOC_TIMER_64COUNTER_LOAD_HI			0x0078
#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO		0x007c
#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI		0x0080

#define SIRFSOC_TIMER_REG_CNT 6

static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
	SIRFSOC_TIMER_WATCHDOG_EN,
	SIRFSOC_TIMER_32COUNTER_0_CTRL,
	SIRFSOC_TIMER_32COUNTER_1_CTRL,
	SIRFSOC_TIMER_64COUNTER_CTRL,
	SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
	SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
};

static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];

static void __iomem *sirfsoc_timer_base;

/* disable count and interrupt */
static inline void sirfsoc_timer_count_disable(int idx)
{
	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
}

/* enable count and interrupt */
static inline void sirfsoc_timer_count_enable(int idx)
{
	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3,
		sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
}

/* timer interrupt handler */
static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *ce = dev_id;
	int cpu = smp_processor_id();

	/* clear timer interrupt */
	writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);

	if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
		sirfsoc_timer_count_disable(cpu);

	ce->event_handler(ce);

	return IRQ_HANDLED;
}

/* read 64-bit timer counter */
static cycle_t sirfsoc_timer_read(struct clocksource *cs)
{
	u64 cycles;

	writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
			BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);

	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
	cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);

	return cycles;
}

static int sirfsoc_timer_set_next_event(unsigned long delta,
	struct clock_event_device *ce)
{
	int cpu = smp_processor_id();

	/* disable timer first, then modify the related registers */
	sirfsoc_timer_count_disable(cpu);

	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
		4 * cpu);
	writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
		4 * cpu);

	/* enable the tick */
	sirfsoc_timer_count_enable(cpu);

	return 0;
}

static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
	struct clock_event_device *ce)
{
	switch (mode) {
	case CLOCK_EVT_MODE_ONESHOT:
		/* enable in set_next_event */
		break;
	default:
		break;
	}

	sirfsoc_timer_count_disable(smp_processor_id());
}

static void sirfsoc_clocksource_suspend(struct clocksource *cs)
{
	int i;

	for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
		sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
}

static void sirfsoc_clocksource_resume(struct clocksource *cs)
{
	int i;

	for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
		writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);

	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
		sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
		sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);

	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
}

static struct clock_event_device __percpu *sirfsoc_clockevent;

static struct clocksource sirfsoc_clocksource = {
	.name = "sirfsoc_clocksource",
	.rating = 200,
	.mask = CLOCKSOURCE_MASK(64),
	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	.read = sirfsoc_timer_read,
	.suspend = sirfsoc_clocksource_suspend,
	.resume = sirfsoc_clocksource_resume,
};

static struct irqaction sirfsoc_timer_irq = {
	.name = "sirfsoc_timer0",
	.flags = IRQF_TIMER | IRQF_NOBALANCING,
	.handler = sirfsoc_timer_interrupt,
};

static struct irqaction sirfsoc_timer1_irq = {
	.name = "sirfsoc_timer1",
	.flags = IRQF_TIMER | IRQF_NOBALANCING,
	.handler = sirfsoc_timer_interrupt,
};

static int sirfsoc_local_timer_setup(struct clock_event_device *ce)
{
	int cpu = smp_processor_id();
	struct irqaction *action;

	if (cpu == 0)
		action = &sirfsoc_timer_irq;
	else
		action = &sirfsoc_timer1_irq;

	ce->irq = action->irq;
	ce->name = "local_timer";
	ce->features = CLOCK_EVT_FEAT_ONESHOT;
	ce->rating = 200;
	ce->set_mode = sirfsoc_timer_set_mode;
	ce->set_next_event = sirfsoc_timer_set_next_event;
	clockevents_calc_mult_shift(ce, MARCO_CLOCK_FREQ, 60);
	ce->max_delta_ns = clockevent_delta2ns(-2, ce);
	ce->min_delta_ns = clockevent_delta2ns(2, ce);
	ce->cpumask = cpumask_of(cpu);

	action->dev_id = ce;
	BUG_ON(setup_irq(ce->irq, action));
	irq_force_affinity(action->irq, cpumask_of(cpu));

	clockevents_register_device(ce);
	return 0;
}

static void sirfsoc_local_timer_stop(struct clock_event_device *ce)
{
	int cpu = smp_processor_id();

	sirfsoc_timer_count_disable(1);

	if (cpu == 0)
		remove_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
	else
		remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
}

static int sirfsoc_cpu_notify(struct notifier_block *self,
			      unsigned long action, void *hcpu)
{
	/*
	 * Grab cpu pointer in each case to avoid spurious
	 * preemptible warnings
	 */
	switch (action & ~CPU_TASKS_FROZEN) {
	case CPU_STARTING:
		sirfsoc_local_timer_setup(this_cpu_ptr(sirfsoc_clockevent));
		break;
	case CPU_DYING:
		sirfsoc_local_timer_stop(this_cpu_ptr(sirfsoc_clockevent));
		break;
	}

	return NOTIFY_OK;
}

static struct notifier_block sirfsoc_cpu_nb = {
	.notifier_call = sirfsoc_cpu_notify,
};

static void __init sirfsoc_clockevent_init(void)
{
	sirfsoc_clockevent = alloc_percpu(struct clock_event_device);
	BUG_ON(!sirfsoc_clockevent);

	BUG_ON(register_cpu_notifier(&sirfsoc_cpu_nb));

	/* Immediately configure the timer on the boot CPU */
	sirfsoc_local_timer_setup(this_cpu_ptr(sirfsoc_clockevent));
}

/* initialize the kernel jiffy timer source */
static void __init sirfsoc_marco_timer_init(struct device_node *np)
{
	unsigned long rate;
	u32 timer_div;
	struct clk *clk;

	clk = of_clk_get(np, 0);
	BUG_ON(IS_ERR(clk));

	BUG_ON(clk_prepare_enable(clk));

	rate = clk_get_rate(clk);

	BUG_ON(rate < MARCO_CLOCK_FREQ);
	BUG_ON(rate % MARCO_CLOCK_FREQ);

	/* Initialize the timer dividers */
	timer_div = rate / MARCO_CLOCK_FREQ - 1;
	writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
	writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);

	/* Initialize timer counters to 0 */
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) |
		BIT(1) | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);

	/* Clear all interrupts */
	writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);

	BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, MARCO_CLOCK_FREQ));

	sirfsoc_clockevent_init();
}

static void __init sirfsoc_of_timer_init(struct device_node *np)
{
	sirfsoc_timer_base = of_iomap(np, 0);
	if (!sirfsoc_timer_base)
		panic("unable to map timer cpu registers\n");

	sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
	if (!sirfsoc_timer_irq.irq)
		panic("No irq passed for timer0 via DT\n");

	sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
	if (!sirfsoc_timer1_irq.irq)
		panic("No irq passed for timer1 via DT\n");

	sirfsoc_marco_timer_init(np);
}
CLOCKSOURCE_OF_DECLARE(sirfsoc_marco_timer, "sirf,marco-tick", sirfsoc_of_timer_init );
Commit	Line	Data
4898de3d BS	1	/*
	2	* System timer for CSR SiRFprimaII
	3	*
	4	* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
	5	*
	6	* Licensed under GPLv2 or later.
	7	*/
	8
	9	#include <linux/kernel.h>
	10	#include <linux/interrupt.h>
	11	#include <linux/clockchips.h>
	12	#include <linux/clocksource.h>
05a65485	13	#include <linux/cpu.h>
4898de3d BS	14	#include <linux/bitops.h>
	15	#include <linux/irq.h>
	16	#include <linux/clk.h>
	17	#include <linux/slab.h>
	18	#include <linux/of.h>
	19	#include <linux/of_irq.h>
	20	#include <linux/of_address.h>
38ff87f7	21	#include <linux/sched_clock.h>
980c51ab UKK	22
980c51ab UKK	23	#define MARCO_CLOCK_FREQ 1000000
4898de3d	24
4898de3d BS	25	#define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000
	26	#define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004
	27	#define SIRFSOC_TIMER_MATCH_0 0x0018
	28	#define SIRFSOC_TIMER_MATCH_1 0x001c
	29	#define SIRFSOC_TIMER_COUNTER_0 0x0048
	30	#define SIRFSOC_TIMER_COUNTER_1 0x004c
	31	#define SIRFSOC_TIMER_INTR_STATUS 0x0060
	32	#define SIRFSOC_TIMER_WATCHDOG_EN 0x0064
	33	#define SIRFSOC_TIMER_64COUNTER_CTRL 0x0068
	34	#define SIRFSOC_TIMER_64COUNTER_LO 0x006c
	35	#define SIRFSOC_TIMER_64COUNTER_HI 0x0070
	36	#define SIRFSOC_TIMER_64COUNTER_LOAD_LO 0x0074
	37	#define SIRFSOC_TIMER_64COUNTER_LOAD_HI 0x0078
	38	#define SIRFSOC_TIMER_64COUNTER_RLATCHED_LO 0x007c
	39	#define SIRFSOC_TIMER_64COUNTER_RLATCHED_HI 0x0080
	40
	41	#define SIRFSOC_TIMER_REG_CNT 6
	42
	43	static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
	44	SIRFSOC_TIMER_WATCHDOG_EN,
	45	SIRFSOC_TIMER_32COUNTER_0_CTRL,
	46	SIRFSOC_TIMER_32COUNTER_1_CTRL,
	47	SIRFSOC_TIMER_64COUNTER_CTRL,
	48	SIRFSOC_TIMER_64COUNTER_RLATCHED_LO,
	49	SIRFSOC_TIMER_64COUNTER_RLATCHED_HI,
	50	};
	51
	52	static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
	53
	54	static void __iomem *sirfsoc_timer_base;
4898de3d BS	55
	56	/* disable count and interrupt */
	57	static inline void sirfsoc_timer_count_disable(int idx)
	58	{
	59	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7,
	60	sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
	61	}
	62
	63	/* enable count and interrupt */
	64	static inline void sirfsoc_timer_count_enable(int idx)
	65	{
28cf3567	66	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) \| 0x3,
4898de3d BS	67	sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx);
	68	}
	69
	70	/* timer interrupt handler */
	71	static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
	72	{
	73	struct clock_event_device *ce = dev_id;
	74	int cpu = smp_processor_id();
	75
	76	/* clear timer interrupt */
	77	writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
	78
	79	if (ce->mode == CLOCK_EVT_MODE_ONESHOT)
	80	sirfsoc_timer_count_disable(cpu);
	81
	82	ce->event_handler(ce);
	83
	84	return IRQ_HANDLED;
	85	}
	86
	87	/* read 64-bit timer counter */
	88	static cycle_t sirfsoc_timer_read(struct clocksource *cs)
	89	{
	90	u64 cycles;
	91
	92	writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) \|
	93	BIT(0)) & ~BIT(1), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	94
	95	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI);
	96	cycles = (cycles << 32) \| readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO);
	97
	98	return cycles;
	99	}
	100
	101	static int sirfsoc_timer_set_next_event(unsigned long delta,
	102	struct clock_event_device *ce)
	103	{
	104	int cpu = smp_processor_id();
	105
28cf3567 HL	106	/* disable timer first, then modify the related registers */
	107	sirfsoc_timer_count_disable(cpu);
	108
4898de3d BS	109	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 +
	110	4 * cpu);
	111	writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 +
	112	4 * cpu);
	113
	114	/* enable the tick */
	115	sirfsoc_timer_count_enable(cpu);
	116
	117	return 0;
	118	}
	119
	120	static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
	121	struct clock_event_device *ce)
	122	{
	123	switch (mode) {
	124	case CLOCK_EVT_MODE_ONESHOT:
	125	/* enable in set_next_event */
	126	break;
	127	default:
	128	break;
	129	}
	130
	131	sirfsoc_timer_count_disable(smp_processor_id());
	132	}
	133
	134	static void sirfsoc_clocksource_suspend(struct clocksource *cs)
	135	{
	136	int i;
	137
	138	for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
	139	sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
	140	}
	141
	142	static void sirfsoc_clocksource_resume(struct clocksource *cs)
	143	{
	144	int i;
	145
	146	for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
	147	writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
	148
	149	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
	150	sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
	151	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
	152	sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
	153
	154	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) \|
	155	BIT(1) \| BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	156	}
	157
05a65485	158	static struct clock_event_device __percpu *sirfsoc_clockevent;
4898de3d BS	159
	160	static struct clocksource sirfsoc_clocksource = {
	161	.name = "sirfsoc_clocksource",
	162	.rating = 200,
	163	.mask = CLOCKSOURCE_MASK(64),
	164	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	165	.read = sirfsoc_timer_read,
	166	.suspend = sirfsoc_clocksource_suspend,
	167	.resume = sirfsoc_clocksource_resume,
	168	};
	169
	170	static struct irqaction sirfsoc_timer_irq = {
	171	.name = "sirfsoc_timer0",
	172	.flags = IRQF_TIMER \| IRQF_NOBALANCING,
	173	.handler = sirfsoc_timer_interrupt,
4898de3d BS	174	};
4898de3d BS	175
4898de3d BS	176	static struct irqaction sirfsoc_timer1_irq = {
	177	.name = "sirfsoc_timer1",
	178	.flags = IRQF_TIMER \| IRQF_NOBALANCING,
	179	.handler = sirfsoc_timer_interrupt,
	180	};
	181
8c37bb3a	182	static int sirfsoc_local_timer_setup(struct clock_event_device *ce)
4898de3d	183	{
05a65485 SB	184	int cpu = smp_processor_id();
	185	struct irqaction *action;
	186
	187	if (cpu == 0)
	188	action = &sirfsoc_timer_irq;
	189	else
	190	action = &sirfsoc_timer1_irq;
4898de3d	191
05a65485	192	ce->irq = action->irq;
4898de3d	193	ce->name = "local_timer";
05a65485 SB	194	ce->features = CLOCK_EVT_FEAT_ONESHOT;
05a65485 SB	195	ce->rating = 200;
4898de3d BS	196	ce->set_mode = sirfsoc_timer_set_mode;
4898de3d BS	197	ce->set_next_event = sirfsoc_timer_set_next_event;
980c51ab	198	clockevents_calc_mult_shift(ce, MARCO_CLOCK_FREQ, 60);
05a65485 SB	199	ce->max_delta_ns = clockevent_delta2ns(-2, ce);
	200	ce->min_delta_ns = clockevent_delta2ns(2, ce);
	201	ce->cpumask = cpumask_of(cpu);
4898de3d	202
05a65485 SB	203	action->dev_id = ce;
05a65485 SB	204	BUG_ON(setup_irq(ce->irq, action));
f214be50	205	irq_force_affinity(action->irq, cpumask_of(cpu));
4898de3d BS	206
	207	clockevents_register_device(ce);
	208	return 0;
	209	}
	210
	211	static void sirfsoc_local_timer_stop(struct clock_event_device *ce)
	212	{
05a65485 SB	213	int cpu = smp_processor_id();
05a65485 SB	214
4898de3d BS	215	sirfsoc_timer_count_disable(1);
4898de3d BS	216
05a65485 SB	217	if (cpu == 0)
	218	remove_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
	219	else
	220	remove_irq(sirfsoc_timer1_irq.irq, &sirfsoc_timer1_irq);
4898de3d BS	221	}
4898de3d BS	222
47dcd356 OJ	223	static int sirfsoc_cpu_notify(struct notifier_block *self,
47dcd356 OJ	224	unsigned long action, void *hcpu)
05a65485 SB	225	{
	226	/*
	227	* Grab cpu pointer in each case to avoid spurious
	228	* preemptible warnings
	229	*/
	230	switch (action & ~CPU_TASKS_FROZEN) {
	231	case CPU_STARTING:
	232	sirfsoc_local_timer_setup(this_cpu_ptr(sirfsoc_clockevent));
	233	break;
	234	case CPU_DYING:
	235	sirfsoc_local_timer_stop(this_cpu_ptr(sirfsoc_clockevent));
	236	break;
	237	}
	238
	239	return NOTIFY_OK;
	240	}
	241
47dcd356	242	static struct notifier_block sirfsoc_cpu_nb = {
05a65485	243	.notifier_call = sirfsoc_cpu_notify,
4898de3d	244	};
4898de3d BS	245
	246	static void __init sirfsoc_clockevent_init(void)
	247	{
05a65485 SB	248	sirfsoc_clockevent = alloc_percpu(struct clock_event_device);
	249	BUG_ON(!sirfsoc_clockevent);
	250
	251	BUG_ON(register_cpu_notifier(&sirfsoc_cpu_nb));
	252
	253	/* Immediately configure the timer on the boot CPU */
	254	sirfsoc_local_timer_setup(this_cpu_ptr(sirfsoc_clockevent));
4898de3d BS	255	}
	256
	257	/* initialize the kernel jiffy timer source */
c7cff54d	258	static void __init sirfsoc_marco_timer_init(struct device_node *np)
4898de3d BS	259	{
	260	unsigned long rate;
	261	u32 timer_div;
	262	struct clk *clk;
	263
c7cff54d	264	clk = of_clk_get(np, 0);
4898de3d	265	BUG_ON(IS_ERR(clk));
38941522 ZS	266
	267	BUG_ON(clk_prepare_enable(clk));
	268
4898de3d BS	269	rate = clk_get_rate(clk);
4898de3d BS	270
980c51ab UKK	271	BUG_ON(rate < MARCO_CLOCK_FREQ);
980c51ab UKK	272	BUG_ON(rate % MARCO_CLOCK_FREQ);
4898de3d	273
4898de3d	274	/* Initialize the timer dividers */
980c51ab	275	timer_div = rate / MARCO_CLOCK_FREQ - 1;
4898de3d BS	276	writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	277	writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL);
	278	writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_1_CTRL);
	279
	280	/* Initialize timer counters to 0 */
	281	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_LO);
	282	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_LOAD_HI);
	283	writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) \|
	284	BIT(1) \| BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL);
	285	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0);
	286	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_1);
	287
	288	/* Clear all interrupts */
	289	writel_relaxed(0xFFFF, sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS);
	290
980c51ab	291	BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, MARCO_CLOCK_FREQ));
4898de3d	292
4898de3d BS	293	sirfsoc_clockevent_init();
	294	}
	295
275786b7	296	static void __init sirfsoc_of_timer_init(struct device_node *np)
4898de3d	297	{
4898de3d BS	298	sirfsoc_timer_base = of_iomap(np, 0);
	299	if (!sirfsoc_timer_base)
	300	panic("unable to map timer cpu registers\n");
	301
	302	sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
	303	if (!sirfsoc_timer_irq.irq)
	304	panic("No irq passed for timer0 via DT\n");
	305
4898de3d BS	306	sirfsoc_timer1_irq.irq = irq_of_parse_and_map(np, 1);
	307	if (!sirfsoc_timer1_irq.irq)
	308	panic("No irq passed for timer1 via DT\n");
4898de3d	309
c7cff54d	310	sirfsoc_marco_timer_init(np);
4898de3d	311	}
275786b7	312	CLOCKSOURCE_OF_DECLARE(sirfsoc_marco_timer, "sirf,marco-tick", sirfsoc_of_timer_init );