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e37e4593 MC |
1 | /* |
2 | * Copyright (C) Maxime Coquelin 2015 | |
3 | * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> | |
4 | * License terms: GNU General Public License (GPL), version 2 | |
5 | * | |
6 | * Inspired by time-efm32.c from Uwe Kleine-Koenig | |
7 | */ | |
8 | ||
9 | #include <linux/kernel.h> | |
10 | #include <linux/clocksource.h> | |
11 | #include <linux/clockchips.h> | |
12 | #include <linux/irq.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/of.h> | |
15 | #include <linux/of_address.h> | |
16 | #include <linux/of_irq.h> | |
17 | #include <linux/clk.h> | |
18 | #include <linux/reset.h> | |
19 | ||
20 | #define TIM_CR1 0x00 | |
21 | #define TIM_DIER 0x0c | |
22 | #define TIM_SR 0x10 | |
23 | #define TIM_EGR 0x14 | |
24 | #define TIM_PSC 0x28 | |
25 | #define TIM_ARR 0x2c | |
26 | ||
27 | #define TIM_CR1_CEN BIT(0) | |
28 | #define TIM_CR1_OPM BIT(3) | |
29 | #define TIM_CR1_ARPE BIT(7) | |
30 | ||
31 | #define TIM_DIER_UIE BIT(0) | |
32 | ||
33 | #define TIM_SR_UIF BIT(0) | |
34 | ||
35 | #define TIM_EGR_UG BIT(0) | |
36 | ||
37 | struct stm32_clock_event_ddata { | |
38 | struct clock_event_device evtdev; | |
39 | unsigned periodic_top; | |
40 | void __iomem *base; | |
41 | }; | |
42 | ||
43 | static void stm32_clock_event_set_mode(enum clock_event_mode mode, | |
44 | struct clock_event_device *evtdev) | |
45 | { | |
46 | struct stm32_clock_event_ddata *data = | |
47 | container_of(evtdev, struct stm32_clock_event_ddata, evtdev); | |
48 | void *base = data->base; | |
49 | ||
50 | switch (mode) { | |
51 | case CLOCK_EVT_MODE_PERIODIC: | |
52 | writel_relaxed(data->periodic_top, base + TIM_ARR); | |
53 | writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, base + TIM_CR1); | |
54 | break; | |
55 | ||
56 | case CLOCK_EVT_MODE_ONESHOT: | |
57 | default: | |
58 | writel_relaxed(0, base + TIM_CR1); | |
59 | break; | |
60 | } | |
61 | } | |
62 | ||
63 | static int stm32_clock_event_set_next_event(unsigned long evt, | |
64 | struct clock_event_device *evtdev) | |
65 | { | |
66 | struct stm32_clock_event_ddata *data = | |
67 | container_of(evtdev, struct stm32_clock_event_ddata, evtdev); | |
68 | ||
69 | writel_relaxed(evt, data->base + TIM_ARR); | |
70 | writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN, | |
71 | data->base + TIM_CR1); | |
72 | ||
73 | return 0; | |
74 | } | |
75 | ||
76 | static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) | |
77 | { | |
78 | struct stm32_clock_event_ddata *data = dev_id; | |
79 | ||
80 | writel_relaxed(0, data->base + TIM_SR); | |
81 | ||
82 | data->evtdev.event_handler(&data->evtdev); | |
83 | ||
84 | return IRQ_HANDLED; | |
85 | } | |
86 | ||
87 | static struct stm32_clock_event_ddata clock_event_ddata = { | |
88 | .evtdev = { | |
89 | .name = "stm32 clockevent", | |
90 | .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, | |
91 | .set_mode = stm32_clock_event_set_mode, | |
92 | .set_next_event = stm32_clock_event_set_next_event, | |
93 | .rating = 200, | |
94 | }, | |
95 | }; | |
96 | ||
97 | static void __init stm32_clockevent_init(struct device_node *np) | |
98 | { | |
99 | struct stm32_clock_event_ddata *data = &clock_event_ddata; | |
100 | struct clk *clk; | |
101 | struct reset_control *rstc; | |
102 | unsigned long rate, max_delta; | |
103 | int irq, ret, bits, prescaler = 1; | |
104 | ||
105 | clk = of_clk_get(np, 0); | |
106 | if (IS_ERR(clk)) { | |
107 | ret = PTR_ERR(clk); | |
108 | pr_err("failed to get clock for clockevent (%d)\n", ret); | |
109 | goto err_clk_get; | |
110 | } | |
111 | ||
112 | ret = clk_prepare_enable(clk); | |
113 | if (ret) { | |
114 | pr_err("failed to enable timer clock for clockevent (%d)\n", | |
115 | ret); | |
116 | goto err_clk_enable; | |
117 | } | |
118 | ||
119 | rate = clk_get_rate(clk); | |
120 | ||
121 | rstc = of_reset_control_get(np, NULL); | |
122 | if (!IS_ERR(rstc)) { | |
123 | reset_control_assert(rstc); | |
124 | reset_control_deassert(rstc); | |
125 | } | |
126 | ||
127 | data->base = of_iomap(np, 0); | |
128 | if (!data->base) { | |
129 | pr_err("failed to map registers for clockevent\n"); | |
130 | goto err_iomap; | |
131 | } | |
132 | ||
133 | irq = irq_of_parse_and_map(np, 0); | |
134 | if (!irq) { | |
135 | pr_err("%s: failed to get irq.\n", np->full_name); | |
136 | goto err_get_irq; | |
137 | } | |
138 | ||
139 | /* Detect whether the timer is 16 or 32 bits */ | |
d4688bdc | 140 | writel_relaxed(~0U, data->base + TIM_ARR); |
e37e4593 | 141 | max_delta = readl_relaxed(data->base + TIM_ARR); |
d4688bdc | 142 | if (max_delta == ~0U) { |
e37e4593 MC |
143 | prescaler = 1; |
144 | bits = 32; | |
145 | } else { | |
146 | prescaler = 1024; | |
147 | bits = 16; | |
148 | } | |
149 | writel_relaxed(0, data->base + TIM_ARR); | |
150 | ||
151 | writel_relaxed(prescaler - 1, data->base + TIM_PSC); | |
152 | writel_relaxed(TIM_EGR_UG, data->base + TIM_EGR); | |
153 | writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER); | |
154 | writel_relaxed(0, data->base + TIM_SR); | |
155 | ||
156 | data->periodic_top = DIV_ROUND_CLOSEST(rate, prescaler * HZ); | |
157 | ||
158 | clockevents_config_and_register(&data->evtdev, | |
159 | DIV_ROUND_CLOSEST(rate, prescaler), | |
160 | 0x1, max_delta); | |
161 | ||
162 | ret = request_irq(irq, stm32_clock_event_handler, IRQF_TIMER, | |
163 | "stm32 clockevent", data); | |
164 | if (ret) { | |
165 | pr_err("%s: failed to request irq.\n", np->full_name); | |
166 | goto err_get_irq; | |
167 | } | |
168 | ||
169 | pr_info("%s: STM32 clockevent driver initialized (%d bits)\n", | |
170 | np->full_name, bits); | |
171 | ||
172 | return; | |
173 | ||
174 | err_get_irq: | |
175 | iounmap(data->base); | |
176 | err_iomap: | |
177 | clk_disable_unprepare(clk); | |
178 | err_clk_enable: | |
179 | clk_put(clk); | |
180 | err_clk_get: | |
181 | return; | |
182 | } | |
183 | ||
184 | CLOCKSOURCE_OF_DECLARE(stm32, "st,stm32-timer", stm32_clockevent_init); |