[deliverable/linux.git] / drivers / clocksource / timer-sun5i.c

/*
 * Allwinner SoCs hstimer driver.
 *
 * Copyright (C) 2013 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqreturn.h>
#include <linux/reset.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#define TIMER_IRQ_EN_REG		0x00
#define TIMER_IRQ_EN(val)			BIT(val)
#define TIMER_IRQ_ST_REG		0x04
#define TIMER_CTL_REG(val)		(0x20 * (val) + 0x10)
#define TIMER_CTL_ENABLE			BIT(0)
#define TIMER_CTL_RELOAD			BIT(1)
#define TIMER_CTL_CLK_PRES(val)			(((val) & 0x7) << 4)
#define TIMER_CTL_ONESHOT			BIT(7)
#define TIMER_INTVAL_LO_REG(val)	(0x20 * (val) + 0x14)
#define TIMER_INTVAL_HI_REG(val)	(0x20 * (val) + 0x18)
#define TIMER_CNTVAL_LO_REG(val)	(0x20 * (val) + 0x1c)
#define TIMER_CNTVAL_HI_REG(val)	(0x20 * (val) + 0x20)

#define TIMER_SYNC_TICKS	3

static void __iomem *timer_base;
static u32 ticks_per_jiffy;

/*
 * When we disable a timer, we need to wait at least for 2 cycles of
 * the timer source clock. We will use for that the clocksource timer
 * that is already setup and runs at the same frequency than the other
 * timers, and we never will be disabled.
 */
static void sun5i_clkevt_sync(void)
{
	u32 old = readl(timer_base + TIMER_CNTVAL_LO_REG(1));

	while ((old - readl(timer_base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
		cpu_relax();
}

static void sun5i_clkevt_time_stop(u8 timer)
{
	u32 val = readl(timer_base + TIMER_CTL_REG(timer));
	writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));

	sun5i_clkevt_sync();
}

static void sun5i_clkevt_time_setup(u8 timer, u32 delay)
{
	writel(delay, timer_base + TIMER_INTVAL_LO_REG(timer));
}

static void sun5i_clkevt_time_start(u8 timer, bool periodic)
{
	u32 val = readl(timer_base + TIMER_CTL_REG(timer));

	if (periodic)
		val &= ~TIMER_CTL_ONESHOT;
	else
		val |= TIMER_CTL_ONESHOT;

	writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
	       timer_base + TIMER_CTL_REG(timer));
}

static void sun5i_clkevt_mode(enum clock_event_mode mode,
			      struct clock_event_device *clk)
{
	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		sun5i_clkevt_time_stop(0);
		sun5i_clkevt_time_setup(0, ticks_per_jiffy);
		sun5i_clkevt_time_start(0, true);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		sun5i_clkevt_time_stop(0);
		sun5i_clkevt_time_start(0, false);
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	default:
		sun5i_clkevt_time_stop(0);
		break;
	}
}

static int sun5i_clkevt_next_event(unsigned long evt,
				   struct clock_event_device *unused)
{
	sun5i_clkevt_time_stop(0);
	sun5i_clkevt_time_setup(0, evt - TIMER_SYNC_TICKS);
	sun5i_clkevt_time_start(0, false);

	return 0;
}

static struct clock_event_device sun5i_clockevent = {
	.name = "sun5i_tick",
	.rating = 340,
	.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.set_mode = sun5i_clkevt_mode,
	.set_next_event = sun5i_clkevt_next_event,
};


static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = (struct clock_event_device *)dev_id;

	writel(0x1, timer_base + TIMER_IRQ_ST_REG);
	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static struct irqaction sun5i_timer_irq = {
	.name = "sun5i_timer0",
	.flags = IRQF_TIMER | IRQF_IRQPOLL,
	.handler = sun5i_timer_interrupt,
	.dev_id = &sun5i_clockevent,
};

static void __init sun5i_timer_init(struct device_node *node)
{
	struct reset_control *rstc;
	unsigned long rate;
	struct clk *clk;
	int ret, irq;
	u32 val;

	timer_base = of_iomap(node, 0);
	if (!timer_base)
		panic("Can't map registers");

	irq = irq_of_parse_and_map(node, 0);
	if (irq <= 0)
		panic("Can't parse IRQ");

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk))
		panic("Can't get timer clock");
	clk_prepare_enable(clk);
	rate = clk_get_rate(clk);

	rstc = of_reset_control_get(node, NULL);
	if (!IS_ERR(rstc))
		reset_control_deassert(rstc);

	writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
	writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
	       timer_base + TIMER_CTL_REG(1));

	clocksource_mmio_init(timer_base + TIMER_CNTVAL_LO_REG(1), node->name,
			      rate, 340, 32, clocksource_mmio_readl_down);

	ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);

	/* Enable timer0 interrupt */
	val = readl(timer_base + TIMER_IRQ_EN_REG);
	writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);

	sun5i_clockevent.cpumask = cpu_possible_mask;
	sun5i_clockevent.irq = irq;

	clockevents_config_and_register(&sun5i_clockevent, rate,
					TIMER_SYNC_TICKS, 0xffffffff);

	ret = setup_irq(irq, &sun5i_timer_irq);
	if (ret)
		pr_warn("failed to setup irq %d\n", irq);
}
CLOCKSOURCE_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
		       sun5i_timer_init);
CLOCKSOURCE_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
		       sun5i_timer_init);
Commit	Line	Data
67905540 MR	1	/*
	2	* Allwinner SoCs hstimer driver.
	3	*
	4	* Copyright (C) 2013 Maxime Ripard
	5	*
	6	* Maxime Ripard <maxime.ripard@free-electrons.com>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#include <linux/clk.h>
	14	#include <linux/clockchips.h>
	15	#include <linux/delay.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/irq.h>
	18	#include <linux/irqreturn.h>
e50a00be	19	#include <linux/reset.h>
67905540 MR	20	#include <linux/of.h>
	21	#include <linux/of_address.h>
	22	#include <linux/of_irq.h>
	23
	24	#define TIMER_IRQ_EN_REG 0x00
	25	#define TIMER_IRQ_EN(val) BIT(val)
	26	#define TIMER_IRQ_ST_REG 0x04
	27	#define TIMER_CTL_REG(val) (0x20 * (val) + 0x10)
	28	#define TIMER_CTL_ENABLE BIT(0)
	29	#define TIMER_CTL_RELOAD BIT(1)
	30	#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
	31	#define TIMER_CTL_ONESHOT BIT(7)
	32	#define TIMER_INTVAL_LO_REG(val) (0x20 * (val) + 0x14)
	33	#define TIMER_INTVAL_HI_REG(val) (0x20 * (val) + 0x18)
	34	#define TIMER_CNTVAL_LO_REG(val) (0x20 * (val) + 0x1c)
	35	#define TIMER_CNTVAL_HI_REG(val) (0x20 * (val) + 0x20)
	36
	37	#define TIMER_SYNC_TICKS 3
	38
	39	static void __iomem *timer_base;
	40	static u32 ticks_per_jiffy;
	41
	42	/*
	43	* When we disable a timer, we need to wait at least for 2 cycles of
	44	* the timer source clock. We will use for that the clocksource timer
	45	* that is already setup and runs at the same frequency than the other
	46	* timers, and we never will be disabled.
	47	*/
	48	static void sun5i_clkevt_sync(void)
	49	{
	50	u32 old = readl(timer_base + TIMER_CNTVAL_LO_REG(1));
	51
	52	while ((old - readl(timer_base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
	53	cpu_relax();
	54	}
	55
	56	static void sun5i_clkevt_time_stop(u8 timer)
	57	{
	58	u32 val = readl(timer_base + TIMER_CTL_REG(timer));
	59	writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer));
	60
	61	sun5i_clkevt_sync();
	62	}
	63
	64	static void sun5i_clkevt_time_setup(u8 timer, u32 delay)
	65	{
	66	writel(delay, timer_base + TIMER_INTVAL_LO_REG(timer));
	67	}
	68
	69	static void sun5i_clkevt_time_start(u8 timer, bool periodic)
	70	{
	71	u32 val = readl(timer_base + TIMER_CTL_REG(timer));
	72
	73	if (periodic)
	74	val &= ~TIMER_CTL_ONESHOT;
	75	else
	76	val \|= TIMER_CTL_ONESHOT;
	77
	78	writel(val \| TIMER_CTL_ENABLE \| TIMER_CTL_RELOAD,
	79	timer_base + TIMER_CTL_REG(timer));
	80	}
	81
	82	static void sun5i_clkevt_mode(enum clock_event_mode mode,
	83	struct clock_event_device *clk)
84	{
85	switch (mode) {
86	case CLOCK_EVT_MODE_PERIODIC:
87	sun5i_clkevt_time_stop(0);
88	sun5i_clkevt_time_setup(0, ticks_per_jiffy);
89	sun5i_clkevt_time_start(0, true);
90	break;
91	case CLOCK_EVT_MODE_ONESHOT:
92	sun5i_clkevt_time_stop(0);
93	sun5i_clkevt_time_start(0, false);
94	break;
95	case CLOCK_EVT_MODE_UNUSED:
96	case CLOCK_EVT_MODE_SHUTDOWN:
97	default:
98	sun5i_clkevt_time_stop(0);
99	break;
100	}
101	}
102
103	static int sun5i_clkevt_next_event(unsigned long evt,
104	struct clock_event_device *unused)
105	{
106	sun5i_clkevt_time_stop(0);
107	sun5i_clkevt_time_setup(0, evt - TIMER_SYNC_TICKS);
108	sun5i_clkevt_time_start(0, false);
109
110	return 0;
111	}
112
113	static struct clock_event_device sun5i_clockevent = {
114	.name = "sun5i_tick",
115	.rating = 340,
116	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
117	.set_mode = sun5i_clkevt_mode,
118	.set_next_event = sun5i_clkevt_next_event,
119	};
120
121
122	static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
123	{
124	struct clock_event_device evt = (struct clock_event_device )dev_id;
125
126	writel(0x1, timer_base + TIMER_IRQ_ST_REG);
127	evt->event_handler(evt);
128
129	return IRQ_HANDLED;
130	}
131
132	static struct irqaction sun5i_timer_irq = {
133	.name = "sun5i_timer0",
134	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
135	.handler = sun5i_timer_interrupt,
136	.dev_id = &sun5i_clockevent,
137	};
138
67905540 MR	139	static void __init sun5i_timer_init(struct device_node *node)
67905540 MR	140	{
e50a00be	141	struct reset_control *rstc;
67905540 MR	142	unsigned long rate;
	143	struct clk *clk;
	144	int ret, irq;
	145	u32 val;
	146
	147	timer_base = of_iomap(node, 0);
	148	if (!timer_base)
	149	panic("Can't map registers");
	150
	151	irq = irq_of_parse_and_map(node, 0);
	152	if (irq <= 0)
	153	panic("Can't parse IRQ");
	154
	155	clk = of_clk_get(node, 0);
	156	if (IS_ERR(clk))
	157	panic("Can't get timer clock");
	158	clk_prepare_enable(clk);
	159	rate = clk_get_rate(clk);
	160
e50a00be MR	161	rstc = of_reset_control_get(node, NULL);
	162	if (!IS_ERR(rstc))
	163	reset_control_deassert(rstc);
	164
67905540 MR	165	writel(~0, timer_base + TIMER_INTVAL_LO_REG(1));
	166	writel(TIMER_CTL_ENABLE \| TIMER_CTL_RELOAD,
	167	timer_base + TIMER_CTL_REG(1));
	168
67905540 MR	169	clocksource_mmio_init(timer_base + TIMER_CNTVAL_LO_REG(1), node->name,
	170	rate, 340, 32, clocksource_mmio_readl_down);
	171
	172	ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
	173
67905540 MR	174	/* Enable timer0 interrupt */
	175	val = readl(timer_base + TIMER_IRQ_EN_REG);
	176	writel(val \| TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
	177
	178	sun5i_clockevent.cpumask = cpu_possible_mask;
	179	sun5i_clockevent.irq = irq;
	180
	181	clockevents_config_and_register(&sun5i_clockevent, rate,
	182	TIMER_SYNC_TICKS, 0xffffffff);
1096be08 YP	183
	184	ret = setup_irq(irq, &sun5i_timer_irq);
	185	if (ret)
	186	pr_warn("failed to setup irq %d\n", irq);
67905540 MR	187	}
	188	CLOCKSOURCE_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
	189	sun5i_timer_init);
	190	CLOCKSOURCE_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
	191	sun5i_timer_init);