Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
3a58df35 | 2 | * acpi-cpufreq.c - ACPI Processor P-States Driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
6 | * Copyright (C) 2002 - 2004 Dominik Brodowski <linux@brodo.de> | |
fe27cb35 | 7 | * Copyright (C) 2006 Denis Sadykov <denis.m.sadykov@intel.com> |
1da177e4 LT |
8 | * |
9 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License along | |
22 | * with this program; if not, write to the Free Software Foundation, Inc., | |
23 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
24 | * | |
25 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
26 | */ | |
27 | ||
1da177e4 LT |
28 | #include <linux/kernel.h> |
29 | #include <linux/module.h> | |
30 | #include <linux/init.h> | |
fe27cb35 VP |
31 | #include <linux/smp.h> |
32 | #include <linux/sched.h> | |
1da177e4 | 33 | #include <linux/cpufreq.h> |
d395bf12 | 34 | #include <linux/compiler.h> |
8adcc0c6 | 35 | #include <linux/dmi.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
1da177e4 LT |
37 | |
38 | #include <linux/acpi.h> | |
3a58df35 DJ |
39 | #include <linux/io.h> |
40 | #include <linux/delay.h> | |
41 | #include <linux/uaccess.h> | |
42 | ||
1da177e4 LT |
43 | #include <acpi/processor.h> |
44 | ||
dde9f7ba | 45 | #include <asm/msr.h> |
fe27cb35 VP |
46 | #include <asm/processor.h> |
47 | #include <asm/cpufeature.h> | |
fe27cb35 | 48 | |
1da177e4 LT |
49 | MODULE_AUTHOR("Paul Diefenbaugh, Dominik Brodowski"); |
50 | MODULE_DESCRIPTION("ACPI Processor P-States Driver"); | |
51 | MODULE_LICENSE("GPL"); | |
52 | ||
acd31624 AP |
53 | #define PFX "acpi-cpufreq: " |
54 | ||
dde9f7ba VP |
55 | enum { |
56 | UNDEFINED_CAPABLE = 0, | |
57 | SYSTEM_INTEL_MSR_CAPABLE, | |
3dc9a633 | 58 | SYSTEM_AMD_MSR_CAPABLE, |
dde9f7ba VP |
59 | SYSTEM_IO_CAPABLE, |
60 | }; | |
61 | ||
62 | #define INTEL_MSR_RANGE (0xffff) | |
3dc9a633 | 63 | #define AMD_MSR_RANGE (0x7) |
dde9f7ba | 64 | |
615b7300 AP |
65 | #define MSR_K7_HWCR_CPB_DIS (1ULL << 25) |
66 | ||
fe27cb35 | 67 | struct acpi_cpufreq_data { |
64be7eed VP |
68 | struct cpufreq_frequency_table *freq_table; |
69 | unsigned int resume; | |
70 | unsigned int cpu_feature; | |
8cfcfd39 | 71 | unsigned int acpi_perf_cpu; |
f4fd3797 | 72 | cpumask_var_t freqdomain_cpus; |
1da177e4 LT |
73 | }; |
74 | ||
50109292 | 75 | /* acpi_perf_data is a pointer to percpu data. */ |
3f6c4df7 | 76 | static struct acpi_processor_performance __percpu *acpi_perf_data; |
1da177e4 | 77 | |
3427616b RW |
78 | static inline struct acpi_processor_performance *to_perf_data(struct acpi_cpufreq_data *data) |
79 | { | |
80 | return per_cpu_ptr(acpi_perf_data, data->acpi_perf_cpu); | |
81 | } | |
82 | ||
1da177e4 LT |
83 | static struct cpufreq_driver acpi_cpufreq_driver; |
84 | ||
d395bf12 | 85 | static unsigned int acpi_pstate_strict; |
615b7300 AP |
86 | static struct msr __percpu *msrs; |
87 | ||
88 | static bool boost_state(unsigned int cpu) | |
89 | { | |
90 | u32 lo, hi; | |
91 | u64 msr; | |
92 | ||
93 | switch (boot_cpu_data.x86_vendor) { | |
94 | case X86_VENDOR_INTEL: | |
95 | rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi); | |
96 | msr = lo | ((u64)hi << 32); | |
97 | return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); | |
98 | case X86_VENDOR_AMD: | |
99 | rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); | |
100 | msr = lo | ((u64)hi << 32); | |
101 | return !(msr & MSR_K7_HWCR_CPB_DIS); | |
102 | } | |
103 | return false; | |
104 | } | |
105 | ||
106 | static void boost_set_msrs(bool enable, const struct cpumask *cpumask) | |
107 | { | |
108 | u32 cpu; | |
109 | u32 msr_addr; | |
110 | u64 msr_mask; | |
111 | ||
112 | switch (boot_cpu_data.x86_vendor) { | |
113 | case X86_VENDOR_INTEL: | |
114 | msr_addr = MSR_IA32_MISC_ENABLE; | |
115 | msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE; | |
116 | break; | |
117 | case X86_VENDOR_AMD: | |
118 | msr_addr = MSR_K7_HWCR; | |
119 | msr_mask = MSR_K7_HWCR_CPB_DIS; | |
120 | break; | |
121 | default: | |
122 | return; | |
123 | } | |
124 | ||
125 | rdmsr_on_cpus(cpumask, msr_addr, msrs); | |
126 | ||
127 | for_each_cpu(cpu, cpumask) { | |
128 | struct msr *reg = per_cpu_ptr(msrs, cpu); | |
129 | if (enable) | |
130 | reg->q &= ~msr_mask; | |
131 | else | |
132 | reg->q |= msr_mask; | |
133 | } | |
134 | ||
135 | wrmsr_on_cpus(cpumask, msr_addr, msrs); | |
136 | } | |
137 | ||
cfc9c8ed | 138 | static int _store_boost(int val) |
615b7300 | 139 | { |
615b7300 | 140 | get_online_cpus(); |
615b7300 | 141 | boost_set_msrs(val, cpu_online_mask); |
615b7300 | 142 | put_online_cpus(); |
615b7300 AP |
143 | pr_debug("Core Boosting %sabled.\n", val ? "en" : "dis"); |
144 | ||
cfc9c8ed | 145 | return 0; |
615b7300 AP |
146 | } |
147 | ||
f4fd3797 LT |
148 | static ssize_t show_freqdomain_cpus(struct cpufreq_policy *policy, char *buf) |
149 | { | |
eb0b3e78 | 150 | struct acpi_cpufreq_data *data = policy->driver_data; |
f4fd3797 | 151 | |
e2530367 SP |
152 | if (unlikely(!data)) |
153 | return -ENODEV; | |
154 | ||
f4fd3797 LT |
155 | return cpufreq_show_cpus(data->freqdomain_cpus, buf); |
156 | } | |
157 | ||
158 | cpufreq_freq_attr_ro(freqdomain_cpus); | |
159 | ||
11269ff5 | 160 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
cfc9c8ed LM |
161 | static ssize_t store_boost(const char *buf, size_t count) |
162 | { | |
163 | int ret; | |
164 | unsigned long val = 0; | |
165 | ||
166 | if (!acpi_cpufreq_driver.boost_supported) | |
167 | return -EINVAL; | |
168 | ||
169 | ret = kstrtoul(buf, 10, &val); | |
170 | if (ret || (val > 1)) | |
171 | return -EINVAL; | |
172 | ||
173 | _store_boost((int) val); | |
174 | ||
175 | return count; | |
176 | } | |
177 | ||
11269ff5 AP |
178 | static ssize_t store_cpb(struct cpufreq_policy *policy, const char *buf, |
179 | size_t count) | |
180 | { | |
cfc9c8ed | 181 | return store_boost(buf, count); |
11269ff5 AP |
182 | } |
183 | ||
184 | static ssize_t show_cpb(struct cpufreq_policy *policy, char *buf) | |
185 | { | |
cfc9c8ed | 186 | return sprintf(buf, "%u\n", acpi_cpufreq_driver.boost_enabled); |
11269ff5 AP |
187 | } |
188 | ||
59027d35 | 189 | cpufreq_freq_attr_rw(cpb); |
11269ff5 AP |
190 | #endif |
191 | ||
dde9f7ba VP |
192 | static int check_est_cpu(unsigned int cpuid) |
193 | { | |
92cb7612 | 194 | struct cpuinfo_x86 *cpu = &cpu_data(cpuid); |
dde9f7ba | 195 | |
0de51088 | 196 | return cpu_has(cpu, X86_FEATURE_EST); |
dde9f7ba VP |
197 | } |
198 | ||
3dc9a633 MG |
199 | static int check_amd_hwpstate_cpu(unsigned int cpuid) |
200 | { | |
201 | struct cpuinfo_x86 *cpu = &cpu_data(cpuid); | |
202 | ||
203 | return cpu_has(cpu, X86_FEATURE_HW_PSTATE); | |
204 | } | |
205 | ||
dde9f7ba | 206 | static unsigned extract_io(u32 value, struct acpi_cpufreq_data *data) |
fe27cb35 | 207 | { |
64be7eed VP |
208 | struct acpi_processor_performance *perf; |
209 | int i; | |
fe27cb35 | 210 | |
3427616b | 211 | perf = to_perf_data(data); |
fe27cb35 | 212 | |
3a58df35 | 213 | for (i = 0; i < perf->state_count; i++) { |
fe27cb35 VP |
214 | if (value == perf->states[i].status) |
215 | return data->freq_table[i].frequency; | |
216 | } | |
217 | return 0; | |
218 | } | |
219 | ||
dde9f7ba VP |
220 | static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) |
221 | { | |
041526f9 | 222 | struct cpufreq_frequency_table *pos; |
a6f6e6e6 | 223 | struct acpi_processor_performance *perf; |
dde9f7ba | 224 | |
3dc9a633 MG |
225 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
226 | msr &= AMD_MSR_RANGE; | |
227 | else | |
228 | msr &= INTEL_MSR_RANGE; | |
229 | ||
3427616b | 230 | perf = to_perf_data(data); |
a6f6e6e6 | 231 | |
041526f9 SK |
232 | cpufreq_for_each_entry(pos, data->freq_table) |
233 | if (msr == perf->states[pos->driver_data].status) | |
234 | return pos->frequency; | |
dde9f7ba VP |
235 | return data->freq_table[0].frequency; |
236 | } | |
237 | ||
dde9f7ba VP |
238 | static unsigned extract_freq(u32 val, struct acpi_cpufreq_data *data) |
239 | { | |
240 | switch (data->cpu_feature) { | |
64be7eed | 241 | case SYSTEM_INTEL_MSR_CAPABLE: |
3dc9a633 | 242 | case SYSTEM_AMD_MSR_CAPABLE: |
dde9f7ba | 243 | return extract_msr(val, data); |
64be7eed | 244 | case SYSTEM_IO_CAPABLE: |
dde9f7ba | 245 | return extract_io(val, data); |
64be7eed | 246 | default: |
dde9f7ba VP |
247 | return 0; |
248 | } | |
249 | } | |
250 | ||
dde9f7ba VP |
251 | struct msr_addr { |
252 | u32 reg; | |
253 | }; | |
254 | ||
fe27cb35 VP |
255 | struct io_addr { |
256 | u16 port; | |
257 | u8 bit_width; | |
258 | }; | |
259 | ||
260 | struct drv_cmd { | |
dde9f7ba | 261 | unsigned int type; |
bfa318ad | 262 | const struct cpumask *mask; |
3a58df35 DJ |
263 | union { |
264 | struct msr_addr msr; | |
265 | struct io_addr io; | |
266 | } addr; | |
fe27cb35 VP |
267 | u32 val; |
268 | }; | |
269 | ||
01599fca AM |
270 | /* Called via smp_call_function_single(), on the target CPU */ |
271 | static void do_drv_read(void *_cmd) | |
1da177e4 | 272 | { |
72859081 | 273 | struct drv_cmd *cmd = _cmd; |
dde9f7ba VP |
274 | u32 h; |
275 | ||
276 | switch (cmd->type) { | |
64be7eed | 277 | case SYSTEM_INTEL_MSR_CAPABLE: |
3dc9a633 | 278 | case SYSTEM_AMD_MSR_CAPABLE: |
dde9f7ba VP |
279 | rdmsr(cmd->addr.msr.reg, cmd->val, h); |
280 | break; | |
64be7eed | 281 | case SYSTEM_IO_CAPABLE: |
4e581ff1 VP |
282 | acpi_os_read_port((acpi_io_address)cmd->addr.io.port, |
283 | &cmd->val, | |
284 | (u32)cmd->addr.io.bit_width); | |
dde9f7ba | 285 | break; |
64be7eed | 286 | default: |
dde9f7ba VP |
287 | break; |
288 | } | |
fe27cb35 | 289 | } |
1da177e4 | 290 | |
01599fca AM |
291 | /* Called via smp_call_function_many(), on the target CPUs */ |
292 | static void do_drv_write(void *_cmd) | |
fe27cb35 | 293 | { |
72859081 | 294 | struct drv_cmd *cmd = _cmd; |
13424f65 | 295 | u32 lo, hi; |
dde9f7ba VP |
296 | |
297 | switch (cmd->type) { | |
64be7eed | 298 | case SYSTEM_INTEL_MSR_CAPABLE: |
13424f65 VP |
299 | rdmsr(cmd->addr.msr.reg, lo, hi); |
300 | lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE); | |
301 | wrmsr(cmd->addr.msr.reg, lo, hi); | |
dde9f7ba | 302 | break; |
3dc9a633 MG |
303 | case SYSTEM_AMD_MSR_CAPABLE: |
304 | wrmsr(cmd->addr.msr.reg, cmd->val, 0); | |
305 | break; | |
64be7eed | 306 | case SYSTEM_IO_CAPABLE: |
4e581ff1 VP |
307 | acpi_os_write_port((acpi_io_address)cmd->addr.io.port, |
308 | cmd->val, | |
309 | (u32)cmd->addr.io.bit_width); | |
dde9f7ba | 310 | break; |
64be7eed | 311 | default: |
dde9f7ba VP |
312 | break; |
313 | } | |
fe27cb35 | 314 | } |
1da177e4 | 315 | |
95dd7227 | 316 | static void drv_read(struct drv_cmd *cmd) |
fe27cb35 | 317 | { |
4a28395d | 318 | int err; |
fe27cb35 VP |
319 | cmd->val = 0; |
320 | ||
4a28395d AM |
321 | err = smp_call_function_any(cmd->mask, do_drv_read, cmd, 1); |
322 | WARN_ON_ONCE(err); /* smp_call_function_any() was buggy? */ | |
fe27cb35 VP |
323 | } |
324 | ||
325 | static void drv_write(struct drv_cmd *cmd) | |
326 | { | |
ea34f43a LT |
327 | int this_cpu; |
328 | ||
329 | this_cpu = get_cpu(); | |
330 | if (cpumask_test_cpu(this_cpu, cmd->mask)) | |
331 | do_drv_write(cmd); | |
01599fca | 332 | smp_call_function_many(cmd->mask, do_drv_write, cmd, 1); |
ea34f43a | 333 | put_cpu(); |
fe27cb35 | 334 | } |
1da177e4 | 335 | |
eb0b3e78 PX |
336 | static u32 |
337 | get_cur_val(const struct cpumask *mask, struct acpi_cpufreq_data *data) | |
fe27cb35 | 338 | { |
64be7eed VP |
339 | struct acpi_processor_performance *perf; |
340 | struct drv_cmd cmd; | |
1da177e4 | 341 | |
4d8bb537 | 342 | if (unlikely(cpumask_empty(mask))) |
fe27cb35 | 343 | return 0; |
1da177e4 | 344 | |
eb0b3e78 | 345 | switch (data->cpu_feature) { |
dde9f7ba VP |
346 | case SYSTEM_INTEL_MSR_CAPABLE: |
347 | cmd.type = SYSTEM_INTEL_MSR_CAPABLE; | |
8673b83b | 348 | cmd.addr.msr.reg = MSR_IA32_PERF_CTL; |
dde9f7ba | 349 | break; |
3dc9a633 MG |
350 | case SYSTEM_AMD_MSR_CAPABLE: |
351 | cmd.type = SYSTEM_AMD_MSR_CAPABLE; | |
8673b83b | 352 | cmd.addr.msr.reg = MSR_AMD_PERF_CTL; |
3dc9a633 | 353 | break; |
dde9f7ba VP |
354 | case SYSTEM_IO_CAPABLE: |
355 | cmd.type = SYSTEM_IO_CAPABLE; | |
3427616b | 356 | perf = to_perf_data(data); |
dde9f7ba VP |
357 | cmd.addr.io.port = perf->control_register.address; |
358 | cmd.addr.io.bit_width = perf->control_register.bit_width; | |
359 | break; | |
360 | default: | |
361 | return 0; | |
362 | } | |
363 | ||
bfa318ad | 364 | cmd.mask = mask; |
fe27cb35 | 365 | drv_read(&cmd); |
1da177e4 | 366 | |
2d06d8c4 | 367 | pr_debug("get_cur_val = %u\n", cmd.val); |
fe27cb35 VP |
368 | |
369 | return cmd.val; | |
370 | } | |
1da177e4 | 371 | |
fe27cb35 VP |
372 | static unsigned int get_cur_freq_on_cpu(unsigned int cpu) |
373 | { | |
eb0b3e78 PX |
374 | struct acpi_cpufreq_data *data; |
375 | struct cpufreq_policy *policy; | |
64be7eed | 376 | unsigned int freq; |
e56a727b | 377 | unsigned int cached_freq; |
fe27cb35 | 378 | |
2d06d8c4 | 379 | pr_debug("get_cur_freq_on_cpu (%d)\n", cpu); |
fe27cb35 | 380 | |
1f0bd44e | 381 | policy = cpufreq_cpu_get_raw(cpu); |
eb0b3e78 PX |
382 | if (unlikely(!policy)) |
383 | return 0; | |
384 | ||
385 | data = policy->driver_data; | |
3427616b | 386 | if (unlikely(!data || !data->freq_table)) |
fe27cb35 | 387 | return 0; |
1da177e4 | 388 | |
3427616b | 389 | cached_freq = data->freq_table[to_perf_data(data)->state].frequency; |
eb0b3e78 | 390 | freq = extract_freq(get_cur_val(cpumask_of(cpu), data), data); |
e56a727b VP |
391 | if (freq != cached_freq) { |
392 | /* | |
393 | * The dreaded BIOS frequency change behind our back. | |
394 | * Force set the frequency on next target call. | |
395 | */ | |
396 | data->resume = 1; | |
397 | } | |
398 | ||
2d06d8c4 | 399 | pr_debug("cur freq = %u\n", freq); |
1da177e4 | 400 | |
fe27cb35 | 401 | return freq; |
1da177e4 LT |
402 | } |
403 | ||
72859081 | 404 | static unsigned int check_freqs(const struct cpumask *mask, unsigned int freq, |
64be7eed | 405 | struct acpi_cpufreq_data *data) |
fe27cb35 | 406 | { |
64be7eed VP |
407 | unsigned int cur_freq; |
408 | unsigned int i; | |
1da177e4 | 409 | |
3a58df35 | 410 | for (i = 0; i < 100; i++) { |
eb0b3e78 | 411 | cur_freq = extract_freq(get_cur_val(mask, data), data); |
fe27cb35 VP |
412 | if (cur_freq == freq) |
413 | return 1; | |
414 | udelay(10); | |
415 | } | |
416 | return 0; | |
417 | } | |
418 | ||
419 | static int acpi_cpufreq_target(struct cpufreq_policy *policy, | |
9c0ebcf7 | 420 | unsigned int index) |
1da177e4 | 421 | { |
eb0b3e78 | 422 | struct acpi_cpufreq_data *data = policy->driver_data; |
64be7eed | 423 | struct acpi_processor_performance *perf; |
64be7eed | 424 | struct drv_cmd cmd; |
8edc59d9 | 425 | unsigned int next_perf_state = 0; /* Index into perf table */ |
64be7eed | 426 | int result = 0; |
fe27cb35 | 427 | |
3427616b | 428 | if (unlikely(data == NULL || data->freq_table == NULL)) { |
fe27cb35 VP |
429 | return -ENODEV; |
430 | } | |
1da177e4 | 431 | |
3427616b | 432 | perf = to_perf_data(data); |
9c0ebcf7 | 433 | next_perf_state = data->freq_table[index].driver_data; |
7650b281 | 434 | if (perf->state == next_perf_state) { |
fe27cb35 | 435 | if (unlikely(data->resume)) { |
2d06d8c4 | 436 | pr_debug("Called after resume, resetting to P%d\n", |
64be7eed | 437 | next_perf_state); |
fe27cb35 VP |
438 | data->resume = 0; |
439 | } else { | |
2d06d8c4 | 440 | pr_debug("Already at target state (P%d)\n", |
64be7eed | 441 | next_perf_state); |
4d8bb537 | 442 | goto out; |
fe27cb35 | 443 | } |
09b4d1ee VP |
444 | } |
445 | ||
64be7eed VP |
446 | switch (data->cpu_feature) { |
447 | case SYSTEM_INTEL_MSR_CAPABLE: | |
448 | cmd.type = SYSTEM_INTEL_MSR_CAPABLE; | |
449 | cmd.addr.msr.reg = MSR_IA32_PERF_CTL; | |
13424f65 | 450 | cmd.val = (u32) perf->states[next_perf_state].control; |
64be7eed | 451 | break; |
3dc9a633 MG |
452 | case SYSTEM_AMD_MSR_CAPABLE: |
453 | cmd.type = SYSTEM_AMD_MSR_CAPABLE; | |
454 | cmd.addr.msr.reg = MSR_AMD_PERF_CTL; | |
455 | cmd.val = (u32) perf->states[next_perf_state].control; | |
456 | break; | |
64be7eed VP |
457 | case SYSTEM_IO_CAPABLE: |
458 | cmd.type = SYSTEM_IO_CAPABLE; | |
459 | cmd.addr.io.port = perf->control_register.address; | |
460 | cmd.addr.io.bit_width = perf->control_register.bit_width; | |
461 | cmd.val = (u32) perf->states[next_perf_state].control; | |
462 | break; | |
463 | default: | |
4d8bb537 MT |
464 | result = -ENODEV; |
465 | goto out; | |
64be7eed | 466 | } |
09b4d1ee | 467 | |
4d8bb537 | 468 | /* cpufreq holds the hotplug lock, so we are safe from here on */ |
fe27cb35 | 469 | if (policy->shared_type != CPUFREQ_SHARED_TYPE_ANY) |
bfa318ad | 470 | cmd.mask = policy->cpus; |
fe27cb35 | 471 | else |
bfa318ad | 472 | cmd.mask = cpumask_of(policy->cpu); |
09b4d1ee | 473 | |
fe27cb35 | 474 | drv_write(&cmd); |
09b4d1ee | 475 | |
fe27cb35 | 476 | if (acpi_pstate_strict) { |
d4019f0a VK |
477 | if (!check_freqs(cmd.mask, data->freq_table[index].frequency, |
478 | data)) { | |
2d06d8c4 | 479 | pr_debug("acpi_cpufreq_target failed (%d)\n", |
64be7eed | 480 | policy->cpu); |
4d8bb537 | 481 | result = -EAGAIN; |
09b4d1ee VP |
482 | } |
483 | } | |
484 | ||
e15d8309 VK |
485 | if (!result) |
486 | perf->state = next_perf_state; | |
fe27cb35 | 487 | |
4d8bb537 | 488 | out: |
fe27cb35 | 489 | return result; |
1da177e4 LT |
490 | } |
491 | ||
1da177e4 | 492 | static unsigned long |
64be7eed | 493 | acpi_cpufreq_guess_freq(struct acpi_cpufreq_data *data, unsigned int cpu) |
1da177e4 | 494 | { |
3427616b | 495 | struct acpi_processor_performance *perf; |
09b4d1ee | 496 | |
3427616b | 497 | perf = to_perf_data(data); |
1da177e4 LT |
498 | if (cpu_khz) { |
499 | /* search the closest match to cpu_khz */ | |
500 | unsigned int i; | |
501 | unsigned long freq; | |
09b4d1ee | 502 | unsigned long freqn = perf->states[0].core_frequency * 1000; |
1da177e4 | 503 | |
3a58df35 | 504 | for (i = 0; i < (perf->state_count-1); i++) { |
1da177e4 | 505 | freq = freqn; |
95dd7227 | 506 | freqn = perf->states[i+1].core_frequency * 1000; |
1da177e4 | 507 | if ((2 * cpu_khz) > (freqn + freq)) { |
09b4d1ee | 508 | perf->state = i; |
64be7eed | 509 | return freq; |
1da177e4 LT |
510 | } |
511 | } | |
95dd7227 | 512 | perf->state = perf->state_count-1; |
64be7eed | 513 | return freqn; |
09b4d1ee | 514 | } else { |
1da177e4 | 515 | /* assume CPU is at P0... */ |
09b4d1ee VP |
516 | perf->state = 0; |
517 | return perf->states[0].core_frequency * 1000; | |
518 | } | |
1da177e4 LT |
519 | } |
520 | ||
2fdf66b4 RR |
521 | static void free_acpi_perf_data(void) |
522 | { | |
523 | unsigned int i; | |
524 | ||
525 | /* Freeing a NULL pointer is OK, and alloc_percpu zeroes. */ | |
526 | for_each_possible_cpu(i) | |
527 | free_cpumask_var(per_cpu_ptr(acpi_perf_data, i) | |
528 | ->shared_cpu_map); | |
529 | free_percpu(acpi_perf_data); | |
530 | } | |
531 | ||
615b7300 AP |
532 | static int boost_notify(struct notifier_block *nb, unsigned long action, |
533 | void *hcpu) | |
534 | { | |
535 | unsigned cpu = (long)hcpu; | |
536 | const struct cpumask *cpumask; | |
537 | ||
538 | cpumask = get_cpu_mask(cpu); | |
539 | ||
540 | /* | |
541 | * Clear the boost-disable bit on the CPU_DOWN path so that | |
542 | * this cpu cannot block the remaining ones from boosting. On | |
543 | * the CPU_UP path we simply keep the boost-disable flag in | |
544 | * sync with the current global state. | |
545 | */ | |
546 | ||
547 | switch (action) { | |
548 | case CPU_UP_PREPARE: | |
549 | case CPU_UP_PREPARE_FROZEN: | |
cfc9c8ed | 550 | boost_set_msrs(acpi_cpufreq_driver.boost_enabled, cpumask); |
615b7300 AP |
551 | break; |
552 | ||
553 | case CPU_DOWN_PREPARE: | |
554 | case CPU_DOWN_PREPARE_FROZEN: | |
555 | boost_set_msrs(1, cpumask); | |
556 | break; | |
557 | ||
558 | default: | |
559 | break; | |
560 | } | |
561 | ||
562 | return NOTIFY_OK; | |
563 | } | |
564 | ||
565 | ||
566 | static struct notifier_block boost_nb = { | |
567 | .notifier_call = boost_notify, | |
568 | }; | |
569 | ||
09b4d1ee VP |
570 | /* |
571 | * acpi_cpufreq_early_init - initialize ACPI P-States library | |
572 | * | |
573 | * Initialize the ACPI P-States library (drivers/acpi/processor_perflib.c) | |
574 | * in order to determine correct frequency and voltage pairings. We can | |
575 | * do _PDC and _PSD and find out the processor dependency for the | |
576 | * actual init that will happen later... | |
577 | */ | |
50109292 | 578 | static int __init acpi_cpufreq_early_init(void) |
09b4d1ee | 579 | { |
2fdf66b4 | 580 | unsigned int i; |
2d06d8c4 | 581 | pr_debug("acpi_cpufreq_early_init\n"); |
09b4d1ee | 582 | |
50109292 FY |
583 | acpi_perf_data = alloc_percpu(struct acpi_processor_performance); |
584 | if (!acpi_perf_data) { | |
2d06d8c4 | 585 | pr_debug("Memory allocation error for acpi_perf_data.\n"); |
50109292 | 586 | return -ENOMEM; |
09b4d1ee | 587 | } |
2fdf66b4 | 588 | for_each_possible_cpu(i) { |
eaa95840 | 589 | if (!zalloc_cpumask_var_node( |
80855f73 MT |
590 | &per_cpu_ptr(acpi_perf_data, i)->shared_cpu_map, |
591 | GFP_KERNEL, cpu_to_node(i))) { | |
2fdf66b4 RR |
592 | |
593 | /* Freeing a NULL pointer is OK: alloc_percpu zeroes. */ | |
594 | free_acpi_perf_data(); | |
595 | return -ENOMEM; | |
596 | } | |
597 | } | |
09b4d1ee VP |
598 | |
599 | /* Do initialization in ACPI core */ | |
fe27cb35 VP |
600 | acpi_processor_preregister_performance(acpi_perf_data); |
601 | return 0; | |
09b4d1ee VP |
602 | } |
603 | ||
95625b8f | 604 | #ifdef CONFIG_SMP |
8adcc0c6 VP |
605 | /* |
606 | * Some BIOSes do SW_ANY coordination internally, either set it up in hw | |
607 | * or do it in BIOS firmware and won't inform about it to OS. If not | |
608 | * detected, this has a side effect of making CPU run at a different speed | |
609 | * than OS intended it to run at. Detect it and handle it cleanly. | |
610 | */ | |
611 | static int bios_with_sw_any_bug; | |
612 | ||
1855256c | 613 | static int sw_any_bug_found(const struct dmi_system_id *d) |
8adcc0c6 VP |
614 | { |
615 | bios_with_sw_any_bug = 1; | |
616 | return 0; | |
617 | } | |
618 | ||
1855256c | 619 | static const struct dmi_system_id sw_any_bug_dmi_table[] = { |
8adcc0c6 VP |
620 | { |
621 | .callback = sw_any_bug_found, | |
622 | .ident = "Supermicro Server X6DLP", | |
623 | .matches = { | |
624 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
625 | DMI_MATCH(DMI_BIOS_VERSION, "080010"), | |
626 | DMI_MATCH(DMI_PRODUCT_NAME, "X6DLP"), | |
627 | }, | |
628 | }, | |
629 | { } | |
630 | }; | |
1a8e42fa PB |
631 | |
632 | static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c) | |
633 | { | |
293afe44 JV |
634 | /* Intel Xeon Processor 7100 Series Specification Update |
635 | * http://www.intel.com/Assets/PDF/specupdate/314554.pdf | |
1a8e42fa PB |
636 | * AL30: A Machine Check Exception (MCE) Occurring during an |
637 | * Enhanced Intel SpeedStep Technology Ratio Change May Cause | |
293afe44 | 638 | * Both Processor Cores to Lock Up. */ |
1a8e42fa PB |
639 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
640 | if ((c->x86 == 15) && | |
641 | (c->x86_model == 6) && | |
293afe44 JV |
642 | (c->x86_mask == 8)) { |
643 | printk(KERN_INFO "acpi-cpufreq: Intel(R) " | |
644 | "Xeon(R) 7100 Errata AL30, processors may " | |
645 | "lock up on frequency changes: disabling " | |
646 | "acpi-cpufreq.\n"); | |
1a8e42fa | 647 | return -ENODEV; |
293afe44 | 648 | } |
1a8e42fa PB |
649 | } |
650 | return 0; | |
651 | } | |
95625b8f | 652 | #endif |
8adcc0c6 | 653 | |
64be7eed | 654 | static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) |
1da177e4 | 655 | { |
64be7eed VP |
656 | unsigned int i; |
657 | unsigned int valid_states = 0; | |
658 | unsigned int cpu = policy->cpu; | |
659 | struct acpi_cpufreq_data *data; | |
64be7eed | 660 | unsigned int result = 0; |
92cb7612 | 661 | struct cpuinfo_x86 *c = &cpu_data(policy->cpu); |
64be7eed | 662 | struct acpi_processor_performance *perf; |
293afe44 JV |
663 | #ifdef CONFIG_SMP |
664 | static int blacklisted; | |
665 | #endif | |
1da177e4 | 666 | |
2d06d8c4 | 667 | pr_debug("acpi_cpufreq_cpu_init\n"); |
1da177e4 | 668 | |
1a8e42fa | 669 | #ifdef CONFIG_SMP |
293afe44 JV |
670 | if (blacklisted) |
671 | return blacklisted; | |
672 | blacklisted = acpi_cpufreq_blacklist(c); | |
673 | if (blacklisted) | |
674 | return blacklisted; | |
1a8e42fa PB |
675 | #endif |
676 | ||
d5b73cd8 | 677 | data = kzalloc(sizeof(*data), GFP_KERNEL); |
1da177e4 | 678 | if (!data) |
64be7eed | 679 | return -ENOMEM; |
1da177e4 | 680 | |
f4fd3797 LT |
681 | if (!zalloc_cpumask_var(&data->freqdomain_cpus, GFP_KERNEL)) { |
682 | result = -ENOMEM; | |
683 | goto err_free; | |
684 | } | |
685 | ||
3427616b | 686 | perf = per_cpu_ptr(acpi_perf_data, cpu); |
8cfcfd39 | 687 | data->acpi_perf_cpu = cpu; |
eb0b3e78 | 688 | policy->driver_data = data; |
1da177e4 | 689 | |
95dd7227 | 690 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) |
fe27cb35 | 691 | acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS; |
1da177e4 | 692 | |
3427616b | 693 | result = acpi_processor_register_performance(perf, cpu); |
1da177e4 | 694 | if (result) |
f4fd3797 | 695 | goto err_free_mask; |
1da177e4 | 696 | |
09b4d1ee | 697 | policy->shared_type = perf->shared_type; |
95dd7227 | 698 | |
46f18e3a | 699 | /* |
95dd7227 | 700 | * Will let policy->cpus know about dependency only when software |
46f18e3a VP |
701 | * coordination is required. |
702 | */ | |
703 | if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL || | |
8adcc0c6 | 704 | policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) { |
835481d9 | 705 | cpumask_copy(policy->cpus, perf->shared_cpu_map); |
8adcc0c6 | 706 | } |
f4fd3797 | 707 | cpumask_copy(data->freqdomain_cpus, perf->shared_cpu_map); |
8adcc0c6 VP |
708 | |
709 | #ifdef CONFIG_SMP | |
710 | dmi_check_system(sw_any_bug_dmi_table); | |
2624f90c | 711 | if (bios_with_sw_any_bug && !policy_is_shared(policy)) { |
8adcc0c6 | 712 | policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; |
3280c3c8 | 713 | cpumask_copy(policy->cpus, topology_core_cpumask(cpu)); |
8adcc0c6 | 714 | } |
acd31624 AP |
715 | |
716 | if (check_amd_hwpstate_cpu(cpu) && !acpi_pstate_strict) { | |
717 | cpumask_clear(policy->cpus); | |
718 | cpumask_set_cpu(cpu, policy->cpus); | |
3280c3c8 BG |
719 | cpumask_copy(data->freqdomain_cpus, |
720 | topology_sibling_cpumask(cpu)); | |
acd31624 AP |
721 | policy->shared_type = CPUFREQ_SHARED_TYPE_HW; |
722 | pr_info_once(PFX "overriding BIOS provided _PSD data\n"); | |
723 | } | |
8adcc0c6 | 724 | #endif |
09b4d1ee | 725 | |
1da177e4 | 726 | /* capability check */ |
09b4d1ee | 727 | if (perf->state_count <= 1) { |
2d06d8c4 | 728 | pr_debug("No P-States\n"); |
1da177e4 LT |
729 | result = -ENODEV; |
730 | goto err_unreg; | |
731 | } | |
09b4d1ee | 732 | |
fe27cb35 VP |
733 | if (perf->control_register.space_id != perf->status_register.space_id) { |
734 | result = -ENODEV; | |
735 | goto err_unreg; | |
736 | } | |
737 | ||
738 | switch (perf->control_register.space_id) { | |
64be7eed | 739 | case ACPI_ADR_SPACE_SYSTEM_IO: |
c40a4518 MG |
740 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && |
741 | boot_cpu_data.x86 == 0xf) { | |
742 | pr_debug("AMD K8 systems must use native drivers.\n"); | |
743 | result = -ENODEV; | |
744 | goto err_unreg; | |
745 | } | |
2d06d8c4 | 746 | pr_debug("SYSTEM IO addr space\n"); |
dde9f7ba VP |
747 | data->cpu_feature = SYSTEM_IO_CAPABLE; |
748 | break; | |
64be7eed | 749 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
2d06d8c4 | 750 | pr_debug("HARDWARE addr space\n"); |
3dc9a633 MG |
751 | if (check_est_cpu(cpu)) { |
752 | data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE; | |
753 | break; | |
dde9f7ba | 754 | } |
3dc9a633 MG |
755 | if (check_amd_hwpstate_cpu(cpu)) { |
756 | data->cpu_feature = SYSTEM_AMD_MSR_CAPABLE; | |
757 | break; | |
758 | } | |
759 | result = -ENODEV; | |
760 | goto err_unreg; | |
64be7eed | 761 | default: |
2d06d8c4 | 762 | pr_debug("Unknown addr space %d\n", |
64be7eed | 763 | (u32) (perf->control_register.space_id)); |
1da177e4 LT |
764 | result = -ENODEV; |
765 | goto err_unreg; | |
766 | } | |
767 | ||
71508a1f | 768 | data->freq_table = kzalloc(sizeof(*data->freq_table) * |
95dd7227 | 769 | (perf->state_count+1), GFP_KERNEL); |
1da177e4 LT |
770 | if (!data->freq_table) { |
771 | result = -ENOMEM; | |
772 | goto err_unreg; | |
773 | } | |
774 | ||
775 | /* detect transition latency */ | |
776 | policy->cpuinfo.transition_latency = 0; | |
3a58df35 | 777 | for (i = 0; i < perf->state_count; i++) { |
64be7eed VP |
778 | if ((perf->states[i].transition_latency * 1000) > |
779 | policy->cpuinfo.transition_latency) | |
780 | policy->cpuinfo.transition_latency = | |
781 | perf->states[i].transition_latency * 1000; | |
1da177e4 | 782 | } |
1da177e4 | 783 | |
a59d1637 PV |
784 | /* Check for high latency (>20uS) from buggy BIOSes, like on T42 */ |
785 | if (perf->control_register.space_id == ACPI_ADR_SPACE_FIXED_HARDWARE && | |
786 | policy->cpuinfo.transition_latency > 20 * 1000) { | |
a59d1637 | 787 | policy->cpuinfo.transition_latency = 20 * 1000; |
61c8c67e JP |
788 | printk_once(KERN_INFO |
789 | "P-state transition latency capped at 20 uS\n"); | |
a59d1637 PV |
790 | } |
791 | ||
1da177e4 | 792 | /* table init */ |
3a58df35 DJ |
793 | for (i = 0; i < perf->state_count; i++) { |
794 | if (i > 0 && perf->states[i].core_frequency >= | |
3cdf552b | 795 | data->freq_table[valid_states-1].frequency / 1000) |
fe27cb35 VP |
796 | continue; |
797 | ||
50701588 | 798 | data->freq_table[valid_states].driver_data = i; |
fe27cb35 | 799 | data->freq_table[valid_states].frequency = |
64be7eed | 800 | perf->states[i].core_frequency * 1000; |
fe27cb35 | 801 | valid_states++; |
1da177e4 | 802 | } |
3d4a7ef3 | 803 | data->freq_table[valid_states].frequency = CPUFREQ_TABLE_END; |
8edc59d9 | 804 | perf->state = 0; |
1da177e4 | 805 | |
776b57be | 806 | result = cpufreq_table_validate_and_show(policy, data->freq_table); |
95dd7227 | 807 | if (result) |
1da177e4 | 808 | goto err_freqfree; |
1da177e4 | 809 | |
d876dfbb TR |
810 | if (perf->states[0].core_frequency * 1000 != policy->cpuinfo.max_freq) |
811 | printk(KERN_WARNING FW_WARN "P-state 0 is not max freq\n"); | |
812 | ||
a507ac4b | 813 | switch (perf->control_register.space_id) { |
64be7eed | 814 | case ACPI_ADR_SPACE_SYSTEM_IO: |
1bab64d5 VK |
815 | /* |
816 | * The core will not set policy->cur, because | |
817 | * cpufreq_driver->get is NULL, so we need to set it here. | |
818 | * However, we have to guess it, because the current speed is | |
819 | * unknown and not detectable via IO ports. | |
820 | */ | |
dde9f7ba VP |
821 | policy->cur = acpi_cpufreq_guess_freq(data, policy->cpu); |
822 | break; | |
64be7eed | 823 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
7650b281 | 824 | acpi_cpufreq_driver.get = get_cur_freq_on_cpu; |
dde9f7ba | 825 | break; |
64be7eed | 826 | default: |
dde9f7ba VP |
827 | break; |
828 | } | |
829 | ||
1da177e4 LT |
830 | /* notify BIOS that we exist */ |
831 | acpi_processor_notify_smm(THIS_MODULE); | |
832 | ||
2d06d8c4 | 833 | pr_debug("CPU%u - ACPI performance management activated.\n", cpu); |
09b4d1ee | 834 | for (i = 0; i < perf->state_count; i++) |
2d06d8c4 | 835 | pr_debug(" %cP%d: %d MHz, %d mW, %d uS\n", |
64be7eed | 836 | (i == perf->state ? '*' : ' '), i, |
09b4d1ee VP |
837 | (u32) perf->states[i].core_frequency, |
838 | (u32) perf->states[i].power, | |
839 | (u32) perf->states[i].transition_latency); | |
1da177e4 | 840 | |
4b31e774 DB |
841 | /* |
842 | * the first call to ->target() should result in us actually | |
843 | * writing something to the appropriate registers. | |
844 | */ | |
845 | data->resume = 1; | |
64be7eed | 846 | |
fe27cb35 | 847 | return result; |
1da177e4 | 848 | |
95dd7227 | 849 | err_freqfree: |
1da177e4 | 850 | kfree(data->freq_table); |
95dd7227 | 851 | err_unreg: |
b2f8dc4c | 852 | acpi_processor_unregister_performance(cpu); |
f4fd3797 LT |
853 | err_free_mask: |
854 | free_cpumask_var(data->freqdomain_cpus); | |
95dd7227 | 855 | err_free: |
1da177e4 | 856 | kfree(data); |
eb0b3e78 | 857 | policy->driver_data = NULL; |
1da177e4 | 858 | |
64be7eed | 859 | return result; |
1da177e4 LT |
860 | } |
861 | ||
64be7eed | 862 | static int acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy) |
1da177e4 | 863 | { |
eb0b3e78 | 864 | struct acpi_cpufreq_data *data = policy->driver_data; |
1da177e4 | 865 | |
2d06d8c4 | 866 | pr_debug("acpi_cpufreq_cpu_exit\n"); |
1da177e4 LT |
867 | |
868 | if (data) { | |
eb0b3e78 | 869 | policy->driver_data = NULL; |
b2f8dc4c | 870 | acpi_processor_unregister_performance(data->acpi_perf_cpu); |
f4fd3797 | 871 | free_cpumask_var(data->freqdomain_cpus); |
dab5fff1 | 872 | kfree(data->freq_table); |
1da177e4 LT |
873 | kfree(data); |
874 | } | |
875 | ||
64be7eed | 876 | return 0; |
1da177e4 LT |
877 | } |
878 | ||
64be7eed | 879 | static int acpi_cpufreq_resume(struct cpufreq_policy *policy) |
1da177e4 | 880 | { |
eb0b3e78 | 881 | struct acpi_cpufreq_data *data = policy->driver_data; |
1da177e4 | 882 | |
2d06d8c4 | 883 | pr_debug("acpi_cpufreq_resume\n"); |
1da177e4 LT |
884 | |
885 | data->resume = 1; | |
886 | ||
64be7eed | 887 | return 0; |
1da177e4 LT |
888 | } |
889 | ||
64be7eed | 890 | static struct freq_attr *acpi_cpufreq_attr[] = { |
1da177e4 | 891 | &cpufreq_freq_attr_scaling_available_freqs, |
f4fd3797 | 892 | &freqdomain_cpus, |
f56c50e3 RW |
893 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
894 | &cpb, | |
895 | #endif | |
1da177e4 LT |
896 | NULL, |
897 | }; | |
898 | ||
899 | static struct cpufreq_driver acpi_cpufreq_driver = { | |
db9be219 | 900 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 901 | .target_index = acpi_cpufreq_target, |
e2f74f35 TR |
902 | .bios_limit = acpi_processor_get_bios_limit, |
903 | .init = acpi_cpufreq_cpu_init, | |
904 | .exit = acpi_cpufreq_cpu_exit, | |
905 | .resume = acpi_cpufreq_resume, | |
906 | .name = "acpi-cpufreq", | |
e2f74f35 | 907 | .attr = acpi_cpufreq_attr, |
cfc9c8ed | 908 | .set_boost = _store_boost, |
1da177e4 LT |
909 | }; |
910 | ||
615b7300 AP |
911 | static void __init acpi_cpufreq_boost_init(void) |
912 | { | |
913 | if (boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA)) { | |
914 | msrs = msrs_alloc(); | |
915 | ||
916 | if (!msrs) | |
917 | return; | |
918 | ||
cfc9c8ed LM |
919 | acpi_cpufreq_driver.boost_supported = true; |
920 | acpi_cpufreq_driver.boost_enabled = boost_state(0); | |
0197fbd2 SB |
921 | |
922 | cpu_notifier_register_begin(); | |
615b7300 AP |
923 | |
924 | /* Force all MSRs to the same value */ | |
cfc9c8ed LM |
925 | boost_set_msrs(acpi_cpufreq_driver.boost_enabled, |
926 | cpu_online_mask); | |
615b7300 | 927 | |
0197fbd2 | 928 | __register_cpu_notifier(&boost_nb); |
615b7300 | 929 | |
0197fbd2 | 930 | cpu_notifier_register_done(); |
cfc9c8ed | 931 | } |
615b7300 AP |
932 | } |
933 | ||
eb8c68ef | 934 | static void acpi_cpufreq_boost_exit(void) |
615b7300 | 935 | { |
615b7300 AP |
936 | if (msrs) { |
937 | unregister_cpu_notifier(&boost_nb); | |
938 | ||
939 | msrs_free(msrs); | |
940 | msrs = NULL; | |
941 | } | |
942 | } | |
943 | ||
64be7eed | 944 | static int __init acpi_cpufreq_init(void) |
1da177e4 | 945 | { |
50109292 FY |
946 | int ret; |
947 | ||
75c07581 RW |
948 | if (acpi_disabled) |
949 | return -ENODEV; | |
950 | ||
8a61e12e YL |
951 | /* don't keep reloading if cpufreq_driver exists */ |
952 | if (cpufreq_get_current_driver()) | |
75c07581 | 953 | return -EEXIST; |
ee297533 | 954 | |
2d06d8c4 | 955 | pr_debug("acpi_cpufreq_init\n"); |
1da177e4 | 956 | |
50109292 FY |
957 | ret = acpi_cpufreq_early_init(); |
958 | if (ret) | |
959 | return ret; | |
09b4d1ee | 960 | |
11269ff5 AP |
961 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
962 | /* this is a sysfs file with a strange name and an even stranger | |
963 | * semantic - per CPU instantiation, but system global effect. | |
964 | * Lets enable it only on AMD CPUs for compatibility reasons and | |
965 | * only if configured. This is considered legacy code, which | |
966 | * will probably be removed at some point in the future. | |
967 | */ | |
f56c50e3 RW |
968 | if (!check_amd_hwpstate_cpu(0)) { |
969 | struct freq_attr **attr; | |
11269ff5 | 970 | |
f56c50e3 | 971 | pr_debug("CPB unsupported, do not expose it\n"); |
11269ff5 | 972 | |
f56c50e3 RW |
973 | for (attr = acpi_cpufreq_attr; *attr; attr++) |
974 | if (*attr == &cpb) { | |
975 | *attr = NULL; | |
976 | break; | |
977 | } | |
11269ff5 AP |
978 | } |
979 | #endif | |
cfc9c8ed | 980 | acpi_cpufreq_boost_init(); |
11269ff5 | 981 | |
847aef6f | 982 | ret = cpufreq_register_driver(&acpi_cpufreq_driver); |
eb8c68ef | 983 | if (ret) { |
2fdf66b4 | 984 | free_acpi_perf_data(); |
eb8c68ef KRW |
985 | acpi_cpufreq_boost_exit(); |
986 | } | |
847aef6f | 987 | return ret; |
1da177e4 LT |
988 | } |
989 | ||
64be7eed | 990 | static void __exit acpi_cpufreq_exit(void) |
1da177e4 | 991 | { |
2d06d8c4 | 992 | pr_debug("acpi_cpufreq_exit\n"); |
1da177e4 | 993 | |
615b7300 AP |
994 | acpi_cpufreq_boost_exit(); |
995 | ||
1da177e4 LT |
996 | cpufreq_unregister_driver(&acpi_cpufreq_driver); |
997 | ||
50f4ddd4 | 998 | free_acpi_perf_data(); |
1da177e4 LT |
999 | } |
1000 | ||
d395bf12 | 1001 | module_param(acpi_pstate_strict, uint, 0644); |
64be7eed | 1002 | MODULE_PARM_DESC(acpi_pstate_strict, |
95dd7227 DJ |
1003 | "value 0 or non-zero. non-zero -> strict ACPI checks are " |
1004 | "performed during frequency changes."); | |
1da177e4 LT |
1005 | |
1006 | late_initcall(acpi_cpufreq_init); | |
1007 | module_exit(acpi_cpufreq_exit); | |
1008 | ||
efa17194 MG |
1009 | static const struct x86_cpu_id acpi_cpufreq_ids[] = { |
1010 | X86_FEATURE_MATCH(X86_FEATURE_ACPI), | |
1011 | X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE), | |
1012 | {} | |
1013 | }; | |
1014 | MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); | |
1015 | ||
c655affb RW |
1016 | static const struct acpi_device_id processor_device_ids[] = { |
1017 | {ACPI_PROCESSOR_OBJECT_HID, }, | |
1018 | {ACPI_PROCESSOR_DEVICE_HID, }, | |
1019 | {}, | |
1020 | }; | |
1021 | MODULE_DEVICE_TABLE(acpi, processor_device_ids); | |
1022 | ||
1da177e4 | 1023 | MODULE_ALIAS("acpi"); |