Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
3a58df35 | 2 | * acpi-cpufreq.c - ACPI Processor P-States Driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
6 | * Copyright (C) 2002 - 2004 Dominik Brodowski <linux@brodo.de> | |
fe27cb35 | 7 | * Copyright (C) 2006 Denis Sadykov <denis.m.sadykov@intel.com> |
1da177e4 LT |
8 | * |
9 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License along | |
22 | * with this program; if not, write to the Free Software Foundation, Inc., | |
23 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
24 | * | |
25 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
26 | */ | |
27 | ||
1da177e4 LT |
28 | #include <linux/kernel.h> |
29 | #include <linux/module.h> | |
30 | #include <linux/init.h> | |
fe27cb35 VP |
31 | #include <linux/smp.h> |
32 | #include <linux/sched.h> | |
1da177e4 | 33 | #include <linux/cpufreq.h> |
d395bf12 | 34 | #include <linux/compiler.h> |
8adcc0c6 | 35 | #include <linux/dmi.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
1da177e4 LT |
37 | |
38 | #include <linux/acpi.h> | |
3a58df35 DJ |
39 | #include <linux/io.h> |
40 | #include <linux/delay.h> | |
41 | #include <linux/uaccess.h> | |
42 | ||
1da177e4 LT |
43 | #include <acpi/processor.h> |
44 | ||
dde9f7ba | 45 | #include <asm/msr.h> |
fe27cb35 VP |
46 | #include <asm/processor.h> |
47 | #include <asm/cpufeature.h> | |
fe27cb35 | 48 | |
1da177e4 LT |
49 | MODULE_AUTHOR("Paul Diefenbaugh, Dominik Brodowski"); |
50 | MODULE_DESCRIPTION("ACPI Processor P-States Driver"); | |
51 | MODULE_LICENSE("GPL"); | |
52 | ||
acd31624 AP |
53 | #define PFX "acpi-cpufreq: " |
54 | ||
dde9f7ba VP |
55 | enum { |
56 | UNDEFINED_CAPABLE = 0, | |
57 | SYSTEM_INTEL_MSR_CAPABLE, | |
3dc9a633 | 58 | SYSTEM_AMD_MSR_CAPABLE, |
dde9f7ba VP |
59 | SYSTEM_IO_CAPABLE, |
60 | }; | |
61 | ||
62 | #define INTEL_MSR_RANGE (0xffff) | |
3dc9a633 | 63 | #define AMD_MSR_RANGE (0x7) |
dde9f7ba | 64 | |
615b7300 AP |
65 | #define MSR_K7_HWCR_CPB_DIS (1ULL << 25) |
66 | ||
fe27cb35 | 67 | struct acpi_cpufreq_data { |
64be7eed VP |
68 | struct acpi_processor_performance *acpi_data; |
69 | struct cpufreq_frequency_table *freq_table; | |
70 | unsigned int resume; | |
71 | unsigned int cpu_feature; | |
f4fd3797 | 72 | cpumask_var_t freqdomain_cpus; |
1da177e4 LT |
73 | }; |
74 | ||
f1625066 | 75 | static DEFINE_PER_CPU(struct acpi_cpufreq_data *, acfreq_data); |
ea348f3e | 76 | |
50109292 | 77 | /* acpi_perf_data is a pointer to percpu data. */ |
3f6c4df7 | 78 | static struct acpi_processor_performance __percpu *acpi_perf_data; |
1da177e4 LT |
79 | |
80 | static struct cpufreq_driver acpi_cpufreq_driver; | |
81 | ||
d395bf12 | 82 | static unsigned int acpi_pstate_strict; |
615b7300 AP |
83 | static bool boost_enabled, boost_supported; |
84 | static struct msr __percpu *msrs; | |
85 | ||
86 | static bool boost_state(unsigned int cpu) | |
87 | { | |
88 | u32 lo, hi; | |
89 | u64 msr; | |
90 | ||
91 | switch (boot_cpu_data.x86_vendor) { | |
92 | case X86_VENDOR_INTEL: | |
93 | rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi); | |
94 | msr = lo | ((u64)hi << 32); | |
95 | return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); | |
96 | case X86_VENDOR_AMD: | |
97 | rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); | |
98 | msr = lo | ((u64)hi << 32); | |
99 | return !(msr & MSR_K7_HWCR_CPB_DIS); | |
100 | } | |
101 | return false; | |
102 | } | |
103 | ||
104 | static void boost_set_msrs(bool enable, const struct cpumask *cpumask) | |
105 | { | |
106 | u32 cpu; | |
107 | u32 msr_addr; | |
108 | u64 msr_mask; | |
109 | ||
110 | switch (boot_cpu_data.x86_vendor) { | |
111 | case X86_VENDOR_INTEL: | |
112 | msr_addr = MSR_IA32_MISC_ENABLE; | |
113 | msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE; | |
114 | break; | |
115 | case X86_VENDOR_AMD: | |
116 | msr_addr = MSR_K7_HWCR; | |
117 | msr_mask = MSR_K7_HWCR_CPB_DIS; | |
118 | break; | |
119 | default: | |
120 | return; | |
121 | } | |
122 | ||
123 | rdmsr_on_cpus(cpumask, msr_addr, msrs); | |
124 | ||
125 | for_each_cpu(cpu, cpumask) { | |
126 | struct msr *reg = per_cpu_ptr(msrs, cpu); | |
127 | if (enable) | |
128 | reg->q &= ~msr_mask; | |
129 | else | |
130 | reg->q |= msr_mask; | |
131 | } | |
132 | ||
133 | wrmsr_on_cpus(cpumask, msr_addr, msrs); | |
134 | } | |
135 | ||
11269ff5 | 136 | static ssize_t _store_boost(const char *buf, size_t count) |
615b7300 AP |
137 | { |
138 | int ret; | |
139 | unsigned long val = 0; | |
140 | ||
141 | if (!boost_supported) | |
142 | return -EINVAL; | |
143 | ||
144 | ret = kstrtoul(buf, 10, &val); | |
145 | if (ret || (val > 1)) | |
146 | return -EINVAL; | |
147 | ||
148 | if ((val && boost_enabled) || (!val && !boost_enabled)) | |
149 | return count; | |
150 | ||
151 | get_online_cpus(); | |
152 | ||
153 | boost_set_msrs(val, cpu_online_mask); | |
154 | ||
155 | put_online_cpus(); | |
156 | ||
157 | boost_enabled = val; | |
158 | pr_debug("Core Boosting %sabled.\n", val ? "en" : "dis"); | |
159 | ||
160 | return count; | |
161 | } | |
162 | ||
11269ff5 AP |
163 | static ssize_t store_global_boost(struct kobject *kobj, struct attribute *attr, |
164 | const char *buf, size_t count) | |
165 | { | |
166 | return _store_boost(buf, count); | |
167 | } | |
168 | ||
615b7300 AP |
169 | static ssize_t show_global_boost(struct kobject *kobj, |
170 | struct attribute *attr, char *buf) | |
171 | { | |
172 | return sprintf(buf, "%u\n", boost_enabled); | |
173 | } | |
174 | ||
175 | static struct global_attr global_boost = __ATTR(boost, 0644, | |
176 | show_global_boost, | |
177 | store_global_boost); | |
d395bf12 | 178 | |
f4fd3797 LT |
179 | static ssize_t show_freqdomain_cpus(struct cpufreq_policy *policy, char *buf) |
180 | { | |
181 | struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu); | |
182 | ||
183 | return cpufreq_show_cpus(data->freqdomain_cpus, buf); | |
184 | } | |
185 | ||
186 | cpufreq_freq_attr_ro(freqdomain_cpus); | |
187 | ||
11269ff5 AP |
188 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
189 | static ssize_t store_cpb(struct cpufreq_policy *policy, const char *buf, | |
190 | size_t count) | |
191 | { | |
192 | return _store_boost(buf, count); | |
193 | } | |
194 | ||
195 | static ssize_t show_cpb(struct cpufreq_policy *policy, char *buf) | |
196 | { | |
197 | return sprintf(buf, "%u\n", boost_enabled); | |
198 | } | |
199 | ||
59027d35 | 200 | cpufreq_freq_attr_rw(cpb); |
11269ff5 AP |
201 | #endif |
202 | ||
dde9f7ba VP |
203 | static int check_est_cpu(unsigned int cpuid) |
204 | { | |
92cb7612 | 205 | struct cpuinfo_x86 *cpu = &cpu_data(cpuid); |
dde9f7ba | 206 | |
0de51088 | 207 | return cpu_has(cpu, X86_FEATURE_EST); |
dde9f7ba VP |
208 | } |
209 | ||
3dc9a633 MG |
210 | static int check_amd_hwpstate_cpu(unsigned int cpuid) |
211 | { | |
212 | struct cpuinfo_x86 *cpu = &cpu_data(cpuid); | |
213 | ||
214 | return cpu_has(cpu, X86_FEATURE_HW_PSTATE); | |
215 | } | |
216 | ||
dde9f7ba | 217 | static unsigned extract_io(u32 value, struct acpi_cpufreq_data *data) |
fe27cb35 | 218 | { |
64be7eed VP |
219 | struct acpi_processor_performance *perf; |
220 | int i; | |
fe27cb35 VP |
221 | |
222 | perf = data->acpi_data; | |
223 | ||
3a58df35 | 224 | for (i = 0; i < perf->state_count; i++) { |
fe27cb35 VP |
225 | if (value == perf->states[i].status) |
226 | return data->freq_table[i].frequency; | |
227 | } | |
228 | return 0; | |
229 | } | |
230 | ||
dde9f7ba VP |
231 | static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) |
232 | { | |
233 | int i; | |
a6f6e6e6 | 234 | struct acpi_processor_performance *perf; |
dde9f7ba | 235 | |
3dc9a633 MG |
236 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
237 | msr &= AMD_MSR_RANGE; | |
238 | else | |
239 | msr &= INTEL_MSR_RANGE; | |
240 | ||
a6f6e6e6 VP |
241 | perf = data->acpi_data; |
242 | ||
3a58df35 | 243 | for (i = 0; data->freq_table[i].frequency != CPUFREQ_TABLE_END; i++) { |
50701588 | 244 | if (msr == perf->states[data->freq_table[i].driver_data].status) |
dde9f7ba VP |
245 | return data->freq_table[i].frequency; |
246 | } | |
247 | return data->freq_table[0].frequency; | |
248 | } | |
249 | ||
dde9f7ba VP |
250 | static unsigned extract_freq(u32 val, struct acpi_cpufreq_data *data) |
251 | { | |
252 | switch (data->cpu_feature) { | |
64be7eed | 253 | case SYSTEM_INTEL_MSR_CAPABLE: |
3dc9a633 | 254 | case SYSTEM_AMD_MSR_CAPABLE: |
dde9f7ba | 255 | return extract_msr(val, data); |
64be7eed | 256 | case SYSTEM_IO_CAPABLE: |
dde9f7ba | 257 | return extract_io(val, data); |
64be7eed | 258 | default: |
dde9f7ba VP |
259 | return 0; |
260 | } | |
261 | } | |
262 | ||
dde9f7ba VP |
263 | struct msr_addr { |
264 | u32 reg; | |
265 | }; | |
266 | ||
fe27cb35 VP |
267 | struct io_addr { |
268 | u16 port; | |
269 | u8 bit_width; | |
270 | }; | |
271 | ||
272 | struct drv_cmd { | |
dde9f7ba | 273 | unsigned int type; |
bfa318ad | 274 | const struct cpumask *mask; |
3a58df35 DJ |
275 | union { |
276 | struct msr_addr msr; | |
277 | struct io_addr io; | |
278 | } addr; | |
fe27cb35 VP |
279 | u32 val; |
280 | }; | |
281 | ||
01599fca AM |
282 | /* Called via smp_call_function_single(), on the target CPU */ |
283 | static void do_drv_read(void *_cmd) | |
1da177e4 | 284 | { |
72859081 | 285 | struct drv_cmd *cmd = _cmd; |
dde9f7ba VP |
286 | u32 h; |
287 | ||
288 | switch (cmd->type) { | |
64be7eed | 289 | case SYSTEM_INTEL_MSR_CAPABLE: |
3dc9a633 | 290 | case SYSTEM_AMD_MSR_CAPABLE: |
dde9f7ba VP |
291 | rdmsr(cmd->addr.msr.reg, cmd->val, h); |
292 | break; | |
64be7eed | 293 | case SYSTEM_IO_CAPABLE: |
4e581ff1 VP |
294 | acpi_os_read_port((acpi_io_address)cmd->addr.io.port, |
295 | &cmd->val, | |
296 | (u32)cmd->addr.io.bit_width); | |
dde9f7ba | 297 | break; |
64be7eed | 298 | default: |
dde9f7ba VP |
299 | break; |
300 | } | |
fe27cb35 | 301 | } |
1da177e4 | 302 | |
01599fca AM |
303 | /* Called via smp_call_function_many(), on the target CPUs */ |
304 | static void do_drv_write(void *_cmd) | |
fe27cb35 | 305 | { |
72859081 | 306 | struct drv_cmd *cmd = _cmd; |
13424f65 | 307 | u32 lo, hi; |
dde9f7ba VP |
308 | |
309 | switch (cmd->type) { | |
64be7eed | 310 | case SYSTEM_INTEL_MSR_CAPABLE: |
13424f65 VP |
311 | rdmsr(cmd->addr.msr.reg, lo, hi); |
312 | lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE); | |
313 | wrmsr(cmd->addr.msr.reg, lo, hi); | |
dde9f7ba | 314 | break; |
3dc9a633 MG |
315 | case SYSTEM_AMD_MSR_CAPABLE: |
316 | wrmsr(cmd->addr.msr.reg, cmd->val, 0); | |
317 | break; | |
64be7eed | 318 | case SYSTEM_IO_CAPABLE: |
4e581ff1 VP |
319 | acpi_os_write_port((acpi_io_address)cmd->addr.io.port, |
320 | cmd->val, | |
321 | (u32)cmd->addr.io.bit_width); | |
dde9f7ba | 322 | break; |
64be7eed | 323 | default: |
dde9f7ba VP |
324 | break; |
325 | } | |
fe27cb35 | 326 | } |
1da177e4 | 327 | |
95dd7227 | 328 | static void drv_read(struct drv_cmd *cmd) |
fe27cb35 | 329 | { |
4a28395d | 330 | int err; |
fe27cb35 VP |
331 | cmd->val = 0; |
332 | ||
4a28395d AM |
333 | err = smp_call_function_any(cmd->mask, do_drv_read, cmd, 1); |
334 | WARN_ON_ONCE(err); /* smp_call_function_any() was buggy? */ | |
fe27cb35 VP |
335 | } |
336 | ||
337 | static void drv_write(struct drv_cmd *cmd) | |
338 | { | |
ea34f43a LT |
339 | int this_cpu; |
340 | ||
341 | this_cpu = get_cpu(); | |
342 | if (cpumask_test_cpu(this_cpu, cmd->mask)) | |
343 | do_drv_write(cmd); | |
01599fca | 344 | smp_call_function_many(cmd->mask, do_drv_write, cmd, 1); |
ea34f43a | 345 | put_cpu(); |
fe27cb35 | 346 | } |
1da177e4 | 347 | |
4d8bb537 | 348 | static u32 get_cur_val(const struct cpumask *mask) |
fe27cb35 | 349 | { |
64be7eed VP |
350 | struct acpi_processor_performance *perf; |
351 | struct drv_cmd cmd; | |
1da177e4 | 352 | |
4d8bb537 | 353 | if (unlikely(cpumask_empty(mask))) |
fe27cb35 | 354 | return 0; |
1da177e4 | 355 | |
f1625066 | 356 | switch (per_cpu(acfreq_data, cpumask_first(mask))->cpu_feature) { |
dde9f7ba VP |
357 | case SYSTEM_INTEL_MSR_CAPABLE: |
358 | cmd.type = SYSTEM_INTEL_MSR_CAPABLE; | |
8673b83b | 359 | cmd.addr.msr.reg = MSR_IA32_PERF_CTL; |
dde9f7ba | 360 | break; |
3dc9a633 MG |
361 | case SYSTEM_AMD_MSR_CAPABLE: |
362 | cmd.type = SYSTEM_AMD_MSR_CAPABLE; | |
8673b83b | 363 | cmd.addr.msr.reg = MSR_AMD_PERF_CTL; |
3dc9a633 | 364 | break; |
dde9f7ba VP |
365 | case SYSTEM_IO_CAPABLE: |
366 | cmd.type = SYSTEM_IO_CAPABLE; | |
f1625066 | 367 | perf = per_cpu(acfreq_data, cpumask_first(mask))->acpi_data; |
dde9f7ba VP |
368 | cmd.addr.io.port = perf->control_register.address; |
369 | cmd.addr.io.bit_width = perf->control_register.bit_width; | |
370 | break; | |
371 | default: | |
372 | return 0; | |
373 | } | |
374 | ||
bfa318ad | 375 | cmd.mask = mask; |
fe27cb35 | 376 | drv_read(&cmd); |
1da177e4 | 377 | |
2d06d8c4 | 378 | pr_debug("get_cur_val = %u\n", cmd.val); |
fe27cb35 VP |
379 | |
380 | return cmd.val; | |
381 | } | |
1da177e4 | 382 | |
fe27cb35 VP |
383 | static unsigned int get_cur_freq_on_cpu(unsigned int cpu) |
384 | { | |
f1625066 | 385 | struct acpi_cpufreq_data *data = per_cpu(acfreq_data, cpu); |
64be7eed | 386 | unsigned int freq; |
e56a727b | 387 | unsigned int cached_freq; |
fe27cb35 | 388 | |
2d06d8c4 | 389 | pr_debug("get_cur_freq_on_cpu (%d)\n", cpu); |
fe27cb35 VP |
390 | |
391 | if (unlikely(data == NULL || | |
64be7eed | 392 | data->acpi_data == NULL || data->freq_table == NULL)) { |
fe27cb35 | 393 | return 0; |
1da177e4 LT |
394 | } |
395 | ||
e56a727b | 396 | cached_freq = data->freq_table[data->acpi_data->state].frequency; |
e39ad415 | 397 | freq = extract_freq(get_cur_val(cpumask_of(cpu)), data); |
e56a727b VP |
398 | if (freq != cached_freq) { |
399 | /* | |
400 | * The dreaded BIOS frequency change behind our back. | |
401 | * Force set the frequency on next target call. | |
402 | */ | |
403 | data->resume = 1; | |
404 | } | |
405 | ||
2d06d8c4 | 406 | pr_debug("cur freq = %u\n", freq); |
1da177e4 | 407 | |
fe27cb35 | 408 | return freq; |
1da177e4 LT |
409 | } |
410 | ||
72859081 | 411 | static unsigned int check_freqs(const struct cpumask *mask, unsigned int freq, |
64be7eed | 412 | struct acpi_cpufreq_data *data) |
fe27cb35 | 413 | { |
64be7eed VP |
414 | unsigned int cur_freq; |
415 | unsigned int i; | |
1da177e4 | 416 | |
3a58df35 | 417 | for (i = 0; i < 100; i++) { |
fe27cb35 VP |
418 | cur_freq = extract_freq(get_cur_val(mask), data); |
419 | if (cur_freq == freq) | |
420 | return 1; | |
421 | udelay(10); | |
422 | } | |
423 | return 0; | |
424 | } | |
425 | ||
426 | static int acpi_cpufreq_target(struct cpufreq_policy *policy, | |
9c0ebcf7 | 427 | unsigned int index) |
1da177e4 | 428 | { |
f1625066 | 429 | struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu); |
64be7eed VP |
430 | struct acpi_processor_performance *perf; |
431 | struct cpufreq_freqs freqs; | |
64be7eed | 432 | struct drv_cmd cmd; |
8edc59d9 | 433 | unsigned int next_perf_state = 0; /* Index into perf table */ |
64be7eed | 434 | int result = 0; |
fe27cb35 | 435 | |
9c0ebcf7 VK |
436 | pr_debug("acpi_cpufreq_target %d (%d)\n", |
437 | data->freq_table[index].frequency, policy->cpu); | |
fe27cb35 VP |
438 | |
439 | if (unlikely(data == NULL || | |
95dd7227 | 440 | data->acpi_data == NULL || data->freq_table == NULL)) { |
fe27cb35 VP |
441 | return -ENODEV; |
442 | } | |
1da177e4 | 443 | |
fe27cb35 | 444 | perf = data->acpi_data; |
9c0ebcf7 | 445 | next_perf_state = data->freq_table[index].driver_data; |
7650b281 | 446 | if (perf->state == next_perf_state) { |
fe27cb35 | 447 | if (unlikely(data->resume)) { |
2d06d8c4 | 448 | pr_debug("Called after resume, resetting to P%d\n", |
64be7eed | 449 | next_perf_state); |
fe27cb35 VP |
450 | data->resume = 0; |
451 | } else { | |
2d06d8c4 | 452 | pr_debug("Already at target state (P%d)\n", |
64be7eed | 453 | next_perf_state); |
4d8bb537 | 454 | goto out; |
fe27cb35 | 455 | } |
09b4d1ee VP |
456 | } |
457 | ||
64be7eed VP |
458 | switch (data->cpu_feature) { |
459 | case SYSTEM_INTEL_MSR_CAPABLE: | |
460 | cmd.type = SYSTEM_INTEL_MSR_CAPABLE; | |
461 | cmd.addr.msr.reg = MSR_IA32_PERF_CTL; | |
13424f65 | 462 | cmd.val = (u32) perf->states[next_perf_state].control; |
64be7eed | 463 | break; |
3dc9a633 MG |
464 | case SYSTEM_AMD_MSR_CAPABLE: |
465 | cmd.type = SYSTEM_AMD_MSR_CAPABLE; | |
466 | cmd.addr.msr.reg = MSR_AMD_PERF_CTL; | |
467 | cmd.val = (u32) perf->states[next_perf_state].control; | |
468 | break; | |
64be7eed VP |
469 | case SYSTEM_IO_CAPABLE: |
470 | cmd.type = SYSTEM_IO_CAPABLE; | |
471 | cmd.addr.io.port = perf->control_register.address; | |
472 | cmd.addr.io.bit_width = perf->control_register.bit_width; | |
473 | cmd.val = (u32) perf->states[next_perf_state].control; | |
474 | break; | |
475 | default: | |
4d8bb537 MT |
476 | result = -ENODEV; |
477 | goto out; | |
64be7eed | 478 | } |
09b4d1ee | 479 | |
4d8bb537 | 480 | /* cpufreq holds the hotplug lock, so we are safe from here on */ |
fe27cb35 | 481 | if (policy->shared_type != CPUFREQ_SHARED_TYPE_ANY) |
bfa318ad | 482 | cmd.mask = policy->cpus; |
fe27cb35 | 483 | else |
bfa318ad | 484 | cmd.mask = cpumask_of(policy->cpu); |
09b4d1ee | 485 | |
8edc59d9 | 486 | freqs.old = perf->states[perf->state].core_frequency * 1000; |
9c0ebcf7 | 487 | freqs.new = data->freq_table[index].frequency; |
b43a7ffb | 488 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); |
1da177e4 | 489 | |
fe27cb35 | 490 | drv_write(&cmd); |
09b4d1ee | 491 | |
fe27cb35 | 492 | if (acpi_pstate_strict) { |
4d8bb537 | 493 | if (!check_freqs(cmd.mask, freqs.new, data)) { |
2d06d8c4 | 494 | pr_debug("acpi_cpufreq_target failed (%d)\n", |
64be7eed | 495 | policy->cpu); |
4d8bb537 | 496 | result = -EAGAIN; |
e15d8309 | 497 | freqs.new = freqs.old; |
09b4d1ee VP |
498 | } |
499 | } | |
500 | ||
b43a7ffb | 501 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE); |
e15d8309 VK |
502 | |
503 | if (!result) | |
504 | perf->state = next_perf_state; | |
fe27cb35 | 505 | |
4d8bb537 | 506 | out: |
fe27cb35 | 507 | return result; |
1da177e4 LT |
508 | } |
509 | ||
1da177e4 | 510 | static unsigned long |
64be7eed | 511 | acpi_cpufreq_guess_freq(struct acpi_cpufreq_data *data, unsigned int cpu) |
1da177e4 | 512 | { |
64be7eed | 513 | struct acpi_processor_performance *perf = data->acpi_data; |
09b4d1ee | 514 | |
1da177e4 LT |
515 | if (cpu_khz) { |
516 | /* search the closest match to cpu_khz */ | |
517 | unsigned int i; | |
518 | unsigned long freq; | |
09b4d1ee | 519 | unsigned long freqn = perf->states[0].core_frequency * 1000; |
1da177e4 | 520 | |
3a58df35 | 521 | for (i = 0; i < (perf->state_count-1); i++) { |
1da177e4 | 522 | freq = freqn; |
95dd7227 | 523 | freqn = perf->states[i+1].core_frequency * 1000; |
1da177e4 | 524 | if ((2 * cpu_khz) > (freqn + freq)) { |
09b4d1ee | 525 | perf->state = i; |
64be7eed | 526 | return freq; |
1da177e4 LT |
527 | } |
528 | } | |
95dd7227 | 529 | perf->state = perf->state_count-1; |
64be7eed | 530 | return freqn; |
09b4d1ee | 531 | } else { |
1da177e4 | 532 | /* assume CPU is at P0... */ |
09b4d1ee VP |
533 | perf->state = 0; |
534 | return perf->states[0].core_frequency * 1000; | |
535 | } | |
1da177e4 LT |
536 | } |
537 | ||
2fdf66b4 RR |
538 | static void free_acpi_perf_data(void) |
539 | { | |
540 | unsigned int i; | |
541 | ||
542 | /* Freeing a NULL pointer is OK, and alloc_percpu zeroes. */ | |
543 | for_each_possible_cpu(i) | |
544 | free_cpumask_var(per_cpu_ptr(acpi_perf_data, i) | |
545 | ->shared_cpu_map); | |
546 | free_percpu(acpi_perf_data); | |
547 | } | |
548 | ||
615b7300 AP |
549 | static int boost_notify(struct notifier_block *nb, unsigned long action, |
550 | void *hcpu) | |
551 | { | |
552 | unsigned cpu = (long)hcpu; | |
553 | const struct cpumask *cpumask; | |
554 | ||
555 | cpumask = get_cpu_mask(cpu); | |
556 | ||
557 | /* | |
558 | * Clear the boost-disable bit on the CPU_DOWN path so that | |
559 | * this cpu cannot block the remaining ones from boosting. On | |
560 | * the CPU_UP path we simply keep the boost-disable flag in | |
561 | * sync with the current global state. | |
562 | */ | |
563 | ||
564 | switch (action) { | |
565 | case CPU_UP_PREPARE: | |
566 | case CPU_UP_PREPARE_FROZEN: | |
567 | boost_set_msrs(boost_enabled, cpumask); | |
568 | break; | |
569 | ||
570 | case CPU_DOWN_PREPARE: | |
571 | case CPU_DOWN_PREPARE_FROZEN: | |
572 | boost_set_msrs(1, cpumask); | |
573 | break; | |
574 | ||
575 | default: | |
576 | break; | |
577 | } | |
578 | ||
579 | return NOTIFY_OK; | |
580 | } | |
581 | ||
582 | ||
583 | static struct notifier_block boost_nb = { | |
584 | .notifier_call = boost_notify, | |
585 | }; | |
586 | ||
09b4d1ee VP |
587 | /* |
588 | * acpi_cpufreq_early_init - initialize ACPI P-States library | |
589 | * | |
590 | * Initialize the ACPI P-States library (drivers/acpi/processor_perflib.c) | |
591 | * in order to determine correct frequency and voltage pairings. We can | |
592 | * do _PDC and _PSD and find out the processor dependency for the | |
593 | * actual init that will happen later... | |
594 | */ | |
50109292 | 595 | static int __init acpi_cpufreq_early_init(void) |
09b4d1ee | 596 | { |
2fdf66b4 | 597 | unsigned int i; |
2d06d8c4 | 598 | pr_debug("acpi_cpufreq_early_init\n"); |
09b4d1ee | 599 | |
50109292 FY |
600 | acpi_perf_data = alloc_percpu(struct acpi_processor_performance); |
601 | if (!acpi_perf_data) { | |
2d06d8c4 | 602 | pr_debug("Memory allocation error for acpi_perf_data.\n"); |
50109292 | 603 | return -ENOMEM; |
09b4d1ee | 604 | } |
2fdf66b4 | 605 | for_each_possible_cpu(i) { |
eaa95840 | 606 | if (!zalloc_cpumask_var_node( |
80855f73 MT |
607 | &per_cpu_ptr(acpi_perf_data, i)->shared_cpu_map, |
608 | GFP_KERNEL, cpu_to_node(i))) { | |
2fdf66b4 RR |
609 | |
610 | /* Freeing a NULL pointer is OK: alloc_percpu zeroes. */ | |
611 | free_acpi_perf_data(); | |
612 | return -ENOMEM; | |
613 | } | |
614 | } | |
09b4d1ee VP |
615 | |
616 | /* Do initialization in ACPI core */ | |
fe27cb35 VP |
617 | acpi_processor_preregister_performance(acpi_perf_data); |
618 | return 0; | |
09b4d1ee VP |
619 | } |
620 | ||
95625b8f | 621 | #ifdef CONFIG_SMP |
8adcc0c6 VP |
622 | /* |
623 | * Some BIOSes do SW_ANY coordination internally, either set it up in hw | |
624 | * or do it in BIOS firmware and won't inform about it to OS. If not | |
625 | * detected, this has a side effect of making CPU run at a different speed | |
626 | * than OS intended it to run at. Detect it and handle it cleanly. | |
627 | */ | |
628 | static int bios_with_sw_any_bug; | |
629 | ||
1855256c | 630 | static int sw_any_bug_found(const struct dmi_system_id *d) |
8adcc0c6 VP |
631 | { |
632 | bios_with_sw_any_bug = 1; | |
633 | return 0; | |
634 | } | |
635 | ||
1855256c | 636 | static const struct dmi_system_id sw_any_bug_dmi_table[] = { |
8adcc0c6 VP |
637 | { |
638 | .callback = sw_any_bug_found, | |
639 | .ident = "Supermicro Server X6DLP", | |
640 | .matches = { | |
641 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
642 | DMI_MATCH(DMI_BIOS_VERSION, "080010"), | |
643 | DMI_MATCH(DMI_PRODUCT_NAME, "X6DLP"), | |
644 | }, | |
645 | }, | |
646 | { } | |
647 | }; | |
1a8e42fa PB |
648 | |
649 | static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c) | |
650 | { | |
293afe44 JV |
651 | /* Intel Xeon Processor 7100 Series Specification Update |
652 | * http://www.intel.com/Assets/PDF/specupdate/314554.pdf | |
1a8e42fa PB |
653 | * AL30: A Machine Check Exception (MCE) Occurring during an |
654 | * Enhanced Intel SpeedStep Technology Ratio Change May Cause | |
293afe44 | 655 | * Both Processor Cores to Lock Up. */ |
1a8e42fa PB |
656 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
657 | if ((c->x86 == 15) && | |
658 | (c->x86_model == 6) && | |
293afe44 JV |
659 | (c->x86_mask == 8)) { |
660 | printk(KERN_INFO "acpi-cpufreq: Intel(R) " | |
661 | "Xeon(R) 7100 Errata AL30, processors may " | |
662 | "lock up on frequency changes: disabling " | |
663 | "acpi-cpufreq.\n"); | |
1a8e42fa | 664 | return -ENODEV; |
293afe44 | 665 | } |
1a8e42fa PB |
666 | } |
667 | return 0; | |
668 | } | |
95625b8f | 669 | #endif |
8adcc0c6 | 670 | |
64be7eed | 671 | static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) |
1da177e4 | 672 | { |
64be7eed VP |
673 | unsigned int i; |
674 | unsigned int valid_states = 0; | |
675 | unsigned int cpu = policy->cpu; | |
676 | struct acpi_cpufreq_data *data; | |
64be7eed | 677 | unsigned int result = 0; |
92cb7612 | 678 | struct cpuinfo_x86 *c = &cpu_data(policy->cpu); |
64be7eed | 679 | struct acpi_processor_performance *perf; |
293afe44 JV |
680 | #ifdef CONFIG_SMP |
681 | static int blacklisted; | |
682 | #endif | |
1da177e4 | 683 | |
2d06d8c4 | 684 | pr_debug("acpi_cpufreq_cpu_init\n"); |
1da177e4 | 685 | |
1a8e42fa | 686 | #ifdef CONFIG_SMP |
293afe44 JV |
687 | if (blacklisted) |
688 | return blacklisted; | |
689 | blacklisted = acpi_cpufreq_blacklist(c); | |
690 | if (blacklisted) | |
691 | return blacklisted; | |
1a8e42fa PB |
692 | #endif |
693 | ||
d5b73cd8 | 694 | data = kzalloc(sizeof(*data), GFP_KERNEL); |
1da177e4 | 695 | if (!data) |
64be7eed | 696 | return -ENOMEM; |
1da177e4 | 697 | |
f4fd3797 LT |
698 | if (!zalloc_cpumask_var(&data->freqdomain_cpus, GFP_KERNEL)) { |
699 | result = -ENOMEM; | |
700 | goto err_free; | |
701 | } | |
702 | ||
b36128c8 | 703 | data->acpi_data = per_cpu_ptr(acpi_perf_data, cpu); |
f1625066 | 704 | per_cpu(acfreq_data, cpu) = data; |
1da177e4 | 705 | |
95dd7227 | 706 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) |
fe27cb35 | 707 | acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS; |
1da177e4 | 708 | |
fe27cb35 | 709 | result = acpi_processor_register_performance(data->acpi_data, cpu); |
1da177e4 | 710 | if (result) |
f4fd3797 | 711 | goto err_free_mask; |
1da177e4 | 712 | |
09b4d1ee | 713 | perf = data->acpi_data; |
09b4d1ee | 714 | policy->shared_type = perf->shared_type; |
95dd7227 | 715 | |
46f18e3a | 716 | /* |
95dd7227 | 717 | * Will let policy->cpus know about dependency only when software |
46f18e3a VP |
718 | * coordination is required. |
719 | */ | |
720 | if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL || | |
8adcc0c6 | 721 | policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) { |
835481d9 | 722 | cpumask_copy(policy->cpus, perf->shared_cpu_map); |
8adcc0c6 | 723 | } |
f4fd3797 | 724 | cpumask_copy(data->freqdomain_cpus, perf->shared_cpu_map); |
8adcc0c6 VP |
725 | |
726 | #ifdef CONFIG_SMP | |
727 | dmi_check_system(sw_any_bug_dmi_table); | |
2624f90c | 728 | if (bios_with_sw_any_bug && !policy_is_shared(policy)) { |
8adcc0c6 | 729 | policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; |
835481d9 | 730 | cpumask_copy(policy->cpus, cpu_core_mask(cpu)); |
8adcc0c6 | 731 | } |
acd31624 AP |
732 | |
733 | if (check_amd_hwpstate_cpu(cpu) && !acpi_pstate_strict) { | |
734 | cpumask_clear(policy->cpus); | |
735 | cpumask_set_cpu(cpu, policy->cpus); | |
f4fd3797 | 736 | cpumask_copy(data->freqdomain_cpus, cpu_sibling_mask(cpu)); |
acd31624 AP |
737 | policy->shared_type = CPUFREQ_SHARED_TYPE_HW; |
738 | pr_info_once(PFX "overriding BIOS provided _PSD data\n"); | |
739 | } | |
8adcc0c6 | 740 | #endif |
09b4d1ee | 741 | |
1da177e4 | 742 | /* capability check */ |
09b4d1ee | 743 | if (perf->state_count <= 1) { |
2d06d8c4 | 744 | pr_debug("No P-States\n"); |
1da177e4 LT |
745 | result = -ENODEV; |
746 | goto err_unreg; | |
747 | } | |
09b4d1ee | 748 | |
fe27cb35 VP |
749 | if (perf->control_register.space_id != perf->status_register.space_id) { |
750 | result = -ENODEV; | |
751 | goto err_unreg; | |
752 | } | |
753 | ||
754 | switch (perf->control_register.space_id) { | |
64be7eed | 755 | case ACPI_ADR_SPACE_SYSTEM_IO: |
c40a4518 MG |
756 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && |
757 | boot_cpu_data.x86 == 0xf) { | |
758 | pr_debug("AMD K8 systems must use native drivers.\n"); | |
759 | result = -ENODEV; | |
760 | goto err_unreg; | |
761 | } | |
2d06d8c4 | 762 | pr_debug("SYSTEM IO addr space\n"); |
dde9f7ba VP |
763 | data->cpu_feature = SYSTEM_IO_CAPABLE; |
764 | break; | |
64be7eed | 765 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
2d06d8c4 | 766 | pr_debug("HARDWARE addr space\n"); |
3dc9a633 MG |
767 | if (check_est_cpu(cpu)) { |
768 | data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE; | |
769 | break; | |
dde9f7ba | 770 | } |
3dc9a633 MG |
771 | if (check_amd_hwpstate_cpu(cpu)) { |
772 | data->cpu_feature = SYSTEM_AMD_MSR_CAPABLE; | |
773 | break; | |
774 | } | |
775 | result = -ENODEV; | |
776 | goto err_unreg; | |
64be7eed | 777 | default: |
2d06d8c4 | 778 | pr_debug("Unknown addr space %d\n", |
64be7eed | 779 | (u32) (perf->control_register.space_id)); |
1da177e4 LT |
780 | result = -ENODEV; |
781 | goto err_unreg; | |
782 | } | |
783 | ||
d5b73cd8 | 784 | data->freq_table = kmalloc(sizeof(*data->freq_table) * |
95dd7227 | 785 | (perf->state_count+1), GFP_KERNEL); |
1da177e4 LT |
786 | if (!data->freq_table) { |
787 | result = -ENOMEM; | |
788 | goto err_unreg; | |
789 | } | |
790 | ||
791 | /* detect transition latency */ | |
792 | policy->cpuinfo.transition_latency = 0; | |
3a58df35 | 793 | for (i = 0; i < perf->state_count; i++) { |
64be7eed VP |
794 | if ((perf->states[i].transition_latency * 1000) > |
795 | policy->cpuinfo.transition_latency) | |
796 | policy->cpuinfo.transition_latency = | |
797 | perf->states[i].transition_latency * 1000; | |
1da177e4 | 798 | } |
1da177e4 | 799 | |
a59d1637 PV |
800 | /* Check for high latency (>20uS) from buggy BIOSes, like on T42 */ |
801 | if (perf->control_register.space_id == ACPI_ADR_SPACE_FIXED_HARDWARE && | |
802 | policy->cpuinfo.transition_latency > 20 * 1000) { | |
a59d1637 | 803 | policy->cpuinfo.transition_latency = 20 * 1000; |
61c8c67e JP |
804 | printk_once(KERN_INFO |
805 | "P-state transition latency capped at 20 uS\n"); | |
a59d1637 PV |
806 | } |
807 | ||
1da177e4 | 808 | /* table init */ |
3a58df35 DJ |
809 | for (i = 0; i < perf->state_count; i++) { |
810 | if (i > 0 && perf->states[i].core_frequency >= | |
3cdf552b | 811 | data->freq_table[valid_states-1].frequency / 1000) |
fe27cb35 VP |
812 | continue; |
813 | ||
50701588 | 814 | data->freq_table[valid_states].driver_data = i; |
fe27cb35 | 815 | data->freq_table[valid_states].frequency = |
64be7eed | 816 | perf->states[i].core_frequency * 1000; |
fe27cb35 | 817 | valid_states++; |
1da177e4 | 818 | } |
3d4a7ef3 | 819 | data->freq_table[valid_states].frequency = CPUFREQ_TABLE_END; |
8edc59d9 | 820 | perf->state = 0; |
1da177e4 | 821 | |
776b57be | 822 | result = cpufreq_table_validate_and_show(policy, data->freq_table); |
95dd7227 | 823 | if (result) |
1da177e4 | 824 | goto err_freqfree; |
1da177e4 | 825 | |
d876dfbb TR |
826 | if (perf->states[0].core_frequency * 1000 != policy->cpuinfo.max_freq) |
827 | printk(KERN_WARNING FW_WARN "P-state 0 is not max freq\n"); | |
828 | ||
a507ac4b | 829 | switch (perf->control_register.space_id) { |
64be7eed | 830 | case ACPI_ADR_SPACE_SYSTEM_IO: |
1bab64d5 VK |
831 | /* |
832 | * The core will not set policy->cur, because | |
833 | * cpufreq_driver->get is NULL, so we need to set it here. | |
834 | * However, we have to guess it, because the current speed is | |
835 | * unknown and not detectable via IO ports. | |
836 | */ | |
dde9f7ba VP |
837 | policy->cur = acpi_cpufreq_guess_freq(data, policy->cpu); |
838 | break; | |
64be7eed | 839 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
7650b281 | 840 | acpi_cpufreq_driver.get = get_cur_freq_on_cpu; |
dde9f7ba | 841 | break; |
64be7eed | 842 | default: |
dde9f7ba VP |
843 | break; |
844 | } | |
845 | ||
1da177e4 LT |
846 | /* notify BIOS that we exist */ |
847 | acpi_processor_notify_smm(THIS_MODULE); | |
848 | ||
2d06d8c4 | 849 | pr_debug("CPU%u - ACPI performance management activated.\n", cpu); |
09b4d1ee | 850 | for (i = 0; i < perf->state_count; i++) |
2d06d8c4 | 851 | pr_debug(" %cP%d: %d MHz, %d mW, %d uS\n", |
64be7eed | 852 | (i == perf->state ? '*' : ' '), i, |
09b4d1ee VP |
853 | (u32) perf->states[i].core_frequency, |
854 | (u32) perf->states[i].power, | |
855 | (u32) perf->states[i].transition_latency); | |
1da177e4 | 856 | |
4b31e774 DB |
857 | /* |
858 | * the first call to ->target() should result in us actually | |
859 | * writing something to the appropriate registers. | |
860 | */ | |
861 | data->resume = 1; | |
64be7eed | 862 | |
fe27cb35 | 863 | return result; |
1da177e4 | 864 | |
95dd7227 | 865 | err_freqfree: |
1da177e4 | 866 | kfree(data->freq_table); |
95dd7227 | 867 | err_unreg: |
09b4d1ee | 868 | acpi_processor_unregister_performance(perf, cpu); |
f4fd3797 LT |
869 | err_free_mask: |
870 | free_cpumask_var(data->freqdomain_cpus); | |
95dd7227 | 871 | err_free: |
1da177e4 | 872 | kfree(data); |
f1625066 | 873 | per_cpu(acfreq_data, cpu) = NULL; |
1da177e4 | 874 | |
64be7eed | 875 | return result; |
1da177e4 LT |
876 | } |
877 | ||
64be7eed | 878 | static int acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy) |
1da177e4 | 879 | { |
f1625066 | 880 | struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu); |
1da177e4 | 881 | |
2d06d8c4 | 882 | pr_debug("acpi_cpufreq_cpu_exit\n"); |
1da177e4 LT |
883 | |
884 | if (data) { | |
885 | cpufreq_frequency_table_put_attr(policy->cpu); | |
f1625066 | 886 | per_cpu(acfreq_data, policy->cpu) = NULL; |
64be7eed VP |
887 | acpi_processor_unregister_performance(data->acpi_data, |
888 | policy->cpu); | |
f4fd3797 | 889 | free_cpumask_var(data->freqdomain_cpus); |
dab5fff1 | 890 | kfree(data->freq_table); |
1da177e4 LT |
891 | kfree(data); |
892 | } | |
893 | ||
64be7eed | 894 | return 0; |
1da177e4 LT |
895 | } |
896 | ||
64be7eed | 897 | static int acpi_cpufreq_resume(struct cpufreq_policy *policy) |
1da177e4 | 898 | { |
f1625066 | 899 | struct acpi_cpufreq_data *data = per_cpu(acfreq_data, policy->cpu); |
1da177e4 | 900 | |
2d06d8c4 | 901 | pr_debug("acpi_cpufreq_resume\n"); |
1da177e4 LT |
902 | |
903 | data->resume = 1; | |
904 | ||
64be7eed | 905 | return 0; |
1da177e4 LT |
906 | } |
907 | ||
64be7eed | 908 | static struct freq_attr *acpi_cpufreq_attr[] = { |
1da177e4 | 909 | &cpufreq_freq_attr_scaling_available_freqs, |
f4fd3797 | 910 | &freqdomain_cpus, |
11269ff5 | 911 | NULL, /* this is a placeholder for cpb, do not remove */ |
1da177e4 LT |
912 | NULL, |
913 | }; | |
914 | ||
915 | static struct cpufreq_driver acpi_cpufreq_driver = { | |
db9be219 | 916 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 917 | .target_index = acpi_cpufreq_target, |
e2f74f35 TR |
918 | .bios_limit = acpi_processor_get_bios_limit, |
919 | .init = acpi_cpufreq_cpu_init, | |
920 | .exit = acpi_cpufreq_cpu_exit, | |
921 | .resume = acpi_cpufreq_resume, | |
922 | .name = "acpi-cpufreq", | |
e2f74f35 | 923 | .attr = acpi_cpufreq_attr, |
1da177e4 LT |
924 | }; |
925 | ||
615b7300 AP |
926 | static void __init acpi_cpufreq_boost_init(void) |
927 | { | |
928 | if (boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA)) { | |
929 | msrs = msrs_alloc(); | |
930 | ||
931 | if (!msrs) | |
932 | return; | |
933 | ||
934 | boost_supported = true; | |
935 | boost_enabled = boost_state(0); | |
936 | ||
937 | get_online_cpus(); | |
938 | ||
939 | /* Force all MSRs to the same value */ | |
940 | boost_set_msrs(boost_enabled, cpu_online_mask); | |
941 | ||
942 | register_cpu_notifier(&boost_nb); | |
943 | ||
944 | put_online_cpus(); | |
945 | } else | |
946 | global_boost.attr.mode = 0444; | |
947 | ||
948 | /* We create the boost file in any case, though for systems without | |
949 | * hardware support it will be read-only and hardwired to return 0. | |
950 | */ | |
2361be23 | 951 | if (cpufreq_sysfs_create_file(&(global_boost.attr))) |
615b7300 AP |
952 | pr_warn(PFX "could not register global boost sysfs file\n"); |
953 | else | |
954 | pr_debug("registered global boost sysfs file\n"); | |
955 | } | |
956 | ||
957 | static void __exit acpi_cpufreq_boost_exit(void) | |
958 | { | |
2361be23 | 959 | cpufreq_sysfs_remove_file(&(global_boost.attr)); |
615b7300 AP |
960 | |
961 | if (msrs) { | |
962 | unregister_cpu_notifier(&boost_nb); | |
963 | ||
964 | msrs_free(msrs); | |
965 | msrs = NULL; | |
966 | } | |
967 | } | |
968 | ||
64be7eed | 969 | static int __init acpi_cpufreq_init(void) |
1da177e4 | 970 | { |
50109292 FY |
971 | int ret; |
972 | ||
8a61e12e YL |
973 | /* don't keep reloading if cpufreq_driver exists */ |
974 | if (cpufreq_get_current_driver()) | |
975 | return 0; | |
976 | ||
ee297533 YL |
977 | if (acpi_disabled) |
978 | return 0; | |
979 | ||
2d06d8c4 | 980 | pr_debug("acpi_cpufreq_init\n"); |
1da177e4 | 981 | |
50109292 FY |
982 | ret = acpi_cpufreq_early_init(); |
983 | if (ret) | |
984 | return ret; | |
09b4d1ee | 985 | |
11269ff5 AP |
986 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
987 | /* this is a sysfs file with a strange name and an even stranger | |
988 | * semantic - per CPU instantiation, but system global effect. | |
989 | * Lets enable it only on AMD CPUs for compatibility reasons and | |
990 | * only if configured. This is considered legacy code, which | |
991 | * will probably be removed at some point in the future. | |
992 | */ | |
993 | if (check_amd_hwpstate_cpu(0)) { | |
994 | struct freq_attr **iter; | |
995 | ||
996 | pr_debug("adding sysfs entry for cpb\n"); | |
997 | ||
998 | for (iter = acpi_cpufreq_attr; *iter != NULL; iter++) | |
999 | ; | |
1000 | ||
1001 | /* make sure there is a terminator behind it */ | |
1002 | if (iter[1] == NULL) | |
1003 | *iter = &cpb; | |
1004 | } | |
1005 | #endif | |
1006 | ||
847aef6f AM |
1007 | ret = cpufreq_register_driver(&acpi_cpufreq_driver); |
1008 | if (ret) | |
2fdf66b4 | 1009 | free_acpi_perf_data(); |
615b7300 AP |
1010 | else |
1011 | acpi_cpufreq_boost_init(); | |
847aef6f AM |
1012 | |
1013 | return ret; | |
1da177e4 LT |
1014 | } |
1015 | ||
64be7eed | 1016 | static void __exit acpi_cpufreq_exit(void) |
1da177e4 | 1017 | { |
2d06d8c4 | 1018 | pr_debug("acpi_cpufreq_exit\n"); |
1da177e4 | 1019 | |
615b7300 AP |
1020 | acpi_cpufreq_boost_exit(); |
1021 | ||
1da177e4 LT |
1022 | cpufreq_unregister_driver(&acpi_cpufreq_driver); |
1023 | ||
50f4ddd4 | 1024 | free_acpi_perf_data(); |
1da177e4 LT |
1025 | } |
1026 | ||
d395bf12 | 1027 | module_param(acpi_pstate_strict, uint, 0644); |
64be7eed | 1028 | MODULE_PARM_DESC(acpi_pstate_strict, |
95dd7227 DJ |
1029 | "value 0 or non-zero. non-zero -> strict ACPI checks are " |
1030 | "performed during frequency changes."); | |
1da177e4 LT |
1031 | |
1032 | late_initcall(acpi_cpufreq_init); | |
1033 | module_exit(acpi_cpufreq_exit); | |
1034 | ||
efa17194 MG |
1035 | static const struct x86_cpu_id acpi_cpufreq_ids[] = { |
1036 | X86_FEATURE_MATCH(X86_FEATURE_ACPI), | |
1037 | X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE), | |
1038 | {} | |
1039 | }; | |
1040 | MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); | |
1041 | ||
c655affb RW |
1042 | static const struct acpi_device_id processor_device_ids[] = { |
1043 | {ACPI_PROCESSOR_OBJECT_HID, }, | |
1044 | {ACPI_PROCESSOR_DEVICE_HID, }, | |
1045 | {}, | |
1046 | }; | |
1047 | MODULE_DEVICE_TABLE(acpi, processor_device_ids); | |
1048 | ||
1da177e4 | 1049 | MODULE_ALIAS("acpi"); |