[deliverable/linux.git] / drivers / cpufreq / cpufreq-cpu0.c

/*
 * Copyright (C) 2012 Freescale Semiconductor, Inc.
 *
 * The OPP code in function cpu0_set_target() is reused from
 * drivers/cpufreq/omap-cpufreq.c
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt

#include <linux/clk.h>
#include <linux/cpu.h>
#include <linux/cpufreq.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pm_opp.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>

static unsigned int transition_latency;
static unsigned int voltage_tolerance; /* in percentage */

static struct device *cpu_dev;
static struct clk *cpu_clk;
static struct regulator *cpu_reg;
static struct cpufreq_frequency_table *freq_table;

static unsigned int cpu0_get_speed(unsigned int cpu)
{
	return clk_get_rate(cpu_clk) / 1000;
}

static int cpu0_set_target(struct cpufreq_policy *policy, unsigned int index)
{
	struct dev_pm_opp *opp;
	unsigned long volt = 0, volt_old = 0, tol = 0;
	unsigned int old_freq, new_freq;
	long freq_Hz, freq_exact;
	int ret;

	freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
	if (freq_Hz < 0)
		freq_Hz = freq_table[index].frequency * 1000;

	freq_exact = freq_Hz;
	new_freq = freq_Hz / 1000;
	old_freq = clk_get_rate(cpu_clk) / 1000;

	if (!IS_ERR(cpu_reg)) {
		rcu_read_lock();
		opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz);
		if (IS_ERR(opp)) {
			rcu_read_unlock();
			pr_err("failed to find OPP for %ld\n", freq_Hz);
			return PTR_ERR(opp);
		}
		volt = dev_pm_opp_get_voltage(opp);
		rcu_read_unlock();
		tol = volt * voltage_tolerance / 100;
		volt_old = regulator_get_voltage(cpu_reg);
	}

	pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n",
		 old_freq / 1000, volt_old ? volt_old / 1000 : -1,
		 new_freq / 1000, volt ? volt / 1000 : -1);

	/* scaling up?  scale voltage before frequency */
	if (!IS_ERR(cpu_reg) && new_freq > old_freq) {
		ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
		if (ret) {
			pr_err("failed to scale voltage up: %d\n", ret);
			return ret;
		}
	}

	ret = clk_set_rate(cpu_clk, freq_exact);
	if (ret) {
		pr_err("failed to set clock rate: %d\n", ret);
		if (!IS_ERR(cpu_reg))
			regulator_set_voltage_tol(cpu_reg, volt_old, tol);
		return ret;
	}

	/* scaling down?  scale voltage after frequency */
	if (!IS_ERR(cpu_reg) && new_freq < old_freq) {
		ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
		if (ret) {
			pr_err("failed to scale voltage down: %d\n", ret);
			clk_set_rate(cpu_clk, old_freq * 1000);
		}
	}

	return ret;
}

static int cpu0_cpufreq_init(struct cpufreq_policy *policy)
{
	return cpufreq_generic_init(policy, freq_table, transition_latency);
}

static struct cpufreq_driver cpu0_cpufreq_driver = {
	.flags = CPUFREQ_STICKY,
	.verify = cpufreq_generic_frequency_table_verify,
	.target_index = cpu0_set_target,
	.get = cpu0_get_speed,
	.init = cpu0_cpufreq_init,
	.exit = cpufreq_generic_exit,
	.name = "generic_cpu0",
	.attr = cpufreq_generic_attr,
};

static int cpu0_cpufreq_probe(struct platform_device *pdev)
{
	struct device_node *np;
	int ret;

	cpu_dev = get_cpu_device(0);
	if (!cpu_dev) {
		pr_err("failed to get cpu0 device\n");
		return -ENODEV;
	}

	np = of_node_get(cpu_dev->of_node);
	if (!np) {
		pr_err("failed to find cpu0 node\n");
		return -ENOENT;
	}

	cpu_reg = devm_regulator_get_optional(cpu_dev, "cpu0");
	if (IS_ERR(cpu_reg)) {
		/*
		 * If cpu0 regulator supply node is present, but regulator is
		 * not yet registered, we should try defering probe.
		 */
		if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
			dev_err(cpu_dev, "cpu0 regulator not ready, retry\n");
			ret = -EPROBE_DEFER;
			goto out_put_node;
		}
		pr_warn("failed to get cpu0 regulator: %ld\n",
			PTR_ERR(cpu_reg));
	}

	cpu_clk = devm_clk_get(cpu_dev, NULL);
	if (IS_ERR(cpu_clk)) {
		ret = PTR_ERR(cpu_clk);
		pr_err("failed to get cpu0 clock: %d\n", ret);
		goto out_put_node;
	}

	ret = of_init_opp_table(cpu_dev);
	if (ret) {
		pr_err("failed to init OPP table: %d\n", ret);
		goto out_put_node;
	}

	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
	if (ret) {
		pr_err("failed to init cpufreq table: %d\n", ret);
		goto out_put_node;
	}

	of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance);

	if (of_property_read_u32(np, "clock-latency", &transition_latency))
		transition_latency = CPUFREQ_ETERNAL;

	if (!IS_ERR(cpu_reg)) {
		struct dev_pm_opp *opp;
		unsigned long min_uV, max_uV;
		int i;

		/*
		 * OPP is maintained in order of increasing frequency, and
		 * freq_table initialised from OPP is therefore sorted in the
		 * same order.
		 */
		for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
			;
		rcu_read_lock();
		opp = dev_pm_opp_find_freq_exact(cpu_dev,
				freq_table[0].frequency * 1000, true);
		min_uV = dev_pm_opp_get_voltage(opp);
		opp = dev_pm_opp_find_freq_exact(cpu_dev,
				freq_table[i-1].frequency * 1000, true);
		max_uV = dev_pm_opp_get_voltage(opp);
		rcu_read_unlock();
		ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
		if (ret > 0)
			transition_latency += ret * 1000;
	}

	ret = cpufreq_register_driver(&cpu0_cpufreq_driver);
	if (ret) {
		pr_err("failed register driver: %d\n", ret);
		goto out_free_table;
	}

	of_node_put(np);
	return 0;

out_free_table:
	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
out_put_node:
	of_node_put(np);
	return ret;
}

static int cpu0_cpufreq_remove(struct platform_device *pdev)
{
	cpufreq_unregister_driver(&cpu0_cpufreq_driver);
	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);

	return 0;
}

static struct platform_driver cpu0_cpufreq_platdrv = {
	.driver = {
		.name	= "cpufreq-cpu0",
		.owner	= THIS_MODULE,
	},
	.probe		= cpu0_cpufreq_probe,
	.remove		= cpu0_cpufreq_remove,
};
module_platform_driver(cpu0_cpufreq_platdrv);

MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
MODULE_DESCRIPTION("Generic CPU0 cpufreq driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
95ceafd4 SG	1	/*
	2	* Copyright (C) 2012 Freescale Semiconductor, Inc.
	3	*
	4	* The OPP code in function cpu0_set_target() is reused from
	5	* drivers/cpufreq/omap-cpufreq.c
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	13
	14	#include <linux/clk.h>
e1825b25	15	#include <linux/cpu.h>
95ceafd4 SG	16	#include <linux/cpufreq.h>
	17	#include <linux/err.h>
	18	#include <linux/module.h>
	19	#include <linux/of.h>
e4db1c74	20	#include <linux/pm_opp.h>
5553f9e2	21	#include <linux/platform_device.h>
95ceafd4 SG	22	#include <linux/regulator/consumer.h>
	23	#include <linux/slab.h>
	24
	25	static unsigned int transition_latency;
	26	static unsigned int voltage_tolerance; /* in percentage */
	27
	28	static struct device *cpu_dev;
	29	static struct clk *cpu_clk;
	30	static struct regulator *cpu_reg;
	31	static struct cpufreq_frequency_table *freq_table;
	32
95ceafd4 SG	33	static unsigned int cpu0_get_speed(unsigned int cpu)
	34	{
	35	return clk_get_rate(cpu_clk) / 1000;
	36	}
	37
9c0ebcf7	38	static int cpu0_set_target(struct cpufreq_policy *policy, unsigned int index)
95ceafd4	39	{
47d43ba7	40	struct dev_pm_opp *opp;
5df60559	41	unsigned long volt = 0, volt_old = 0, tol = 0;
d4019f0a	42	unsigned int old_freq, new_freq;
0ca68436	43	long freq_Hz, freq_exact;
95ceafd4 SG	44	int ret;
95ceafd4 SG	45
95ceafd4 SG	46	freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
	47	if (freq_Hz < 0)
	48	freq_Hz = freq_table[index].frequency * 1000;
95ceafd4	49
d4019f0a VK	50	freq_exact = freq_Hz;
	51	new_freq = freq_Hz / 1000;
	52	old_freq = clk_get_rate(cpu_clk) / 1000;
95ceafd4	53
4a511de9	54	if (!IS_ERR(cpu_reg)) {
78e8eb8f	55	rcu_read_lock();
5d4879cd	56	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz);
95ceafd4	57	if (IS_ERR(opp)) {
78e8eb8f	58	rcu_read_unlock();
95ceafd4	59	pr_err("failed to find OPP for %ld\n", freq_Hz);
d4019f0a	60	return PTR_ERR(opp);
95ceafd4	61	}
5d4879cd	62	volt = dev_pm_opp_get_voltage(opp);
78e8eb8f	63	rcu_read_unlock();
95ceafd4 SG	64	tol = volt * voltage_tolerance / 100;
	65	volt_old = regulator_get_voltage(cpu_reg);
	66	}
	67
	68	pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n",
d4019f0a VK	69	old_freq / 1000, volt_old ? volt_old / 1000 : -1,
d4019f0a VK	70	new_freq / 1000, volt ? volt / 1000 : -1);
95ceafd4 SG	71
95ceafd4 SG	72	/* scaling up? scale voltage before frequency */
d4019f0a	73	if (!IS_ERR(cpu_reg) && new_freq > old_freq) {
95ceafd4 SG	74	ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
	75	if (ret) {
	76	pr_err("failed to scale voltage up: %d\n", ret);
d4019f0a	77	return ret;
95ceafd4 SG	78	}
	79	}
	80
0ca68436	81	ret = clk_set_rate(cpu_clk, freq_exact);
95ceafd4 SG	82	if (ret) {
95ceafd4 SG	83	pr_err("failed to set clock rate: %d\n", ret);
4a511de9	84	if (!IS_ERR(cpu_reg))
95ceafd4	85	regulator_set_voltage_tol(cpu_reg, volt_old, tol);
d4019f0a	86	return ret;
95ceafd4 SG	87	}
	88
	89	/* scaling down? scale voltage after frequency */
d4019f0a	90	if (!IS_ERR(cpu_reg) && new_freq < old_freq) {
95ceafd4 SG	91	ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
	92	if (ret) {
	93	pr_err("failed to scale voltage down: %d\n", ret);
d4019f0a	94	clk_set_rate(cpu_clk, old_freq * 1000);
95ceafd4 SG	95	}
	96	}
	97
fd143b4d	98	return ret;
95ceafd4 SG	99	}
	100
	101	static int cpu0_cpufreq_init(struct cpufreq_policy *policy)
	102	{
78b3d109	103	return cpufreq_generic_init(policy, freq_table, transition_latency);
95ceafd4 SG	104	}
95ceafd4 SG	105
95ceafd4 SG	106	static struct cpufreq_driver cpu0_cpufreq_driver = {
95ceafd4 SG	107	.flags = CPUFREQ_STICKY,
f793d79f	108	.verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7	109	.target_index = cpu0_set_target,
95ceafd4 SG	110	.get = cpu0_get_speed,
95ceafd4 SG	111	.init = cpu0_cpufreq_init,
f793d79f	112	.exit = cpufreq_generic_exit,
95ceafd4	113	.name = "generic_cpu0",
f793d79f	114	.attr = cpufreq_generic_attr,
95ceafd4 SG	115	};
95ceafd4 SG	116
5553f9e2	117	static int cpu0_cpufreq_probe(struct platform_device *pdev)
95ceafd4	118	{
f837a9b5	119	struct device_node *np;
95ceafd4 SG	120	int ret;
95ceafd4 SG	121
e1825b25 SK	122	cpu_dev = get_cpu_device(0);
	123	if (!cpu_dev) {
	124	pr_err("failed to get cpu0 device\n");
	125	return -ENODEV;
	126	}
6754f556	127
f837a9b5	128	np = of_node_get(cpu_dev->of_node);
95ceafd4 SG	129	if (!np) {
95ceafd4 SG	130	pr_err("failed to find cpu0 node\n");
f837a9b5	131	return -ENOENT;
95ceafd4 SG	132	}
95ceafd4 SG	133
7d748971	134	cpu_reg = devm_regulator_get_optional(cpu_dev, "cpu0");
fc31d6f5 NM	135	if (IS_ERR(cpu_reg)) {
	136	/*
	137	* If cpu0 regulator supply node is present, but regulator is
	138	* not yet registered, we should try defering probe.
	139	*/
	140	if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
	141	dev_err(cpu_dev, "cpu0 regulator not ready, retry\n");
	142	ret = -EPROBE_DEFER;
	143	goto out_put_node;
	144	}
	145	pr_warn("failed to get cpu0 regulator: %ld\n",
	146	PTR_ERR(cpu_reg));
fc31d6f5 NM	147	}
fc31d6f5 NM	148
5553f9e2	149	cpu_clk = devm_clk_get(cpu_dev, NULL);
95ceafd4 SG	150	if (IS_ERR(cpu_clk)) {
	151	ret = PTR_ERR(cpu_clk);
	152	pr_err("failed to get cpu0 clock: %d\n", ret);
	153	goto out_put_node;
	154	}
	155
95ceafd4 SG	156	ret = of_init_opp_table(cpu_dev);
	157	if (ret) {
	158	pr_err("failed to init OPP table: %d\n", ret);
	159	goto out_put_node;
	160	}
	161
5d4879cd	162	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
95ceafd4 SG	163	if (ret) {
	164	pr_err("failed to init cpufreq table: %d\n", ret);
	165	goto out_put_node;
	166	}
	167
	168	of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance);
	169
	170	if (of_property_read_u32(np, "clock-latency", &transition_latency))
	171	transition_latency = CPUFREQ_ETERNAL;
	172
43c638e3	173	if (!IS_ERR(cpu_reg)) {
47d43ba7	174	struct dev_pm_opp *opp;
95ceafd4 SG	175	unsigned long min_uV, max_uV;
	176	int i;
	177
	178	/*
	179	* OPP is maintained in order of increasing frequency, and
	180	* freq_table initialised from OPP is therefore sorted in the
	181	* same order.
	182	*/
	183	for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
	184	;
78e8eb8f	185	rcu_read_lock();
5d4879cd	186	opp = dev_pm_opp_find_freq_exact(cpu_dev,
95ceafd4	187	freq_table[0].frequency * 1000, true);
5d4879cd NM	188	min_uV = dev_pm_opp_get_voltage(opp);
5d4879cd NM	189	opp = dev_pm_opp_find_freq_exact(cpu_dev,
95ceafd4	190	freq_table[i-1].frequency * 1000, true);
5d4879cd	191	max_uV = dev_pm_opp_get_voltage(opp);
78e8eb8f	192	rcu_read_unlock();
95ceafd4 SG	193	ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
	194	if (ret > 0)
	195	transition_latency += ret * 1000;
	196	}
	197
	198	ret = cpufreq_register_driver(&cpu0_cpufreq_driver);
	199	if (ret) {
	200	pr_err("failed register driver: %d\n", ret);
	201	goto out_free_table;
	202	}
	203
	204	of_node_put(np);
	205	return 0;
	206
	207	out_free_table:
5d4879cd	208	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
95ceafd4 SG	209	out_put_node:
	210	of_node_put(np);
	211	return ret;
	212	}
5553f9e2 SG	213
	214	static int cpu0_cpufreq_remove(struct platform_device *pdev)
	215	{
	216	cpufreq_unregister_driver(&cpu0_cpufreq_driver);
5d4879cd	217	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
5553f9e2 SG	218
	219	return 0;
	220	}
	221
	222	static struct platform_driver cpu0_cpufreq_platdrv = {
	223	.driver = {
	224	.name = "cpufreq-cpu0",
	225	.owner = THIS_MODULE,
	226	},
	227	.probe = cpu0_cpufreq_probe,
	228	.remove = cpu0_cpufreq_remove,
	229	};
	230	module_platform_driver(cpu0_cpufreq_platdrv);
95ceafd4 SG	231
	232	MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
	233	MODULE_DESCRIPTION("Generic CPU0 cpufreq driver");
	234	MODULE_LICENSE("GPL");