[deliverable/linux.git] / drivers / cpufreq / cris-etraxfs-cpufreq.c

#include <linux/init.h>
#include <linux/module.h>
#include <linux/cpufreq.h>
#include <hwregs/reg_map.h>
#include <arch/hwregs/reg_rdwr.h>
#include <arch/hwregs/config_defs.h>
#include <arch/hwregs/bif_core_defs.h>

static int
cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
			 void *data);

static struct notifier_block cris_sdram_freq_notifier_block = {
	.notifier_call = cris_sdram_freq_notifier
};

static struct cpufreq_frequency_table cris_freq_table[] = {
	{0x01, 6000},
	{0x02, 200000},
	{0, CPUFREQ_TABLE_END},
};

static unsigned int cris_freq_get_cpu_frequency(unsigned int cpu)
{
	reg_config_rw_clk_ctrl clk_ctrl;
	clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
	return clk_ctrl.pll ? 200000 : 6000;
}

static void cris_freq_set_cpu_state(struct cpufreq_policy *policy,
		unsigned int state)
{
	struct cpufreq_freqs freqs;
	reg_config_rw_clk_ctrl clk_ctrl;
	clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);

	freqs.old = cris_freq_get_cpu_frequency(policy->cpu);
	freqs.new = cris_freq_table[state].frequency;

	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);

	local_irq_disable();

	/* Even though we may be SMP they will share the same clock
	 * so all settings are made on CPU0. */
	if (cris_freq_table[state].frequency == 200000)
		clk_ctrl.pll = 1;
	else
		clk_ctrl.pll = 0;
	REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl);

	local_irq_enable();

	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
};

static int cris_freq_verify(struct cpufreq_policy *policy)
{
	return cpufreq_frequency_table_verify(policy, &cris_freq_table[0]);
}

static int cris_freq_target(struct cpufreq_policy *policy,
			    unsigned int target_freq, unsigned int relation)
{
	unsigned int newstate = 0;

	if (cpufreq_frequency_table_target
	    (policy, cris_freq_table, target_freq, relation, &newstate))
		return -EINVAL;

	cris_freq_set_cpu_state(policy, newstate);

	return 0;
}

static int cris_freq_cpu_init(struct cpufreq_policy *policy)
{
	int result;

	/* cpuinfo and default policy values */
	policy->cpuinfo.transition_latency = 1000000;	/* 1ms */
	policy->cur = cris_freq_get_cpu_frequency(0);

	result = cpufreq_frequency_table_cpuinfo(policy, cris_freq_table);
	if (result)
		return (result);

	cpufreq_frequency_table_get_attr(cris_freq_table, policy->cpu);

	return 0;
}

static int cris_freq_cpu_exit(struct cpufreq_policy *policy)
{
	cpufreq_frequency_table_put_attr(policy->cpu);
	return 0;
}

static struct freq_attr *cris_freq_attr[] = {
	&cpufreq_freq_attr_scaling_available_freqs,
	NULL,
};

static struct cpufreq_driver cris_freq_driver = {
	.get = cris_freq_get_cpu_frequency,
	.verify = cris_freq_verify,
	.target = cris_freq_target,
	.init = cris_freq_cpu_init,
	.exit = cris_freq_cpu_exit,
	.name = "cris_freq",
	.attr = cris_freq_attr,
};

static int __init cris_freq_init(void)
{
	int ret;
	ret = cpufreq_register_driver(&cris_freq_driver);
	cpufreq_register_notifier(&cris_sdram_freq_notifier_block,
				  CPUFREQ_TRANSITION_NOTIFIER);
	return ret;
}

static int
cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
			 void *data)
{
	int i;
	struct cpufreq_freqs *freqs = data;
	if (val == CPUFREQ_PRECHANGE) {
		reg_bif_core_rw_sdram_timing timing =
		    REG_RD(bif_core, regi_bif_core, rw_sdram_timing);
		timing.cpd = (freqs->new == 200000 ? 0 : 1);

		if (freqs->new == 200000)
			for (i = 0; i < 50000; i++) ;
		REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing);
	}
	return 0;
}

module_init(cris_freq_init);
Commit	Line	Data
035e111f JN	1	#include <linux/init.h>
	2	#include <linux/module.h>
	3	#include <linux/cpufreq.h>
	4	#include <hwregs/reg_map.h>
556dcee7 JN	5	#include <arch/hwregs/reg_rdwr.h>
	6	#include <arch/hwregs/config_defs.h>
	7	#include <arch/hwregs/bif_core_defs.h>
035e111f JN	8
	9	static int
	10	cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
	11	void *data);
	12
	13	static struct notifier_block cris_sdram_freq_notifier_block = {
	14	.notifier_call = cris_sdram_freq_notifier
	15	};
	16
	17	static struct cpufreq_frequency_table cris_freq_table[] = {
	18	{0x01, 6000},
	19	{0x02, 200000},
	20	{0, CPUFREQ_TABLE_END},
	21	};
	22
	23	static unsigned int cris_freq_get_cpu_frequency(unsigned int cpu)
	24	{
	25	reg_config_rw_clk_ctrl clk_ctrl;
	26	clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
	27	return clk_ctrl.pll ? 200000 : 6000;
	28	}
	29
b43a7ffb VK	30	static void cris_freq_set_cpu_state(struct cpufreq_policy *policy,
b43a7ffb VK	31	unsigned int state)
035e111f	32	{
035e111f JN	33	struct cpufreq_freqs freqs;
	34	reg_config_rw_clk_ctrl clk_ctrl;
	35	clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
	36
b43a7ffb VK	37	freqs.old = cris_freq_get_cpu_frequency(policy->cpu);
b43a7ffb VK	38	freqs.new = cris_freq_table[state].frequency;
035e111f	39
b43a7ffb	40	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
035e111f JN	41
	42	local_irq_disable();
	43
	44	/* Even though we may be SMP they will share the same clock
	45	* so all settings are made on CPU0. */
	46	if (cris_freq_table[state].frequency == 200000)
	47	clk_ctrl.pll = 1;
	48	else
	49	clk_ctrl.pll = 0;
	50	REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl);
	51
	52	local_irq_enable();
	53
b43a7ffb	54	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
035e111f JN	55	};
	56
	57	static int cris_freq_verify(struct cpufreq_policy *policy)
	58	{
	59	return cpufreq_frequency_table_verify(policy, &cris_freq_table[0]);
	60	}
	61
	62	static int cris_freq_target(struct cpufreq_policy *policy,
	63	unsigned int target_freq, unsigned int relation)
	64	{
	65	unsigned int newstate = 0;
	66
	67	if (cpufreq_frequency_table_target
	68	(policy, cris_freq_table, target_freq, relation, &newstate))
	69	return -EINVAL;
	70
b43a7ffb	71	cris_freq_set_cpu_state(policy, newstate);
035e111f JN	72
	73	return 0;
	74	}
	75
	76	static int cris_freq_cpu_init(struct cpufreq_policy *policy)
	77	{
	78	int result;
	79
	80	/* cpuinfo and default policy values */
035e111f JN	81	policy->cpuinfo.transition_latency = 1000000; /* 1ms */
	82	policy->cur = cris_freq_get_cpu_frequency(0);
	83
	84	result = cpufreq_frequency_table_cpuinfo(policy, cris_freq_table);
	85	if (result)
	86	return (result);
	87
	88	cpufreq_frequency_table_get_attr(cris_freq_table, policy->cpu);
	89
	90	return 0;
	91	}
	92
	93	static int cris_freq_cpu_exit(struct cpufreq_policy *policy)
	94	{
	95	cpufreq_frequency_table_put_attr(policy->cpu);
	96	return 0;
	97	}
	98
	99	static struct freq_attr *cris_freq_attr[] = {
	100	&cpufreq_freq_attr_scaling_available_freqs,
	101	NULL,
	102	};
	103
	104	static struct cpufreq_driver cris_freq_driver = {
	105	.get = cris_freq_get_cpu_frequency,
	106	.verify = cris_freq_verify,
	107	.target = cris_freq_target,
	108	.init = cris_freq_cpu_init,
	109	.exit = cris_freq_cpu_exit,
	110	.name = "cris_freq",
035e111f JN	111	.attr = cris_freq_attr,
	112	};
	113
	114	static int __init cris_freq_init(void)
	115	{
	116	int ret;
	117	ret = cpufreq_register_driver(&cris_freq_driver);
	118	cpufreq_register_notifier(&cris_sdram_freq_notifier_block,
	119	CPUFREQ_TRANSITION_NOTIFIER);
	120	return ret;
	121	}
	122
	123	static int
	124	cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
	125	void *data)
	126	{
	127	int i;
	128	struct cpufreq_freqs *freqs = data;
	129	if (val == CPUFREQ_PRECHANGE) {
	130	reg_bif_core_rw_sdram_timing timing =
	131	REG_RD(bif_core, regi_bif_core, rw_sdram_timing);
	132	timing.cpd = (freqs->new == 200000 ? 0 : 1);
	133
	134	if (freqs->new == 200000)
	135	for (i = 0; i < 50000; i++) ;
	136	REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing);
	137	}
	138	return 0;
	139	}
	140
	141	module_init(cris_freq_init);