Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
32ee8c3e | 2 | * elanfreq: cpufreq driver for the AMD ELAN family |
1da177e4 LT |
3 | * |
4 | * (c) Copyright 2002 Robert Schwebel <r.schwebel@pengutronix.de> | |
5 | * | |
32ee8c3e | 6 | * Parts of this code are (c) Sven Geggus <sven@geggus.net> |
1da177e4 | 7 | * |
32ee8c3e | 8 | * All Rights Reserved. |
1da177e4 LT |
9 | * |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License | |
12 | * as published by the Free Software Foundation; either version | |
32ee8c3e | 13 | * 2 of the License, or (at your option) any later version. |
1da177e4 LT |
14 | * |
15 | * 2002-02-13: - initial revision for 2.4.18-pre9 by Robert Schwebel | |
16 | * | |
17 | */ | |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/init.h> | |
22 | ||
1da177e4 LT |
23 | #include <linux/delay.h> |
24 | #include <linux/cpufreq.h> | |
25 | ||
fa8031ae | 26 | #include <asm/cpu_device_id.h> |
1da177e4 | 27 | #include <asm/msr.h> |
18c6faa9 PC |
28 | #include <linux/timex.h> |
29 | #include <linux/io.h> | |
1da177e4 | 30 | |
32ee8c3e | 31 | #define REG_CSCIR 0x22 /* Chip Setup and Control Index Register */ |
1da177e4 LT |
32 | #define REG_CSCDR 0x23 /* Chip Setup and Control Data Register */ |
33 | ||
34 | /* Module parameter */ | |
35 | static int max_freq; | |
36 | ||
37 | struct s_elan_multiplier { | |
38 | int clock; /* frequency in kHz */ | |
39 | int val40h; /* PMU Force Mode register */ | |
40 | int val80h; /* CPU Clock Speed Register */ | |
41 | }; | |
42 | ||
43 | /* | |
32ee8c3e | 44 | * It is important that the frequencies |
1da177e4 LT |
45 | * are listed in ascending order here! |
46 | */ | |
460f5ef2 | 47 | static struct s_elan_multiplier elan_multiplier[] = { |
1da177e4 LT |
48 | {1000, 0x02, 0x18}, |
49 | {2000, 0x02, 0x10}, | |
50 | {4000, 0x02, 0x08}, | |
51 | {8000, 0x00, 0x00}, | |
52 | {16000, 0x00, 0x02}, | |
53 | {33000, 0x00, 0x04}, | |
54 | {66000, 0x01, 0x04}, | |
55 | {99000, 0x01, 0x05} | |
56 | }; | |
57 | ||
58 | static struct cpufreq_frequency_table elanfreq_table[] = { | |
59 | {0, 1000}, | |
60 | {1, 2000}, | |
61 | {2, 4000}, | |
62 | {3, 8000}, | |
63 | {4, 16000}, | |
64 | {5, 33000}, | |
65 | {6, 66000}, | |
66 | {7, 99000}, | |
67 | {0, CPUFREQ_TABLE_END}, | |
68 | }; | |
69 | ||
70 | ||
71 | /** | |
72 | * elanfreq_get_cpu_frequency: determine current cpu speed | |
73 | * | |
74 | * Finds out at which frequency the CPU of the Elan SOC runs | |
32ee8c3e | 75 | * at the moment. Frequencies from 1 to 33 MHz are generated |
1da177e4 | 76 | * the normal way, 66 and 99 MHz are called "Hyperspeed Mode" |
32ee8c3e | 77 | * and have the rest of the chip running with 33 MHz. |
1da177e4 LT |
78 | */ |
79 | ||
80 | static unsigned int elanfreq_get_cpu_frequency(unsigned int cpu) | |
81 | { | |
32ee8c3e DJ |
82 | u8 clockspeed_reg; /* Clock Speed Register */ |
83 | ||
1da177e4 | 84 | local_irq_disable(); |
18c6faa9 | 85 | outb_p(0x80, REG_CSCIR); |
32ee8c3e | 86 | clockspeed_reg = inb_p(REG_CSCDR); |
1da177e4 LT |
87 | local_irq_enable(); |
88 | ||
32ee8c3e DJ |
89 | if ((clockspeed_reg & 0xE0) == 0xE0) |
90 | return 0; | |
1da177e4 | 91 | |
32ee8c3e DJ |
92 | /* Are we in CPU clock multiplied mode (66/99 MHz)? */ |
93 | if ((clockspeed_reg & 0xE0) == 0xC0) { | |
94 | if ((clockspeed_reg & 0x01) == 0) | |
1da177e4 | 95 | return 66000; |
32ee8c3e DJ |
96 | else |
97 | return 99000; | |
98 | } | |
1da177e4 LT |
99 | |
100 | /* 33 MHz is not 32 MHz... */ | |
18c6faa9 | 101 | if ((clockspeed_reg & 0xE0) == 0xA0) |
1da177e4 LT |
102 | return 33000; |
103 | ||
18c6faa9 | 104 | return (1<<((clockspeed_reg & 0xE0) >> 5)) * 1000; |
1da177e4 LT |
105 | } |
106 | ||
107 | ||
108 | /** | |
32ee8c3e DJ |
109 | * elanfreq_set_cpu_frequency: Change the CPU core frequency |
110 | * @cpu: cpu number | |
1da177e4 LT |
111 | * @freq: frequency in kHz |
112 | * | |
32ee8c3e | 113 | * This function takes a frequency value and changes the CPU frequency |
1da177e4 LT |
114 | * according to this. Note that the frequency has to be checked by |
115 | * elanfreq_validatespeed() for correctness! | |
32ee8c3e DJ |
116 | * |
117 | * There is no return value. | |
1da177e4 LT |
118 | */ |
119 | ||
18c6faa9 | 120 | static void elanfreq_set_cpu_state(unsigned int state) |
32ee8c3e | 121 | { |
1da177e4 LT |
122 | struct cpufreq_freqs freqs; |
123 | ||
124 | freqs.old = elanfreq_get_cpu_frequency(0); | |
125 | freqs.new = elan_multiplier[state].clock; | |
126 | freqs.cpu = 0; /* elanfreq.c is UP only driver */ | |
32ee8c3e | 127 | |
1da177e4 LT |
128 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); |
129 | ||
32ee8c3e DJ |
130 | printk(KERN_INFO "elanfreq: attempting to set frequency to %i kHz\n", |
131 | elan_multiplier[state].clock); | |
1da177e4 LT |
132 | |
133 | ||
32ee8c3e DJ |
134 | /* |
135 | * Access to the Elan's internal registers is indexed via | |
136 | * 0x22: Chip Setup & Control Register Index Register (CSCI) | |
137 | * 0x23: Chip Setup & Control Register Data Register (CSCD) | |
1da177e4 LT |
138 | * |
139 | */ | |
140 | ||
32ee8c3e DJ |
141 | /* |
142 | * 0x40 is the Power Management Unit's Force Mode Register. | |
1da177e4 LT |
143 | * Bit 6 enables Hyperspeed Mode (66/100 MHz core frequency) |
144 | */ | |
145 | ||
146 | local_irq_disable(); | |
18c6faa9 PC |
147 | outb_p(0x40, REG_CSCIR); /* Disable hyperspeed mode */ |
148 | outb_p(0x00, REG_CSCDR); | |
1da177e4 LT |
149 | local_irq_enable(); /* wait till internal pipelines and */ |
150 | udelay(1000); /* buffers have cleaned up */ | |
151 | ||
152 | local_irq_disable(); | |
153 | ||
154 | /* now, set the CPU clock speed register (0x80) */ | |
18c6faa9 PC |
155 | outb_p(0x80, REG_CSCIR); |
156 | outb_p(elan_multiplier[state].val80h, REG_CSCDR); | |
1da177e4 LT |
157 | |
158 | /* now, the hyperspeed bit in PMU Force Mode Register (0x40) */ | |
18c6faa9 PC |
159 | outb_p(0x40, REG_CSCIR); |
160 | outb_p(elan_multiplier[state].val40h, REG_CSCDR); | |
1da177e4 LT |
161 | udelay(10000); |
162 | local_irq_enable(); | |
163 | ||
164 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
165 | }; | |
166 | ||
167 | ||
168 | /** | |
169 | * elanfreq_validatespeed: test if frequency range is valid | |
32ee8c3e | 170 | * @policy: the policy to validate |
1da177e4 | 171 | * |
32ee8c3e DJ |
172 | * This function checks if a given frequency range in kHz is valid |
173 | * for the hardware supported by the driver. | |
1da177e4 LT |
174 | */ |
175 | ||
18c6faa9 | 176 | static int elanfreq_verify(struct cpufreq_policy *policy) |
1da177e4 LT |
177 | { |
178 | return cpufreq_frequency_table_verify(policy, &elanfreq_table[0]); | |
179 | } | |
180 | ||
18c6faa9 | 181 | static int elanfreq_target(struct cpufreq_policy *policy, |
32ee8c3e | 182 | unsigned int target_freq, |
1da177e4 LT |
183 | unsigned int relation) |
184 | { | |
32ee8c3e | 185 | unsigned int newstate = 0; |
1da177e4 | 186 | |
04cd1a99 DJ |
187 | if (cpufreq_frequency_table_target(policy, &elanfreq_table[0], |
188 | target_freq, relation, &newstate)) | |
1da177e4 LT |
189 | return -EINVAL; |
190 | ||
191 | elanfreq_set_cpu_state(newstate); | |
192 | ||
193 | return 0; | |
194 | } | |
195 | ||
196 | ||
197 | /* | |
198 | * Module init and exit code | |
199 | */ | |
200 | ||
201 | static int elanfreq_cpu_init(struct cpufreq_policy *policy) | |
202 | { | |
92cb7612 | 203 | struct cpuinfo_x86 *c = &cpu_data(0); |
1da177e4 LT |
204 | unsigned int i; |
205 | int result; | |
206 | ||
207 | /* capability check */ | |
208 | if ((c->x86_vendor != X86_VENDOR_AMD) || | |
18c6faa9 | 209 | (c->x86 != 4) || (c->x86_model != 10)) |
1da177e4 LT |
210 | return -ENODEV; |
211 | ||
212 | /* max freq */ | |
213 | if (!max_freq) | |
214 | max_freq = elanfreq_get_cpu_frequency(0); | |
215 | ||
216 | /* table init */ | |
18c6faa9 | 217 | for (i = 0; (elanfreq_table[i].frequency != CPUFREQ_TABLE_END); i++) { |
1da177e4 LT |
218 | if (elanfreq_table[i].frequency > max_freq) |
219 | elanfreq_table[i].frequency = CPUFREQ_ENTRY_INVALID; | |
220 | } | |
221 | ||
222 | /* cpuinfo and default policy values */ | |
1da177e4 LT |
223 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; |
224 | policy->cur = elanfreq_get_cpu_frequency(0); | |
225 | ||
226 | result = cpufreq_frequency_table_cpuinfo(policy, elanfreq_table); | |
227 | if (result) | |
18c6faa9 | 228 | return result; |
1da177e4 | 229 | |
32ee8c3e | 230 | cpufreq_frequency_table_get_attr(elanfreq_table, policy->cpu); |
1da177e4 LT |
231 | return 0; |
232 | } | |
233 | ||
234 | ||
235 | static int elanfreq_cpu_exit(struct cpufreq_policy *policy) | |
236 | { | |
237 | cpufreq_frequency_table_put_attr(policy->cpu); | |
238 | return 0; | |
239 | } | |
240 | ||
241 | ||
242 | #ifndef MODULE | |
243 | /** | |
244 | * elanfreq_setup - elanfreq command line parameter parsing | |
245 | * | |
246 | * elanfreq command line parameter. Use: | |
247 | * elanfreq=66000 | |
248 | * to set the maximum CPU frequency to 66 MHz. Note that in | |
249 | * case you do not give this boot parameter, the maximum | |
250 | * frequency will fall back to _current_ CPU frequency which | |
251 | * might be lower. If you build this as a module, use the | |
252 | * max_freq module parameter instead. | |
253 | */ | |
254 | static int __init elanfreq_setup(char *str) | |
255 | { | |
256 | max_freq = simple_strtoul(str, &str, 0); | |
257 | printk(KERN_WARNING "You're using the deprecated elanfreq command line option. Use elanfreq.max_freq instead, please!\n"); | |
258 | return 1; | |
259 | } | |
260 | __setup("elanfreq=", elanfreq_setup); | |
261 | #endif | |
262 | ||
263 | ||
18c6faa9 | 264 | static struct freq_attr *elanfreq_attr[] = { |
1da177e4 LT |
265 | &cpufreq_freq_attr_scaling_available_freqs, |
266 | NULL, | |
267 | }; | |
268 | ||
269 | ||
221dee28 | 270 | static struct cpufreq_driver elanfreq_driver = { |
32ee8c3e DJ |
271 | .get = elanfreq_get_cpu_frequency, |
272 | .verify = elanfreq_verify, | |
273 | .target = elanfreq_target, | |
1da177e4 LT |
274 | .init = elanfreq_cpu_init, |
275 | .exit = elanfreq_cpu_exit, | |
276 | .name = "elanfreq", | |
277 | .owner = THIS_MODULE, | |
278 | .attr = elanfreq_attr, | |
279 | }; | |
280 | ||
fa8031ae AK |
281 | static const struct x86_cpu_id elan_id[] = { |
282 | { X86_VENDOR_AMD, 4, 10, }, | |
283 | {} | |
284 | }; | |
285 | MODULE_DEVICE_TABLE(x86cpu, elan_id); | |
1da177e4 | 286 | |
32ee8c3e DJ |
287 | static int __init elanfreq_init(void) |
288 | { | |
fa8031ae | 289 | if (!x86_match_cpu(elan_id)) |
18c6faa9 | 290 | return -ENODEV; |
1da177e4 LT |
291 | return cpufreq_register_driver(&elanfreq_driver); |
292 | } | |
293 | ||
294 | ||
32ee8c3e | 295 | static void __exit elanfreq_exit(void) |
1da177e4 LT |
296 | { |
297 | cpufreq_unregister_driver(&elanfreq_driver); | |
298 | } | |
299 | ||
300 | ||
18c6faa9 | 301 | module_param(max_freq, int, 0444); |
1da177e4 LT |
302 | |
303 | MODULE_LICENSE("GPL"); | |
04cd1a99 DJ |
304 | MODULE_AUTHOR("Robert Schwebel <r.schwebel@pengutronix.de>, " |
305 | "Sven Geggus <sven@geggus.net>"); | |
1da177e4 LT |
306 | MODULE_DESCRIPTION("cpufreq driver for AMD's Elan CPUs"); |
307 | ||
308 | module_init(elanfreq_init); | |
309 | module_exit(elanfreq_exit); |