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a125a17f JL |
1 | /* |
2 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com | |
4 | * | |
5 | * EXYNOS - CPU frequency scaling support for EXYNOS series | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
a125a17f JL |
12 | #include <linux/kernel.h> |
13 | #include <linux/err.h> | |
14 | #include <linux/clk.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/regulator/consumer.h> | |
18 | #include <linux/cpufreq.h> | |
d568b6f7 | 19 | #include <linux/platform_device.h> |
be1f7c8d | 20 | #include <linux/of.h> |
a125a17f | 21 | |
c4aaa295 KK |
22 | #include "exynos-cpufreq.h" |
23 | ||
a125a17f | 24 | static struct exynos_dvfs_info *exynos_info; |
a125a17f | 25 | static struct regulator *arm_regulator; |
a125a17f | 26 | static unsigned int locking_frequency; |
a125a17f | 27 | |
0e0e425f JC |
28 | static int exynos_cpufreq_get_index(unsigned int freq) |
29 | { | |
30 | struct cpufreq_frequency_table *freq_table = exynos_info->freq_table; | |
041526f9 | 31 | struct cpufreq_frequency_table *pos; |
0e0e425f | 32 | |
041526f9 SK |
33 | cpufreq_for_each_entry(pos, freq_table) |
34 | if (pos->frequency == freq) | |
0e0e425f JC |
35 | break; |
36 | ||
041526f9 | 37 | if (pos->frequency == CPUFREQ_TABLE_END) |
0e0e425f JC |
38 | return -EINVAL; |
39 | ||
041526f9 | 40 | return pos - freq_table; |
0e0e425f JC |
41 | } |
42 | ||
43 | static int exynos_cpufreq_scale(unsigned int target_freq) | |
a125a17f | 44 | { |
a125a17f JL |
45 | struct cpufreq_frequency_table *freq_table = exynos_info->freq_table; |
46 | unsigned int *volt_table = exynos_info->volt_table; | |
0e0e425f JC |
47 | struct cpufreq_policy *policy = cpufreq_cpu_get(0); |
48 | unsigned int arm_volt, safe_arm_volt = 0; | |
a125a17f | 49 | unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz; |
e5eaa445 | 50 | struct device *dev = exynos_info->dev; |
d4019f0a | 51 | unsigned int old_freq; |
d271d077 | 52 | int index, old_index; |
0e0e425f | 53 | int ret = 0; |
a125a17f | 54 | |
d4019f0a | 55 | old_freq = policy->cur; |
a125a17f | 56 | |
53df1ad5 JL |
57 | /* |
58 | * The policy max have been changed so that we cannot get proper | |
59 | * old_index with cpufreq_frequency_table_target(). Thus, ignore | |
0585123e | 60 | * policy and get the index from the raw frequency table. |
53df1ad5 | 61 | */ |
d4019f0a | 62 | old_index = exynos_cpufreq_get_index(old_freq); |
0e0e425f JC |
63 | if (old_index < 0) { |
64 | ret = old_index; | |
a125a17f JL |
65 | goto out; |
66 | } | |
67 | ||
0e0e425f JC |
68 | index = exynos_cpufreq_get_index(target_freq); |
69 | if (index < 0) { | |
70 | ret = index; | |
a125a17f JL |
71 | goto out; |
72 | } | |
73 | ||
a125a17f JL |
74 | /* |
75 | * ARM clock source will be changed APLL to MPLL temporary | |
76 | * To support this level, need to control regulator for | |
77 | * required voltage level | |
78 | */ | |
79 | if (exynos_info->need_apll_change != NULL) { | |
80 | if (exynos_info->need_apll_change(old_index, index) && | |
81 | (freq_table[index].frequency < mpll_freq_khz) && | |
82 | (freq_table[old_index].frequency < mpll_freq_khz)) | |
83 | safe_arm_volt = volt_table[exynos_info->pll_safe_idx]; | |
84 | } | |
85 | arm_volt = volt_table[index]; | |
86 | ||
a125a17f | 87 | /* When the new frequency is higher than current frequency */ |
d4019f0a | 88 | if ((target_freq > old_freq) && !safe_arm_volt) { |
a125a17f | 89 | /* Firstly, voltage up to increase frequency */ |
0e0e425f JC |
90 | ret = regulator_set_voltage(arm_regulator, arm_volt, arm_volt); |
91 | if (ret) { | |
e5eaa445 CC |
92 | dev_err(dev, "failed to set cpu voltage to %d\n", |
93 | arm_volt); | |
d4019f0a | 94 | return ret; |
0e0e425f | 95 | } |
a125a17f JL |
96 | } |
97 | ||
0e0e425f JC |
98 | if (safe_arm_volt) { |
99 | ret = regulator_set_voltage(arm_regulator, safe_arm_volt, | |
a125a17f | 100 | safe_arm_volt); |
0e0e425f | 101 | if (ret) { |
e5eaa445 CC |
102 | dev_err(dev, "failed to set cpu voltage to %d\n", |
103 | safe_arm_volt); | |
d4019f0a | 104 | return ret; |
0e0e425f JC |
105 | } |
106 | } | |
857d90f7 JC |
107 | |
108 | exynos_info->set_freq(old_index, index); | |
a125a17f | 109 | |
a125a17f | 110 | /* When the new frequency is lower than current frequency */ |
d4019f0a VK |
111 | if ((target_freq < old_freq) || |
112 | ((target_freq > old_freq) && safe_arm_volt)) { | |
a125a17f | 113 | /* down the voltage after frequency change */ |
006454ae | 114 | ret = regulator_set_voltage(arm_regulator, arm_volt, |
a125a17f | 115 | arm_volt); |
0e0e425f | 116 | if (ret) { |
e5eaa445 CC |
117 | dev_err(dev, "failed to set cpu voltage to %d\n", |
118 | arm_volt); | |
0e0e425f JC |
119 | goto out; |
120 | } | |
a125a17f JL |
121 | } |
122 | ||
0e0e425f | 123 | out: |
0e0e425f JC |
124 | cpufreq_cpu_put(policy); |
125 | ||
126 | return ret; | |
127 | } | |
128 | ||
9c0ebcf7 | 129 | static int exynos_target(struct cpufreq_policy *policy, unsigned int index) |
0e0e425f | 130 | { |
d248bb89 | 131 | return exynos_cpufreq_scale(exynos_info->freq_table[index].frequency); |
a125a17f JL |
132 | } |
133 | ||
a125a17f JL |
134 | static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy) |
135 | { | |
652ed95d | 136 | policy->clk = exynos_info->cpu_clk; |
d248bb89 | 137 | policy->suspend_freq = locking_frequency; |
b249abae | 138 | return cpufreq_generic_init(policy, exynos_info->freq_table, 100000); |
a125a17f JL |
139 | } |
140 | ||
141 | static struct cpufreq_driver exynos_driver = { | |
ae6b4271 | 142 | .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
eea6181e | 143 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 144 | .target_index = exynos_target, |
652ed95d | 145 | .get = cpufreq_generic_get, |
a125a17f JL |
146 | .init = exynos_cpufreq_cpu_init, |
147 | .name = "exynos_cpufreq", | |
eea6181e | 148 | .attr = cpufreq_generic_attr, |
c683c2c9 LM |
149 | #ifdef CONFIG_ARM_EXYNOS_CPU_FREQ_BOOST_SW |
150 | .boost_supported = true, | |
151 | #endif | |
a125a17f | 152 | #ifdef CONFIG_PM |
d248bb89 | 153 | .suspend = cpufreq_generic_suspend, |
a125a17f JL |
154 | #endif |
155 | }; | |
156 | ||
d568b6f7 | 157 | static int exynos_cpufreq_probe(struct platform_device *pdev) |
a125a17f JL |
158 | { |
159 | int ret = -EINVAL; | |
160 | ||
d5b73cd8 | 161 | exynos_info = kzalloc(sizeof(*exynos_info), GFP_KERNEL); |
a125a17f JL |
162 | if (!exynos_info) |
163 | return -ENOMEM; | |
164 | ||
e5eaa445 CC |
165 | exynos_info->dev = &pdev->dev; |
166 | ||
be1f7c8d JC |
167 | if (of_machine_is_compatible("samsung,exynos4210")) { |
168 | exynos_info->type = EXYNOS_SOC_4210; | |
a125a17f | 169 | ret = exynos4210_cpufreq_init(exynos_info); |
be1f7c8d JC |
170 | } else if (of_machine_is_compatible("samsung,exynos4212")) { |
171 | exynos_info->type = EXYNOS_SOC_4212; | |
a35c5051 | 172 | ret = exynos4x12_cpufreq_init(exynos_info); |
be1f7c8d JC |
173 | } else if (of_machine_is_compatible("samsung,exynos4412")) { |
174 | exynos_info->type = EXYNOS_SOC_4412; | |
175 | ret = exynos4x12_cpufreq_init(exynos_info); | |
176 | } else if (of_machine_is_compatible("samsung,exynos5250")) { | |
177 | exynos_info->type = EXYNOS_SOC_5250; | |
562a6cbe | 178 | ret = exynos5250_cpufreq_init(exynos_info); |
be1f7c8d JC |
179 | } else { |
180 | pr_err("%s: Unknown SoC type\n", __func__); | |
181 | return -ENODEV; | |
182 | } | |
a125a17f JL |
183 | |
184 | if (ret) | |
185 | goto err_vdd_arm; | |
186 | ||
187 | if (exynos_info->set_freq == NULL) { | |
e5eaa445 | 188 | dev_err(&pdev->dev, "No set_freq function (ERR)\n"); |
a125a17f JL |
189 | goto err_vdd_arm; |
190 | } | |
191 | ||
192 | arm_regulator = regulator_get(NULL, "vdd_arm"); | |
193 | if (IS_ERR(arm_regulator)) { | |
e5eaa445 | 194 | dev_err(&pdev->dev, "failed to get resource vdd_arm\n"); |
a125a17f JL |
195 | goto err_vdd_arm; |
196 | } | |
197 | ||
d248bb89 | 198 | /* Done here as we want to capture boot frequency */ |
652ed95d | 199 | locking_frequency = clk_get_rate(exynos_info->cpu_clk) / 1000; |
6e45eb12 | 200 | |
d248bb89 VK |
201 | if (!cpufreq_register_driver(&exynos_driver)) |
202 | return 0; | |
a125a17f | 203 | |
e5eaa445 | 204 | dev_err(&pdev->dev, "failed to register cpufreq driver\n"); |
184cddd1 | 205 | regulator_put(arm_regulator); |
a125a17f JL |
206 | err_vdd_arm: |
207 | kfree(exynos_info); | |
a125a17f JL |
208 | return -EINVAL; |
209 | } | |
d568b6f7 LM |
210 | |
211 | static struct platform_driver exynos_cpufreq_platdrv = { | |
212 | .driver = { | |
213 | .name = "exynos-cpufreq", | |
214 | .owner = THIS_MODULE, | |
215 | }, | |
216 | .probe = exynos_cpufreq_probe, | |
217 | }; | |
218 | module_platform_driver(exynos_cpufreq_platdrv); |