Merge branch 'parisc-4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/deller...
[deliverable/linux.git] / drivers / cpufreq / exynos-cpufreq.c
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1/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS - CPU frequency scaling support for EXYNOS series
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
a125a17f 12#include <linux/kernel.h>
743492cc 13#include <linux/module.h>
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14#include <linux/err.h>
15#include <linux/clk.h>
16#include <linux/io.h>
17#include <linux/slab.h>
18#include <linux/regulator/consumer.h>
19#include <linux/cpufreq.h>
d568b6f7 20#include <linux/platform_device.h>
be1f7c8d 21#include <linux/of.h>
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22#include <linux/cpu_cooling.h>
23#include <linux/cpu.h>
a125a17f 24
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25#include "exynos-cpufreq.h"
26
a125a17f 27static struct exynos_dvfs_info *exynos_info;
e725d26c 28static struct thermal_cooling_device *cdev;
a125a17f 29static struct regulator *arm_regulator;
a125a17f 30static unsigned int locking_frequency;
a125a17f 31
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32static int exynos_cpufreq_get_index(unsigned int freq)
33{
34 struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
041526f9 35 struct cpufreq_frequency_table *pos;
0e0e425f 36
041526f9
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37 cpufreq_for_each_entry(pos, freq_table)
38 if (pos->frequency == freq)
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39 break;
40
041526f9 41 if (pos->frequency == CPUFREQ_TABLE_END)
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42 return -EINVAL;
43
041526f9 44 return pos - freq_table;
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45}
46
47static int exynos_cpufreq_scale(unsigned int target_freq)
a125a17f 48{
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49 struct cpufreq_frequency_table *freq_table = exynos_info->freq_table;
50 unsigned int *volt_table = exynos_info->volt_table;
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51 struct cpufreq_policy *policy = cpufreq_cpu_get(0);
52 unsigned int arm_volt, safe_arm_volt = 0;
a125a17f 53 unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz;
e5eaa445 54 struct device *dev = exynos_info->dev;
d4019f0a 55 unsigned int old_freq;
d271d077 56 int index, old_index;
0e0e425f 57 int ret = 0;
a125a17f 58
d4019f0a 59 old_freq = policy->cur;
a125a17f 60
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61 /*
62 * The policy max have been changed so that we cannot get proper
63 * old_index with cpufreq_frequency_table_target(). Thus, ignore
0585123e 64 * policy and get the index from the raw frequency table.
53df1ad5 65 */
d4019f0a 66 old_index = exynos_cpufreq_get_index(old_freq);
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JC
67 if (old_index < 0) {
68 ret = old_index;
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69 goto out;
70 }
71
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72 index = exynos_cpufreq_get_index(target_freq);
73 if (index < 0) {
74 ret = index;
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75 goto out;
76 }
77
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78 /*
79 * ARM clock source will be changed APLL to MPLL temporary
80 * To support this level, need to control regulator for
81 * required voltage level
82 */
83 if (exynos_info->need_apll_change != NULL) {
84 if (exynos_info->need_apll_change(old_index, index) &&
85 (freq_table[index].frequency < mpll_freq_khz) &&
86 (freq_table[old_index].frequency < mpll_freq_khz))
87 safe_arm_volt = volt_table[exynos_info->pll_safe_idx];
88 }
89 arm_volt = volt_table[index];
90
a125a17f 91 /* When the new frequency is higher than current frequency */
d4019f0a 92 if ((target_freq > old_freq) && !safe_arm_volt) {
a125a17f 93 /* Firstly, voltage up to increase frequency */
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94 ret = regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
95 if (ret) {
e5eaa445
CC
96 dev_err(dev, "failed to set cpu voltage to %d\n",
97 arm_volt);
d4019f0a 98 return ret;
0e0e425f 99 }
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100 }
101
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102 if (safe_arm_volt) {
103 ret = regulator_set_voltage(arm_regulator, safe_arm_volt,
a125a17f 104 safe_arm_volt);
0e0e425f 105 if (ret) {
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CC
106 dev_err(dev, "failed to set cpu voltage to %d\n",
107 safe_arm_volt);
d4019f0a 108 return ret;
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109 }
110 }
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111
112 exynos_info->set_freq(old_index, index);
a125a17f 113
a125a17f 114 /* When the new frequency is lower than current frequency */
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VK
115 if ((target_freq < old_freq) ||
116 ((target_freq > old_freq) && safe_arm_volt)) {
a125a17f 117 /* down the voltage after frequency change */
006454ae 118 ret = regulator_set_voltage(arm_regulator, arm_volt,
a125a17f 119 arm_volt);
0e0e425f 120 if (ret) {
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121 dev_err(dev, "failed to set cpu voltage to %d\n",
122 arm_volt);
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123 goto out;
124 }
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125 }
126
0e0e425f 127out:
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128 cpufreq_cpu_put(policy);
129
130 return ret;
131}
132
9c0ebcf7 133static int exynos_target(struct cpufreq_policy *policy, unsigned int index)
0e0e425f 134{
d248bb89 135 return exynos_cpufreq_scale(exynos_info->freq_table[index].frequency);
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136}
137
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138static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy)
139{
652ed95d 140 policy->clk = exynos_info->cpu_clk;
d248bb89 141 policy->suspend_freq = locking_frequency;
b249abae 142 return cpufreq_generic_init(policy, exynos_info->freq_table, 100000);
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143}
144
145static struct cpufreq_driver exynos_driver = {
ae6b4271 146 .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
eea6181e 147 .verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7 148 .target_index = exynos_target,
652ed95d 149 .get = cpufreq_generic_get,
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150 .init = exynos_cpufreq_cpu_init,
151 .name = "exynos_cpufreq",
eea6181e 152 .attr = cpufreq_generic_attr,
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153#ifdef CONFIG_ARM_EXYNOS_CPU_FREQ_BOOST_SW
154 .boost_supported = true,
155#endif
a125a17f 156#ifdef CONFIG_PM
d248bb89 157 .suspend = cpufreq_generic_suspend,
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158#endif
159};
160
d568b6f7 161static int exynos_cpufreq_probe(struct platform_device *pdev)
a125a17f 162{
0fc83929 163 struct device_node *cpu0;
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164 int ret = -EINVAL;
165
d5b73cd8 166 exynos_info = kzalloc(sizeof(*exynos_info), GFP_KERNEL);
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167 if (!exynos_info)
168 return -ENOMEM;
169
e5eaa445
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170 exynos_info->dev = &pdev->dev;
171
8eb92ab6 172 if (of_machine_is_compatible("samsung,exynos4212")) {
be1f7c8d 173 exynos_info->type = EXYNOS_SOC_4212;
a35c5051 174 ret = exynos4x12_cpufreq_init(exynos_info);
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175 } else if (of_machine_is_compatible("samsung,exynos4412")) {
176 exynos_info->type = EXYNOS_SOC_4412;
177 ret = exynos4x12_cpufreq_init(exynos_info);
178 } else if (of_machine_is_compatible("samsung,exynos5250")) {
179 exynos_info->type = EXYNOS_SOC_5250;
562a6cbe 180 ret = exynos5250_cpufreq_init(exynos_info);
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181 } else {
182 pr_err("%s: Unknown SoC type\n", __func__);
183 return -ENODEV;
184 }
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185
186 if (ret)
187 goto err_vdd_arm;
188
189 if (exynos_info->set_freq == NULL) {
e5eaa445 190 dev_err(&pdev->dev, "No set_freq function (ERR)\n");
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191 goto err_vdd_arm;
192 }
193
194 arm_regulator = regulator_get(NULL, "vdd_arm");
195 if (IS_ERR(arm_regulator)) {
e5eaa445 196 dev_err(&pdev->dev, "failed to get resource vdd_arm\n");
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197 goto err_vdd_arm;
198 }
199
d248bb89 200 /* Done here as we want to capture boot frequency */
652ed95d 201 locking_frequency = clk_get_rate(exynos_info->cpu_clk) / 1000;
6e45eb12 202
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203 ret = cpufreq_register_driver(&exynos_driver);
204 if (ret)
205 goto err_cpufreq_reg;
206
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207 cpu0 = of_get_cpu_node(0, NULL);
208 if (!cpu0) {
209 pr_err("failed to find cpu0 node\n");
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210 return 0;
211 }
212
0fc83929
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213 if (of_find_property(cpu0, "#cooling-cells", NULL)) {
214 cdev = of_cpufreq_cooling_register(cpu0,
e725d26c
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215 cpu_present_mask);
216 if (IS_ERR(cdev))
217 pr_err("running cpufreq without cooling device: %ld\n",
218 PTR_ERR(cdev));
219 }
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220
221 return 0;
a125a17f 222
e725d26c 223err_cpufreq_reg:
e5eaa445 224 dev_err(&pdev->dev, "failed to register cpufreq driver\n");
184cddd1 225 regulator_put(arm_regulator);
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226err_vdd_arm:
227 kfree(exynos_info);
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228 return -EINVAL;
229}
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230
231static struct platform_driver exynos_cpufreq_platdrv = {
232 .driver = {
233 .name = "exynos-cpufreq",
d568b6f7
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234 },
235 .probe = exynos_cpufreq_probe,
236};
237module_platform_driver(exynos_cpufreq_platdrv);
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