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a125a17f JL |
1 | /* |
2 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com | |
4 | * | |
5 | * EXYNOS - CPU frequency scaling support for EXYNOS series | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
a125a17f JL |
12 | #include <linux/kernel.h> |
13 | #include <linux/err.h> | |
14 | #include <linux/clk.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/regulator/consumer.h> | |
18 | #include <linux/cpufreq.h> | |
19 | #include <linux/suspend.h> | |
d568b6f7 | 20 | #include <linux/platform_device.h> |
a125a17f | 21 | |
6c523c61 | 22 | #include <plat/cpu.h> |
a125a17f | 23 | |
c4aaa295 KK |
24 | #include "exynos-cpufreq.h" |
25 | ||
a125a17f JL |
26 | static struct exynos_dvfs_info *exynos_info; |
27 | ||
28 | static struct regulator *arm_regulator; | |
a125a17f JL |
29 | |
30 | static unsigned int locking_frequency; | |
31 | static bool frequency_locked; | |
32 | static DEFINE_MUTEX(cpufreq_lock); | |
33 | ||
0e0e425f JC |
34 | static int exynos_cpufreq_get_index(unsigned int freq) |
35 | { | |
36 | struct cpufreq_frequency_table *freq_table = exynos_info->freq_table; | |
37 | int index; | |
38 | ||
39 | for (index = 0; | |
40 | freq_table[index].frequency != CPUFREQ_TABLE_END; index++) | |
41 | if (freq_table[index].frequency == freq) | |
42 | break; | |
43 | ||
44 | if (freq_table[index].frequency == CPUFREQ_TABLE_END) | |
45 | return -EINVAL; | |
46 | ||
47 | return index; | |
48 | } | |
49 | ||
50 | static int exynos_cpufreq_scale(unsigned int target_freq) | |
a125a17f | 51 | { |
a125a17f JL |
52 | struct cpufreq_frequency_table *freq_table = exynos_info->freq_table; |
53 | unsigned int *volt_table = exynos_info->volt_table; | |
0e0e425f JC |
54 | struct cpufreq_policy *policy = cpufreq_cpu_get(0); |
55 | unsigned int arm_volt, safe_arm_volt = 0; | |
a125a17f | 56 | unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz; |
d4019f0a | 57 | unsigned int old_freq; |
d271d077 | 58 | int index, old_index; |
0e0e425f | 59 | int ret = 0; |
a125a17f | 60 | |
d4019f0a | 61 | old_freq = policy->cur; |
a125a17f | 62 | |
53df1ad5 JL |
63 | /* |
64 | * The policy max have been changed so that we cannot get proper | |
65 | * old_index with cpufreq_frequency_table_target(). Thus, ignore | |
0585123e | 66 | * policy and get the index from the raw frequency table. |
53df1ad5 | 67 | */ |
d4019f0a | 68 | old_index = exynos_cpufreq_get_index(old_freq); |
0e0e425f JC |
69 | if (old_index < 0) { |
70 | ret = old_index; | |
a125a17f JL |
71 | goto out; |
72 | } | |
73 | ||
0e0e425f JC |
74 | index = exynos_cpufreq_get_index(target_freq); |
75 | if (index < 0) { | |
76 | ret = index; | |
a125a17f JL |
77 | goto out; |
78 | } | |
79 | ||
a125a17f JL |
80 | /* |
81 | * ARM clock source will be changed APLL to MPLL temporary | |
82 | * To support this level, need to control regulator for | |
83 | * required voltage level | |
84 | */ | |
85 | if (exynos_info->need_apll_change != NULL) { | |
86 | if (exynos_info->need_apll_change(old_index, index) && | |
87 | (freq_table[index].frequency < mpll_freq_khz) && | |
88 | (freq_table[old_index].frequency < mpll_freq_khz)) | |
89 | safe_arm_volt = volt_table[exynos_info->pll_safe_idx]; | |
90 | } | |
91 | arm_volt = volt_table[index]; | |
92 | ||
a125a17f | 93 | /* When the new frequency is higher than current frequency */ |
d4019f0a | 94 | if ((target_freq > old_freq) && !safe_arm_volt) { |
a125a17f | 95 | /* Firstly, voltage up to increase frequency */ |
0e0e425f JC |
96 | ret = regulator_set_voltage(arm_regulator, arm_volt, arm_volt); |
97 | if (ret) { | |
98 | pr_err("%s: failed to set cpu voltage to %d\n", | |
99 | __func__, arm_volt); | |
d4019f0a | 100 | return ret; |
0e0e425f | 101 | } |
a125a17f JL |
102 | } |
103 | ||
0e0e425f JC |
104 | if (safe_arm_volt) { |
105 | ret = regulator_set_voltage(arm_regulator, safe_arm_volt, | |
a125a17f | 106 | safe_arm_volt); |
0e0e425f JC |
107 | if (ret) { |
108 | pr_err("%s: failed to set cpu voltage to %d\n", | |
109 | __func__, safe_arm_volt); | |
d4019f0a | 110 | return ret; |
0e0e425f JC |
111 | } |
112 | } | |
857d90f7 JC |
113 | |
114 | exynos_info->set_freq(old_index, index); | |
a125a17f | 115 | |
a125a17f | 116 | /* When the new frequency is lower than current frequency */ |
d4019f0a VK |
117 | if ((target_freq < old_freq) || |
118 | ((target_freq > old_freq) && safe_arm_volt)) { | |
a125a17f | 119 | /* down the voltage after frequency change */ |
006454ae | 120 | ret = regulator_set_voltage(arm_regulator, arm_volt, |
a125a17f | 121 | arm_volt); |
0e0e425f JC |
122 | if (ret) { |
123 | pr_err("%s: failed to set cpu voltage to %d\n", | |
124 | __func__, arm_volt); | |
125 | goto out; | |
126 | } | |
a125a17f JL |
127 | } |
128 | ||
0e0e425f | 129 | out: |
0e0e425f JC |
130 | cpufreq_cpu_put(policy); |
131 | ||
132 | return ret; | |
133 | } | |
134 | ||
9c0ebcf7 | 135 | static int exynos_target(struct cpufreq_policy *policy, unsigned int index) |
0e0e425f JC |
136 | { |
137 | struct cpufreq_frequency_table *freq_table = exynos_info->freq_table; | |
229b21e2 | 138 | int ret = 0; |
0e0e425f JC |
139 | |
140 | mutex_lock(&cpufreq_lock); | |
141 | ||
142 | if (frequency_locked) | |
143 | goto out; | |
144 | ||
9c0ebcf7 | 145 | ret = exynos_cpufreq_scale(freq_table[index].frequency); |
0e0e425f | 146 | |
a125a17f JL |
147 | out: |
148 | mutex_unlock(&cpufreq_lock); | |
149 | ||
150 | return ret; | |
151 | } | |
152 | ||
153 | #ifdef CONFIG_PM | |
154 | static int exynos_cpufreq_suspend(struct cpufreq_policy *policy) | |
155 | { | |
156 | return 0; | |
157 | } | |
158 | ||
159 | static int exynos_cpufreq_resume(struct cpufreq_policy *policy) | |
160 | { | |
161 | return 0; | |
162 | } | |
163 | #endif | |
164 | ||
165 | /** | |
166 | * exynos_cpufreq_pm_notifier - block CPUFREQ's activities in suspend-resume | |
167 | * context | |
168 | * @notifier | |
169 | * @pm_event | |
170 | * @v | |
171 | * | |
172 | * While frequency_locked == true, target() ignores every frequency but | |
173 | * locking_frequency. The locking_frequency value is the initial frequency, | |
174 | * which is set by the bootloader. In order to eliminate possible | |
175 | * inconsistency in clock values, we save and restore frequencies during | |
176 | * suspend and resume and block CPUFREQ activities. Note that the standard | |
177 | * suspend/resume cannot be used as they are too deep (syscore_ops) for | |
178 | * regulator actions. | |
179 | */ | |
180 | static int exynos_cpufreq_pm_notifier(struct notifier_block *notifier, | |
181 | unsigned long pm_event, void *v) | |
182 | { | |
0e0e425f | 183 | int ret; |
a125a17f | 184 | |
a125a17f JL |
185 | switch (pm_event) { |
186 | case PM_SUSPEND_PREPARE: | |
0e0e425f | 187 | mutex_lock(&cpufreq_lock); |
a125a17f | 188 | frequency_locked = true; |
0e0e425f | 189 | mutex_unlock(&cpufreq_lock); |
a125a17f | 190 | |
0e0e425f JC |
191 | ret = exynos_cpufreq_scale(locking_frequency); |
192 | if (ret < 0) | |
193 | return NOTIFY_BAD; | |
a125a17f | 194 | |
a125a17f JL |
195 | break; |
196 | ||
197 | case PM_POST_SUSPEND: | |
0e0e425f | 198 | mutex_lock(&cpufreq_lock); |
a125a17f | 199 | frequency_locked = false; |
0e0e425f | 200 | mutex_unlock(&cpufreq_lock); |
a125a17f JL |
201 | break; |
202 | } | |
a125a17f JL |
203 | |
204 | return NOTIFY_OK; | |
205 | } | |
206 | ||
207 | static struct notifier_block exynos_cpufreq_nb = { | |
208 | .notifier_call = exynos_cpufreq_pm_notifier, | |
209 | }; | |
210 | ||
211 | static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy) | |
212 | { | |
652ed95d | 213 | policy->clk = exynos_info->cpu_clk; |
b249abae | 214 | return cpufreq_generic_init(policy, exynos_info->freq_table, 100000); |
a125a17f JL |
215 | } |
216 | ||
217 | static struct cpufreq_driver exynos_driver = { | |
ae6b4271 | 218 | .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
eea6181e | 219 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 220 | .target_index = exynos_target, |
652ed95d | 221 | .get = cpufreq_generic_get, |
a125a17f | 222 | .init = exynos_cpufreq_cpu_init, |
eea6181e | 223 | .exit = cpufreq_generic_exit, |
a125a17f | 224 | .name = "exynos_cpufreq", |
eea6181e | 225 | .attr = cpufreq_generic_attr, |
c683c2c9 LM |
226 | #ifdef CONFIG_ARM_EXYNOS_CPU_FREQ_BOOST_SW |
227 | .boost_supported = true, | |
228 | #endif | |
a125a17f JL |
229 | #ifdef CONFIG_PM |
230 | .suspend = exynos_cpufreq_suspend, | |
231 | .resume = exynos_cpufreq_resume, | |
232 | #endif | |
233 | }; | |
234 | ||
d568b6f7 | 235 | static int exynos_cpufreq_probe(struct platform_device *pdev) |
a125a17f JL |
236 | { |
237 | int ret = -EINVAL; | |
238 | ||
d5b73cd8 | 239 | exynos_info = kzalloc(sizeof(*exynos_info), GFP_KERNEL); |
a125a17f JL |
240 | if (!exynos_info) |
241 | return -ENOMEM; | |
242 | ||
243 | if (soc_is_exynos4210()) | |
244 | ret = exynos4210_cpufreq_init(exynos_info); | |
a35c5051 JL |
245 | else if (soc_is_exynos4212() || soc_is_exynos4412()) |
246 | ret = exynos4x12_cpufreq_init(exynos_info); | |
562a6cbe JL |
247 | else if (soc_is_exynos5250()) |
248 | ret = exynos5250_cpufreq_init(exynos_info); | |
a125a17f | 249 | else |
c1585207 | 250 | return 0; |
a125a17f JL |
251 | |
252 | if (ret) | |
253 | goto err_vdd_arm; | |
254 | ||
255 | if (exynos_info->set_freq == NULL) { | |
256 | pr_err("%s: No set_freq function (ERR)\n", __func__); | |
257 | goto err_vdd_arm; | |
258 | } | |
259 | ||
260 | arm_regulator = regulator_get(NULL, "vdd_arm"); | |
261 | if (IS_ERR(arm_regulator)) { | |
262 | pr_err("%s: failed to get resource vdd_arm\n", __func__); | |
263 | goto err_vdd_arm; | |
264 | } | |
265 | ||
652ed95d | 266 | locking_frequency = clk_get_rate(exynos_info->cpu_clk) / 1000; |
6e45eb12 | 267 | |
a125a17f JL |
268 | register_pm_notifier(&exynos_cpufreq_nb); |
269 | ||
270 | if (cpufreq_register_driver(&exynos_driver)) { | |
271 | pr_err("%s: failed to register cpufreq driver\n", __func__); | |
272 | goto err_cpufreq; | |
273 | } | |
274 | ||
275 | return 0; | |
276 | err_cpufreq: | |
277 | unregister_pm_notifier(&exynos_cpufreq_nb); | |
278 | ||
184cddd1 | 279 | regulator_put(arm_regulator); |
a125a17f JL |
280 | err_vdd_arm: |
281 | kfree(exynos_info); | |
a125a17f JL |
282 | return -EINVAL; |
283 | } | |
d568b6f7 LM |
284 | |
285 | static struct platform_driver exynos_cpufreq_platdrv = { | |
286 | .driver = { | |
287 | .name = "exynos-cpufreq", | |
288 | .owner = THIS_MODULE, | |
289 | }, | |
290 | .probe = exynos_cpufreq_probe, | |
291 | }; | |
292 | module_platform_driver(exynos_cpufreq_platdrv); |