[deliverable/linux.git] / drivers / cpufreq / exynos4210-cpufreq.c

/*
 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * EXYNOS4 - CPU frequency scaling support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/regulator/consumer.h>
#include <linux/cpufreq.h>
#include <linux/notifier.h>
#include <linux/suspend.h>

#include <mach/map.h>
#include <mach/regs-clock.h>
#include <mach/regs-mem.h>

#include <plat/clock.h>
#include <plat/pm.h>

static struct clk *cpu_clk;
static struct clk *moutcore;
static struct clk *mout_mpll;
static struct clk *mout_apll;

static struct regulator *arm_regulator;

static struct cpufreq_freqs freqs;

struct cpufreq_clkdiv {
	unsigned int clkdiv;
};

static unsigned int locking_frequency;
static bool frequency_locked;
static DEFINE_MUTEX(cpufreq_lock);

enum cpufreq_level_index {
	L0, L1, L2, L3, L4, CPUFREQ_LEVEL_END,
};

static struct cpufreq_clkdiv exynos4_clkdiv_table[CPUFREQ_LEVEL_END];

static struct cpufreq_frequency_table exynos4_freq_table[] = {
	{L0, 1200*1000},
	{L1, 1000*1000},
	{L2, 800*1000},
	{L3, 500*1000},
	{L4, 200*1000},
	{0, CPUFREQ_TABLE_END},
};

static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
	/*
	 * Clock divider value for following
	 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
	 *		DIVATB, DIVPCLK_DBG, DIVAPLL }
	 */

	/* ARM L0: 1200MHz */
	{ 0, 3, 7, 3, 4, 1, 7 },

	/* ARM L1: 1000MHz */
	{ 0, 3, 7, 3, 4, 1, 7 },

	/* ARM L2: 800MHz */
	{ 0, 3, 7, 3, 3, 1, 7 },

	/* ARM L3: 500MHz */
	{ 0, 3, 7, 3, 3, 1, 7 },

	/* ARM L4: 200MHz */
	{ 0, 1, 3, 1, 3, 1, 0 },
};

static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
	/*
	 * Clock divider value for following
	 * { DIVCOPY, DIVHPM }
	 */

	/* ARM L0: 1200MHz */
	{ 5, 0 },

	/* ARM L1: 1000MHz */
	{ 4, 0 },

	/* ARM L2: 800MHz */
	{ 3, 0 },

	/* ARM L3: 500MHz */
	{ 3, 0 },

	/* ARM L4: 200MHz */
	{ 3, 0 },
};

struct cpufreq_voltage_table {
	unsigned int	index;		/* any */
	unsigned int	arm_volt;	/* uV */
};

static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {
	{
		.index		= L0,
		.arm_volt	= 1350000,
	}, {
		.index		= L1,
		.arm_volt	= 1300000,
	}, {
		.index		= L2,
		.arm_volt	= 1200000,
	}, {
		.index		= L3,
		.arm_volt	= 1100000,
	}, {
		.index		= L4,
		.arm_volt	= 1050000,
	},
};

static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
	/* APLL FOUT L0: 1200MHz */
	((150 << 16) | (3 << 8) | 1),

	/* APLL FOUT L1: 1000MHz */
	((250 << 16) | (6 << 8) | 1),

	/* APLL FOUT L2: 800MHz */
	((200 << 16) | (6 << 8) | 1),

	/* APLL FOUT L3: 500MHz */
	((250 << 16) | (6 << 8) | 2),

	/* APLL FOUT L4: 200MHz */
	((200 << 16) | (6 << 8) | 3),
};

static int exynos4_verify_speed(struct cpufreq_policy *policy)
{
	return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
}

static unsigned int exynos4_getspeed(unsigned int cpu)
{
	return clk_get_rate(cpu_clk) / 1000;
}

static void exynos4_set_clkdiv(unsigned int div_index)
{
	unsigned int tmp;

	/* Change Divider - CPU0 */

	tmp = exynos4_clkdiv_table[div_index].clkdiv;

	__raw_writel(tmp, S5P_CLKDIV_CPU);

	do {
		tmp = __raw_readl(S5P_CLKDIV_STATCPU);
	} while (tmp & 0x1111111);

	/* Change Divider - CPU1 */

	tmp = __raw_readl(S5P_CLKDIV_CPU1);

	tmp &= ~((0x7 << 4) | 0x7);

	tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
		(clkdiv_cpu1[div_index][1] << 0));

	__raw_writel(tmp, S5P_CLKDIV_CPU1);

	do {
		tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
	} while (tmp & 0x11);
}

static void exynos4_set_apll(unsigned int index)
{
	unsigned int tmp;

	/* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
	clk_set_parent(moutcore, mout_mpll);

	do {
		tmp = (__raw_readl(S5P_CLKMUX_STATCPU)
			>> S5P_CLKSRC_CPU_MUXCORE_SHIFT);
		tmp &= 0x7;
	} while (tmp != 0x2);

	/* 2. Set APLL Lock time */
	__raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK);

	/* 3. Change PLL PMS values */
	tmp = __raw_readl(S5P_APLL_CON0);
	tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
	tmp |= exynos4_apll_pms_table[index];
	__raw_writel(tmp, S5P_APLL_CON0);

	/* 4. wait_lock_time */
	do {
		tmp = __raw_readl(S5P_APLL_CON0);
	} while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT)));

	/* 5. MUX_CORE_SEL = APLL */
	clk_set_parent(moutcore, mout_apll);

	do {
		tmp = __raw_readl(S5P_CLKMUX_STATCPU);
		tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
	} while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
}

static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index)
{
	unsigned int tmp;

	if (old_index > new_index) {
		/*
		 * L1/L3, L2/L4 Level change require
		 * to only change s divider value
		 */
		if (((old_index == L3) && (new_index == L1)) ||
				((old_index == L4) && (new_index == L2))) {
			/* 1. Change the system clock divider values */
			exynos4_set_clkdiv(new_index);

			/* 2. Change just s value in apll m,p,s value */
			tmp = __raw_readl(S5P_APLL_CON0);
			tmp &= ~(0x7 << 0);
			tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
			__raw_writel(tmp, S5P_APLL_CON0);
		} else {
			/* Clock Configuration Procedure */
			/* 1. Change the system clock divider values */
			exynos4_set_clkdiv(new_index);
			/* 2. Change the apll m,p,s value */
			exynos4_set_apll(new_index);
		}
	} else if (old_index < new_index) {
		/*
		 * L1/L3, L2/L4 Level change require
		 * to only change s divider value
		 */
		if (((old_index == L1) && (new_index == L3)) ||
				((old_index == L2) && (new_index == L4))) {
			/* 1. Change just s value in apll m,p,s value */
			tmp = __raw_readl(S5P_APLL_CON0);
			tmp &= ~(0x7 << 0);
			tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
			__raw_writel(tmp, S5P_APLL_CON0);

			/* 2. Change the system clock divider values */
			exynos4_set_clkdiv(new_index);
		} else {
			/* Clock Configuration Procedure */
			/* 1. Change the apll m,p,s value */
			exynos4_set_apll(new_index);
			/* 2. Change the system clock divider values */
			exynos4_set_clkdiv(new_index);
		}
	}
}

static int exynos4_target(struct cpufreq_policy *policy,
			  unsigned int target_freq,
			  unsigned int relation)
{
	unsigned int index, old_index;
	unsigned int arm_volt;
	int err = -EINVAL;

	freqs.old = exynos4_getspeed(policy->cpu);

	mutex_lock(&cpufreq_lock);

	if (frequency_locked && target_freq != locking_frequency) {
		err = -EAGAIN;
		goto out;
	}

	if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
					   freqs.old, relation, &old_index))
		goto out;

	if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
					   target_freq, relation, &index))
		goto out;

	err = 0;

	freqs.new = exynos4_freq_table[index].frequency;
	freqs.cpu = policy->cpu;

	if (freqs.new == freqs.old)
		goto out;

	/* get the voltage value */
	arm_volt = exynos4_volt_table[index].arm_volt;

	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);

	/* control regulator */
	if (freqs.new > freqs.old) {
		/* Voltage up */
		regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
	}

	/* Clock Configuration Procedure */
	exynos4_set_frequency(old_index, index);

	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);

	/* control regulator */
	if (freqs.new < freqs.old) {
		/* Voltage down */
		regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
	}

out:
	mutex_unlock(&cpufreq_lock);
	return err;
}

#ifdef CONFIG_PM
/*
 * These suspend/resume are used as syscore_ops, it is already too
 * late to set regulator voltages at this stage.
 */
static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy)
{
	return 0;
}

static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)
{
	return 0;
}
#endif

/**
 * exynos4_cpufreq_pm_notifier - block CPUFREQ's activities in suspend-resume
 *			context
 * @notifier
 * @pm_event
 * @v
 *
 * While frequency_locked == true, target() ignores every frequency but
 * locking_frequency. The locking_frequency value is the initial frequency,
 * which is set by the bootloader. In order to eliminate possible
 * inconsistency in clock values, we save and restore frequencies during
 * suspend and resume and block CPUFREQ activities. Note that the standard
 * suspend/resume cannot be used as they are too deep (syscore_ops) for
 * regulator actions.
 */
static int exynos4_cpufreq_pm_notifier(struct notifier_block *notifier,
				       unsigned long pm_event, void *v)
{
	struct cpufreq_policy *policy = cpufreq_cpu_get(0); /* boot CPU */
	static unsigned int saved_frequency;
	unsigned int temp;

	mutex_lock(&cpufreq_lock);
	switch (pm_event) {
	case PM_SUSPEND_PREPARE:
		if (frequency_locked)
			goto out;
		frequency_locked = true;

		if (locking_frequency) {
			saved_frequency = exynos4_getspeed(0);

			mutex_unlock(&cpufreq_lock);
			exynos4_target(policy, locking_frequency,
				       CPUFREQ_RELATION_H);
			mutex_lock(&cpufreq_lock);
		}

		break;
	case PM_POST_SUSPEND:

		if (saved_frequency) {
			/*
			 * While frequency_locked, only locking_frequency
			 * is valid for target(). In order to use
			 * saved_frequency while keeping frequency_locked,
			 * we temporarly overwrite locking_frequency.
			 */
			temp = locking_frequency;
			locking_frequency = saved_frequency;

			mutex_unlock(&cpufreq_lock);
			exynos4_target(policy, locking_frequency,
				       CPUFREQ_RELATION_H);
			mutex_lock(&cpufreq_lock);

			locking_frequency = temp;
		}

		frequency_locked = false;
		break;
	}
out:
	mutex_unlock(&cpufreq_lock);

	return NOTIFY_OK;
}

static struct notifier_block exynos4_cpufreq_nb = {
	.notifier_call = exynos4_cpufreq_pm_notifier,
};

static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
{
	int ret;

	policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);

	cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);

	/* set the transition latency value */
	policy->cpuinfo.transition_latency = 100000;

	/*
	 * EXYNOS4 multi-core processors has 2 cores
	 * that the frequency cannot be set independently.
	 * Each cpu is bound to the same speed.
	 * So the affected cpu is all of the cpus.
	 */
	if (!cpu_online(1)) {
		cpumask_copy(policy->related_cpus, cpu_possible_mask);
		cpumask_copy(policy->cpus, cpu_online_mask);
	} else {
		cpumask_setall(policy->cpus);
	}

	ret = cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
	if (ret)
		return ret;

	cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);

	return 0;
}

static int exynos4_cpufreq_cpu_exit(struct cpufreq_policy *policy)
{
	cpufreq_frequency_table_put_attr(policy->cpu);
	return 0;
}

static struct freq_attr *exynos4_cpufreq_attr[] = {
	&cpufreq_freq_attr_scaling_available_freqs,
	NULL,
};

static struct cpufreq_driver exynos4_driver = {
	.flags		= CPUFREQ_STICKY,
	.verify		= exynos4_verify_speed,
	.target		= exynos4_target,
	.get		= exynos4_getspeed,
	.init		= exynos4_cpufreq_cpu_init,
	.exit		= exynos4_cpufreq_cpu_exit,
	.name		= "exynos4_cpufreq",
	.attr		= exynos4_cpufreq_attr,
#ifdef CONFIG_PM
	.suspend	= exynos4_cpufreq_suspend,
	.resume		= exynos4_cpufreq_resume,
#endif
};

static int __init exynos4_cpufreq_init(void)
{
	int i;
	unsigned int tmp;

	cpu_clk = clk_get(NULL, "armclk");
	if (IS_ERR(cpu_clk))
		return PTR_ERR(cpu_clk);

	locking_frequency = exynos4_getspeed(0);

	moutcore = clk_get(NULL, "moutcore");
	if (IS_ERR(moutcore))
		goto out;

	mout_mpll = clk_get(NULL, "mout_mpll");
	if (IS_ERR(mout_mpll))
		goto out;

	mout_apll = clk_get(NULL, "mout_apll");
	if (IS_ERR(mout_apll))
		goto out;

	arm_regulator = regulator_get(NULL, "vdd_arm");
	if (IS_ERR(arm_regulator)) {
		printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
		goto out;
	}

	register_pm_notifier(&exynos4_cpufreq_nb);

	tmp = __raw_readl(S5P_CLKDIV_CPU);

	for (i = L0; i <  CPUFREQ_LEVEL_END; i++) {
		tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK |
			 S5P_CLKDIV_CPU0_COREM0_MASK |
			 S5P_CLKDIV_CPU0_COREM1_MASK |
			 S5P_CLKDIV_CPU0_PERIPH_MASK |
			 S5P_CLKDIV_CPU0_ATB_MASK |
			 S5P_CLKDIV_CPU0_PCLKDBG_MASK |
			 S5P_CLKDIV_CPU0_APLL_MASK);

		tmp |= ((clkdiv_cpu0[i][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) |
			(clkdiv_cpu0[i][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) |
			(clkdiv_cpu0[i][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) |
			(clkdiv_cpu0[i][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) |
			(clkdiv_cpu0[i][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) |
			(clkdiv_cpu0[i][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) |
			(clkdiv_cpu0[i][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));

		exynos4_clkdiv_table[i].clkdiv = tmp;
	}

	return cpufreq_register_driver(&exynos4_driver);

out:
	if (!IS_ERR(cpu_clk))
		clk_put(cpu_clk);

	if (!IS_ERR(moutcore))
		clk_put(moutcore);

	if (!IS_ERR(mout_mpll))
		clk_put(mout_mpll);

	if (!IS_ERR(mout_apll))
		clk_put(mout_apll);

	if (!IS_ERR(arm_regulator))
		regulator_put(arm_regulator);

	printk(KERN_ERR "%s: failed initialization\n", __func__);

	return -EINVAL;
}
late_initcall(exynos4_cpufreq_init);
Commit	Line	Data
f7d77079	1	/*
7d30e8b3	2	* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
f40f91fe SK	3	* http://www.samsung.com
f40f91fe SK	4	*
7d30e8b3	5	* EXYNOS4 - CPU frequency scaling support
f40f91fe SK	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/types.h>
	13	#include <linux/kernel.h>
	14	#include <linux/err.h>
	15	#include <linux/clk.h>
	16	#include <linux/io.h>
	17	#include <linux/slab.h>
	18	#include <linux/regulator/consumer.h>
	19	#include <linux/cpufreq.h>
0073f538 MH	20	#include <linux/notifier.h>
0073f538 MH	21	#include <linux/suspend.h>
f40f91fe SK	22
	23	#include <mach/map.h>
	24	#include <mach/regs-clock.h>
	25	#include <mach/regs-mem.h>
	26
	27	#include <plat/clock.h>
bf5ce054	28	#include <plat/pm.h>
f40f91fe SK	29
	30	static struct clk *cpu_clk;
	31	static struct clk *moutcore;
	32	static struct clk *mout_mpll;
	33	static struct clk *mout_apll;
	34
f40f91fe	35	static struct regulator *arm_regulator;
f40f91fe SK	36
f40f91fe SK	37	static struct cpufreq_freqs freqs;
f40f91fe	38
27f805dc JL	39	struct cpufreq_clkdiv {
	40	unsigned int clkdiv;
	41	};
	42
0073f538 MH	43	static unsigned int locking_frequency;
	44	static bool frequency_locked;
	45	static DEFINE_MUTEX(cpufreq_lock);
	46
f40f91fe	47	enum cpufreq_level_index {
ba9d7803	48	L0, L1, L2, L3, L4, CPUFREQ_LEVEL_END,
f40f91fe SK	49	};
f40f91fe SK	50
27f805dc JL	51	static struct cpufreq_clkdiv exynos4_clkdiv_table[CPUFREQ_LEVEL_END];
27f805dc JL	52
7d30e8b3	53	static struct cpufreq_frequency_table exynos4_freq_table[] = {
ba9d7803 JL	54	{L0, 1200*1000},
	55	{L1, 1000*1000},
	56	{L2, 800*1000},
	57	{L3, 500*1000},
	58	{L4, 200*1000},
f40f91fe SK	59	{0, CPUFREQ_TABLE_END},
	60	};
	61
bf5ce054	62	static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
f40f91fe SK	63	/*
	64	* Clock divider value for following
	65	* { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
	66	* DIVATB, DIVPCLK_DBG, DIVAPLL }
	67	*/
	68
ba9d7803 JL	69	/* ARM L0: 1200MHz */
ba9d7803 JL	70	{ 0, 3, 7, 3, 4, 1, 7 },
f40f91fe	71
ba9d7803 JL	72	/* ARM L1: 1000MHz */
ba9d7803 JL	73	{ 0, 3, 7, 3, 4, 1, 7 },
f40f91fe	74
ba9d7803 JL	75	/* ARM L2: 800MHz */
ba9d7803 JL	76	{ 0, 3, 7, 3, 3, 1, 7 },
f40f91fe	77
ba9d7803 JL	78	/* ARM L3: 500MHz */
	79	{ 0, 3, 7, 3, 3, 1, 7 },
	80
	81	/* ARM L4: 200MHz */
	82	{ 0, 1, 3, 1, 3, 1, 0 },
bf5ce054	83	};
f40f91fe	84
bf5ce054 SJ	85	static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
	86	/*
	87	* Clock divider value for following
	88	* { DIVCOPY, DIVHPM }
	89	*/
	90
ba9d7803 JL	91	/* ARM L0: 1200MHz */
	92	{ 5, 0 },
	93
	94	/* ARM L1: 1000MHz */
	95	{ 4, 0 },
bf5ce054	96
ba9d7803	97	/* ARM L2: 800MHz */
bf5ce054	98	{ 3, 0 },
f40f91fe	99
ba9d7803	100	/* ARM L3: 500MHz */
bf5ce054 SJ	101	{ 3, 0 },
bf5ce054 SJ	102
ba9d7803	103	/* ARM L4: 200MHz */
bf5ce054	104	{ 3, 0 },
f40f91fe SK	105	};
f40f91fe SK	106
f40f91fe SK	107	struct cpufreq_voltage_table {
	108	unsigned int index; /* any */
	109	unsigned int arm_volt; /* uV */
f40f91fe SK	110	};
f40f91fe SK	111
7d30e8b3	112	static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {
f40f91fe SK	113	{
f40f91fe SK	114	.index = L0,
ba9d7803	115	.arm_volt = 1350000,
f40f91fe SK	116	}, {
f40f91fe SK	117	.index = L1,
ba9d7803	118	.arm_volt = 1300000,
f40f91fe SK	119	}, {
f40f91fe SK	120	.index = L2,
ba9d7803	121	.arm_volt = 1200000,
f40f91fe SK	122	}, {
f40f91fe SK	123	.index = L3,
ba9d7803 JL	124	.arm_volt = 1100000,
	125	}, {
	126	.index = L4,
	127	.arm_volt = 1050000,
f40f91fe SK	128	},
	129	};
	130
7d30e8b3	131	static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
ba9d7803 JL	132	/* APLL FOUT L0: 1200MHz */
	133	((150 << 16) \| (3 << 8) \| 1),
	134
	135	/* APLL FOUT L1: 1000MHz */
bf5ce054 SJ	136	((250 << 16) \| (6 << 8) \| 1),
bf5ce054 SJ	137
ba9d7803	138	/* APLL FOUT L2: 800MHz */
bf5ce054 SJ	139	((200 << 16) \| (6 << 8) \| 1),
bf5ce054 SJ	140
ba9d7803 JL	141	/* APLL FOUT L3: 500MHz */
ba9d7803 JL	142	((250 << 16) \| (6 << 8) \| 2),
bf5ce054	143
ba9d7803 JL	144	/* APLL FOUT L4: 200MHz */
ba9d7803 JL	145	((200 << 16) \| (6 << 8) \| 3),
bf5ce054 SJ	146	};
bf5ce054 SJ	147
2f0d6f20	148	static int exynos4_verify_speed(struct cpufreq_policy *policy)
f40f91fe	149	{
7d30e8b3	150	return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
f40f91fe SK	151	}
f40f91fe SK	152
2f0d6f20	153	static unsigned int exynos4_getspeed(unsigned int cpu)
f40f91fe SK	154	{
	155	return clk_get_rate(cpu_clk) / 1000;
	156	}
	157
2f0d6f20	158	static void exynos4_set_clkdiv(unsigned int div_index)
f40f91fe SK	159	{
	160	unsigned int tmp;
	161
	162	/* Change Divider - CPU0 */
	163
27f805dc	164	tmp = exynos4_clkdiv_table[div_index].clkdiv;
f40f91fe SK	165
	166	__raw_writel(tmp, S5P_CLKDIV_CPU);
	167
	168	do {
	169	tmp = __raw_readl(S5P_CLKDIV_STATCPU);
	170	} while (tmp & 0x1111111);
	171
bf5ce054 SJ	172	/* Change Divider - CPU1 */
	173
	174	tmp = __raw_readl(S5P_CLKDIV_CPU1);
	175
	176	tmp &= ~((0x7 << 4) \| 0x7);
	177
	178	tmp \|= ((clkdiv_cpu1[div_index][0] << 4) \|
	179	(clkdiv_cpu1[div_index][1] << 0));
	180
	181	__raw_writel(tmp, S5P_CLKDIV_CPU1);
	182
	183	do {
	184	tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
	185	} while (tmp & 0x11);
f40f91fe SK	186	}
f40f91fe SK	187
7d30e8b3	188	static void exynos4_set_apll(unsigned int index)
bf5ce054 SJ	189	{
	190	unsigned int tmp;
	191
	192	/* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
	193	clk_set_parent(moutcore, mout_mpll);
	194
	195	do {
	196	tmp = (__raw_readl(S5P_CLKMUX_STATCPU)
	197	>> S5P_CLKSRC_CPU_MUXCORE_SHIFT);
	198	tmp &= 0x7;
	199	} while (tmp != 0x2);
	200
	201	/* 2. Set APLL Lock time */
	202	__raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK);
	203
	204	/* 3. Change PLL PMS values */
	205	tmp = __raw_readl(S5P_APLL_CON0);
	206	tmp &= ~((0x3ff << 16) \| (0x3f << 8) \| (0x7 << 0));
7d30e8b3	207	tmp \|= exynos4_apll_pms_table[index];
bf5ce054 SJ	208	__raw_writel(tmp, S5P_APLL_CON0);
	209
	210	/* 4. wait_lock_time */
	211	do {
	212	tmp = __raw_readl(S5P_APLL_CON0);
	213	} while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT)));
	214
	215	/* 5. MUX_CORE_SEL = APLL */
	216	clk_set_parent(moutcore, mout_apll);
	217
	218	do {
	219	tmp = __raw_readl(S5P_CLKMUX_STATCPU);
	220	tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
	221	} while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
	222	}
	223
7d30e8b3	224	static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index)
bf5ce054 SJ	225	{
	226	unsigned int tmp;
	227
	228	if (old_index > new_index) {
27f805dc JL	229	/*
	230	* L1/L3, L2/L4 Level change require
	231	* to only change s divider value
	232	*/
	233	if (((old_index == L3) && (new_index == L1)) \|\|
	234	((old_index == L4) && (new_index == L2))) {
bf5ce054	235	/* 1. Change the system clock divider values */
7d30e8b3	236	exynos4_set_clkdiv(new_index);
bf5ce054 SJ	237
	238	/* 2. Change just s value in apll m,p,s value */
	239	tmp = __raw_readl(S5P_APLL_CON0);
	240	tmp &= ~(0x7 << 0);
7d30e8b3	241	tmp \|= (exynos4_apll_pms_table[new_index] & 0x7);
bf5ce054	242	__raw_writel(tmp, S5P_APLL_CON0);
bf5ce054	243	} else {
27f805dc JL	244	/* Clock Configuration Procedure */
	245	/* 1. Change the system clock divider values */
	246	exynos4_set_clkdiv(new_index);
	247	/* 2. Change the apll m,p,s value */
	248	exynos4_set_apll(new_index);
	249	}
	250	} else if (old_index < new_index) {
	251	/*
	252	* L1/L3, L2/L4 Level change require
	253	* to only change s divider value
	254	*/
	255	if (((old_index == L1) && (new_index == L3)) \|\|
	256	((old_index == L2) && (new_index == L4))) {
bf5ce054 SJ	257	/* 1. Change just s value in apll m,p,s value */
	258	tmp = __raw_readl(S5P_APLL_CON0);
	259	tmp &= ~(0x7 << 0);
7d30e8b3	260	tmp \|= (exynos4_apll_pms_table[new_index] & 0x7);
bf5ce054 SJ	261	__raw_writel(tmp, S5P_APLL_CON0);
bf5ce054 SJ	262
27f805dc JL	263	/* 2. Change the system clock divider values */
	264	exynos4_set_clkdiv(new_index);
	265	} else {
	266	/* Clock Configuration Procedure */
	267	/* 1. Change the apll m,p,s value */
	268	exynos4_set_apll(new_index);
bf5ce054	269	/* 2. Change the system clock divider values */
7d30e8b3	270	exynos4_set_clkdiv(new_index);
bf5ce054 SJ	271	}
	272	}
	273	}
	274
7d30e8b3	275	static int exynos4_target(struct cpufreq_policy *policy,
f40f91fe SK	276	unsigned int target_freq,
	277	unsigned int relation)
	278	{
bf5ce054	279	unsigned int index, old_index;
c8c430e2	280	unsigned int arm_volt;
0073f538	281	int err = -EINVAL;
f40f91fe	282
7d30e8b3	283	freqs.old = exynos4_getspeed(policy->cpu);
f40f91fe	284
0073f538 MH	285	mutex_lock(&cpufreq_lock);
	286
	287	if (frequency_locked && target_freq != locking_frequency) {
	288	err = -EAGAIN;
	289	goto out;
	290	}
	291
7d30e8b3	292	if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
bf5ce054	293	freqs.old, relation, &old_index))
0073f538	294	goto out;
bf5ce054	295
7d30e8b3	296	if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
f40f91fe	297	target_freq, relation, &index))
0073f538 MH	298	goto out;
	299
	300	err = 0;
f40f91fe	301
7d30e8b3	302	freqs.new = exynos4_freq_table[index].frequency;
f40f91fe SK	303	freqs.cpu = policy->cpu;
	304
	305	if (freqs.new == freqs.old)
0073f538	306	goto out;
f40f91fe	307
f40f91fe	308	/* get the voltage value */
7d30e8b3	309	arm_volt = exynos4_volt_table[index].arm_volt;
f40f91fe SK	310
	311	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
	312
	313	/* control regulator */
	314	if (freqs.new > freqs.old) {
	315	/* Voltage up */
f40f91fe	316	regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
f40f91fe SK	317	}
	318
	319	/* Clock Configuration Procedure */
7d30e8b3	320	exynos4_set_frequency(old_index, index);
f40f91fe	321
27f805dc JL	322	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
27f805dc JL	323
f40f91fe SK	324	/* control regulator */
	325	if (freqs.new < freqs.old) {
	326	/* Voltage down */
f40f91fe	327	regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
f40f91fe SK	328	}
f40f91fe SK	329
0073f538 MH	330	out:
	331	mutex_unlock(&cpufreq_lock);
	332	return err;
f40f91fe SK	333	}
	334
	335	#ifdef CONFIG_PM
0073f538 MH	336	/*
	337	* These suspend/resume are used as syscore_ops, it is already too
	338	* late to set regulator voltages at this stage.
	339	*/
411f5c7a	340	static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy)
f40f91fe SK	341	{
	342	return 0;
	343	}
	344
7d30e8b3	345	static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)
f40f91fe SK	346	{
	347	return 0;
	348	}
	349	#endif
	350
0073f538 MH	351	/**
	352	* exynos4_cpufreq_pm_notifier - block CPUFREQ's activities in suspend-resume
	353	* context
	354	* @notifier
	355	* @pm_event
	356	* @v
	357	*
	358	* While frequency_locked == true, target() ignores every frequency but
	359	* locking_frequency. The locking_frequency value is the initial frequency,
	360	* which is set by the bootloader. In order to eliminate possible
	361	* inconsistency in clock values, we save and restore frequencies during
	362	* suspend and resume and block CPUFREQ activities. Note that the standard
	363	* suspend/resume cannot be used as they are too deep (syscore_ops) for
	364	* regulator actions.
	365	*/
	366	static int exynos4_cpufreq_pm_notifier(struct notifier_block *notifier,
	367	unsigned long pm_event, void *v)
	368	{
	369	struct cpufreq_policy policy = cpufreq_cpu_get(0); / boot CPU */
	370	static unsigned int saved_frequency;
	371	unsigned int temp;
	372
	373	mutex_lock(&cpufreq_lock);
	374	switch (pm_event) {
	375	case PM_SUSPEND_PREPARE:
	376	if (frequency_locked)
	377	goto out;
	378	frequency_locked = true;
	379
	380	if (locking_frequency) {
	381	saved_frequency = exynos4_getspeed(0);
	382
	383	mutex_unlock(&cpufreq_lock);
	384	exynos4_target(policy, locking_frequency,
	385	CPUFREQ_RELATION_H);
	386	mutex_lock(&cpufreq_lock);
	387	}
	388
	389	break;
	390	case PM_POST_SUSPEND:
	391
	392	if (saved_frequency) {
	393	/*
	394	* While frequency_locked, only locking_frequency
	395	* is valid for target(). In order to use
	396	* saved_frequency while keeping frequency_locked,
	397	* we temporarly overwrite locking_frequency.
	398	*/
	399	temp = locking_frequency;
	400	locking_frequency = saved_frequency;
	401
	402	mutex_unlock(&cpufreq_lock);
	403	exynos4_target(policy, locking_frequency,
	404	CPUFREQ_RELATION_H);
	405	mutex_lock(&cpufreq_lock);
	406
	407	locking_frequency = temp;
	408	}
	409
	410	frequency_locked = false;
	411	break;
	412	}
	413	out:
	414	mutex_unlock(&cpufreq_lock);
415
416	return NOTIFY_OK;
417	}
418
419	static struct notifier_block exynos4_cpufreq_nb = {
420	.notifier_call = exynos4_cpufreq_pm_notifier,
421	};
422
7d30e8b3	423	static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
f40f91fe	424	{
5beae3b9 DK	425	int ret;
5beae3b9 DK	426
7d30e8b3	427	policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);
f40f91fe	428
7d30e8b3	429	cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
f40f91fe SK	430
	431	/* set the transition latency value */
	432	policy->cpuinfo.transition_latency = 100000;
	433
	434	/*
7d30e8b3	435	* EXYNOS4 multi-core processors has 2 cores
f40f91fe SK	436	* that the frequency cannot be set independently.
	437	* Each cpu is bound to the same speed.
	438	* So the affected cpu is all of the cpus.
	439	*/
27f805dc JL	440	if (!cpu_online(1)) {
	441	cpumask_copy(policy->related_cpus, cpu_possible_mask);
	442	cpumask_copy(policy->cpus, cpu_online_mask);
	443	} else {
	444	cpumask_setall(policy->cpus);
	445	}
f40f91fe	446
5beae3b9 DK	447	ret = cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
	448	if (ret)
	449	return ret;
	450
	451	cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
	452
	453	return 0;
f40f91fe SK	454	}
f40f91fe SK	455
5beae3b9 DK	456	static int exynos4_cpufreq_cpu_exit(struct cpufreq_policy *policy)
	457	{
	458	cpufreq_frequency_table_put_attr(policy->cpu);
	459	return 0;
	460	}
	461
	462	static struct freq_attr *exynos4_cpufreq_attr[] = {
	463	&cpufreq_freq_attr_scaling_available_freqs,
	464	NULL,
	465	};
	466
7d30e8b3	467	static struct cpufreq_driver exynos4_driver = {
f40f91fe	468	.flags = CPUFREQ_STICKY,
7d30e8b3 KK	469	.verify = exynos4_verify_speed,
	470	.target = exynos4_target,
	471	.get = exynos4_getspeed,
	472	.init = exynos4_cpufreq_cpu_init,
5beae3b9	473	.exit = exynos4_cpufreq_cpu_exit,
7d30e8b3	474	.name = "exynos4_cpufreq",
5beae3b9	475	.attr = exynos4_cpufreq_attr,
f40f91fe	476	#ifdef CONFIG_PM
7d30e8b3 KK	477	.suspend = exynos4_cpufreq_suspend,
7d30e8b3 KK	478	.resume = exynos4_cpufreq_resume,
f40f91fe SK	479	#endif
	480	};
	481
7d30e8b3	482	static int __init exynos4_cpufreq_init(void)
f40f91fe	483	{
27f805dc JL	484	int i;
	485	unsigned int tmp;
	486
f40f91fe SK	487	cpu_clk = clk_get(NULL, "armclk");
	488	if (IS_ERR(cpu_clk))
	489	return PTR_ERR(cpu_clk);
	490
0073f538 MH	491	locking_frequency = exynos4_getspeed(0);
0073f538 MH	492
f40f91fe SK	493	moutcore = clk_get(NULL, "moutcore");
	494	if (IS_ERR(moutcore))
	495	goto out;
	496
	497	mout_mpll = clk_get(NULL, "mout_mpll");
	498	if (IS_ERR(mout_mpll))
	499	goto out;
	500
	501	mout_apll = clk_get(NULL, "mout_apll");
	502	if (IS_ERR(mout_apll))
	503	goto out;
	504
f40f91fe SK	505	arm_regulator = regulator_get(NULL, "vdd_arm");
	506	if (IS_ERR(arm_regulator)) {
	507	printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
	508	goto out;
	509	}
	510
0073f538 MH	511	register_pm_notifier(&exynos4_cpufreq_nb);
0073f538 MH	512
27f805dc JL	513	tmp = __raw_readl(S5P_CLKDIV_CPU);
	514
	515	for (i = L0; i < CPUFREQ_LEVEL_END; i++) {
	516	tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK \|
	517	S5P_CLKDIV_CPU0_COREM0_MASK \|
	518	S5P_CLKDIV_CPU0_COREM1_MASK \|
	519	S5P_CLKDIV_CPU0_PERIPH_MASK \|
	520	S5P_CLKDIV_CPU0_ATB_MASK \|
	521	S5P_CLKDIV_CPU0_PCLKDBG_MASK \|
	522	S5P_CLKDIV_CPU0_APLL_MASK);
	523
	524	tmp \|= ((clkdiv_cpu0[i][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) \|
	525	(clkdiv_cpu0[i][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) \|
	526	(clkdiv_cpu0[i][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) \|
	527	(clkdiv_cpu0[i][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) \|
	528	(clkdiv_cpu0[i][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) \|
	529	(clkdiv_cpu0[i][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) \|
	530	(clkdiv_cpu0[i][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));
	531
	532	exynos4_clkdiv_table[i].clkdiv = tmp;
	533	}
	534
7d30e8b3	535	return cpufreq_register_driver(&exynos4_driver);
f40f91fe SK	536
	537	out:
	538	if (!IS_ERR(cpu_clk))
	539	clk_put(cpu_clk);
	540
	541	if (!IS_ERR(moutcore))
	542	clk_put(moutcore);
	543
	544	if (!IS_ERR(mout_mpll))
	545	clk_put(mout_mpll);
	546
	547	if (!IS_ERR(mout_apll))
	548	clk_put(mout_apll);
	549
f40f91fe SK	550	if (!IS_ERR(arm_regulator))
	551	regulator_put(arm_regulator);
	552
f40f91fe SK	553	printk(KERN_ERR "%s: failed initialization\n", __func__);
	554
	555	return -EINVAL;
	556	}
7d30e8b3	557	late_initcall(exynos4_cpufreq_init);