[deliverable/linux.git] / drivers / cpufreq / exynos4x12-cpufreq.c

/*
 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * EXYNOS4X12 - CPU frequency scaling support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/cpufreq.h>

#include "exynos-cpufreq.h"

static struct clk *cpu_clk;
static struct clk *moutcore;
static struct clk *mout_mpll;
static struct clk *mout_apll;

static unsigned int exynos4x12_volt_table[] = {
	1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
	1000000,  987500,  975000,  950000,  925000,  900000,  900000
};

static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
	{CPUFREQ_BOOST_FREQ, L0, 1500 * 1000},
	{0, L1, 1400 * 1000},
	{0, L2, 1300 * 1000},
	{0, L3, 1200 * 1000},
	{0, L4, 1100 * 1000},
	{0, L5, 1000 * 1000},
	{0, L6,  900 * 1000},
	{0, L7,  800 * 1000},
	{0, L8,  700 * 1000},
	{0, L9,  600 * 1000},
	{0, L10, 500 * 1000},
	{0, L11, 400 * 1000},
	{0, L12, 300 * 1000},
	{0, L13, 200 * 1000},
	{0, 0, CPUFREQ_TABLE_END},
};

static struct apll_freq *apll_freq_4x12;

static struct apll_freq apll_freq_4212[] = {
	/*
	 * values:
	 * freq
	 * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
	 * clock divider for COPY, HPM, RESERVED
	 * PLL M, P, S
	 */
	APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 250, 4, 0),
	APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 175, 3, 0),
	APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 325, 6, 0),
	APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 200, 4, 0),
	APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 2, 0, 275, 6, 0),
	APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 2, 0, 125, 3, 0),
	APLL_FREQ(900,  0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 150, 4, 0),
	APLL_FREQ(800,  0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 0),
	APLL_FREQ(700,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 175, 3, 1),
	APLL_FREQ(600,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 200, 4, 1),
	APLL_FREQ(500,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 125, 3, 1),
	APLL_FREQ(400,  0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 1),
	APLL_FREQ(300,  0, 2, 4, 0, 2, 1, 1, 0, 3, 2, 0, 200, 4, 2),
	APLL_FREQ(200,  0, 1, 3, 0, 1, 1, 1, 0, 3, 2, 0, 100, 3, 2),
};

static struct apll_freq apll_freq_4412[] = {
	/*
	 * values:
	 * freq
	 * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
	 * clock divider for COPY, HPM, CORES
	 * PLL M, P, S
	 */
	APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 7, 250, 4, 0),
	APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 6, 175, 3, 0),
	APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 6, 325, 6, 0),
	APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 5, 200, 4, 0),
	APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 0, 5, 275, 6, 0),
	APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 0, 4, 125, 3, 0),
	APLL_FREQ(900,  0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 4, 150, 4, 0),
	APLL_FREQ(800,  0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 3, 100, 3, 0),
	APLL_FREQ(700,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 3, 175, 3, 1),
	APLL_FREQ(600,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 200, 4, 1),
	APLL_FREQ(500,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 125, 3, 1),
	APLL_FREQ(400,  0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 1, 100, 3, 1),
	APLL_FREQ(300,  0, 2, 4, 0, 2, 1, 1, 0, 3, 0, 1, 200, 4, 2),
	APLL_FREQ(200,  0, 1, 3, 0, 1, 1, 1, 0, 3, 0, 0, 100, 3, 2),
};

static void exynos4x12_set_clkdiv(unsigned int div_index)
{
	unsigned int tmp;
	unsigned int stat_cpu1;

	/* Change Divider - CPU0 */

	tmp = apll_freq_4x12[div_index].clk_div_cpu0;

	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);

	while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
		cpu_relax();

	/* Change Divider - CPU1 */
	tmp = apll_freq_4x12[div_index].clk_div_cpu1;

	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
	if (soc_is_exynos4212())
		stat_cpu1 = 0x11;
	else
		stat_cpu1 = 0x111;

	while (__raw_readl(EXYNOS4_CLKDIV_STATCPU1) & stat_cpu1)
		cpu_relax();
}

static void exynos4x12_set_apll(unsigned int index)
{
	unsigned int tmp, freq = apll_freq_4x12[index].freq;

	/* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
	clk_set_parent(moutcore, mout_mpll);

	do {
		cpu_relax();
		tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
			>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
		tmp &= 0x7;
	} while (tmp != 0x2);

	clk_set_rate(mout_apll, freq * 1000);

	/* MUX_CORE_SEL = APLL */
	clk_set_parent(moutcore, mout_apll);

	do {
		cpu_relax();
		tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
		tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
	} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
}

static void exynos4x12_set_frequency(unsigned int old_index,
				  unsigned int new_index)
{
	if (old_index > new_index) {
		exynos4x12_set_clkdiv(new_index);
		exynos4x12_set_apll(new_index);
	} else if (old_index < new_index) {
		exynos4x12_set_apll(new_index);
		exynos4x12_set_clkdiv(new_index);
	}
}

int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
{
	unsigned long rate;

	cpu_clk = clk_get(NULL, "armclk");
	if (IS_ERR(cpu_clk))
		return PTR_ERR(cpu_clk);

	moutcore = clk_get(NULL, "moutcore");
	if (IS_ERR(moutcore))
		goto err_moutcore;

	mout_mpll = clk_get(NULL, "mout_mpll");
	if (IS_ERR(mout_mpll))
		goto err_mout_mpll;

	rate = clk_get_rate(mout_mpll) / 1000;

	mout_apll = clk_get(NULL, "mout_apll");
	if (IS_ERR(mout_apll))
		goto err_mout_apll;

	if (soc_is_exynos4212())
		apll_freq_4x12 = apll_freq_4212;
	else
		apll_freq_4x12 = apll_freq_4412;

	info->mpll_freq_khz = rate;
	/* 800Mhz */
	info->pll_safe_idx = L7;
	info->cpu_clk = cpu_clk;
	info->volt_table = exynos4x12_volt_table;
	info->freq_table = exynos4x12_freq_table;
	info->set_freq = exynos4x12_set_frequency;

	return 0;

err_mout_apll:
	clk_put(mout_mpll);
err_mout_mpll:
	clk_put(moutcore);
err_moutcore:
	clk_put(cpu_clk);

	pr_debug("%s: failed initialization\n", __func__);
	return -EINVAL;
}
Commit	Line	Data
a35c5051 JL	1	/*
	2	* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com
	4	*
	5	* EXYNOS4X12 - CPU frequency scaling support
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/module.h>
	13	#include <linux/kernel.h>
	14	#include <linux/err.h>
	15	#include <linux/clk.h>
	16	#include <linux/io.h>
	17	#include <linux/slab.h>
	18	#include <linux/cpufreq.h>
	19
c4aaa295	20	#include "exynos-cpufreq.h"
a35c5051	21
a35c5051 JL	22	static struct clk *cpu_clk;
	23	static struct clk *moutcore;
	24	static struct clk *mout_mpll;
	25	static struct clk *mout_apll;
	26
9d0554ff JC	27	static unsigned int exynos4x12_volt_table[] = {
	28	1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
	29	1000000, 987500, 975000, 950000, 925000, 900000, 900000
a35c5051 JL	30	};
a35c5051 JL	31
a35c5051	32	static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
7f4b0461 VK	33	{CPUFREQ_BOOST_FREQ, L0, 1500 * 1000},
	34	{0, L1, 1400 * 1000},
	35	{0, L2, 1300 * 1000},
	36	{0, L3, 1200 * 1000},
	37	{0, L4, 1100 * 1000},
	38	{0, L5, 1000 * 1000},
	39	{0, L6, 900 * 1000},
	40	{0, L7, 800 * 1000},
	41	{0, L8, 700 * 1000},
	42	{0, L9, 600 * 1000},
	43	{0, L10, 500 * 1000},
	44	{0, L11, 400 * 1000},
	45	{0, L12, 300 * 1000},
	46	{0, L13, 200 * 1000},
	47	{0, 0, CPUFREQ_TABLE_END},
a35c5051 JL	48	};
a35c5051 JL	49
9d0554ff	50	static struct apll_freq *apll_freq_4x12;
a35c5051	51
9d0554ff	52	static struct apll_freq apll_freq_4212[] = {
a35c5051	53	/*
9d0554ff JC	54	* values:
	55	* freq
	56	* clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
	57	* clock divider for COPY, HPM, RESERVED
	58	* PLL M, P, S
a35c5051	59	*/
9d0554ff JC	60	APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 250, 4, 0),
	61	APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 175, 3, 0),
	62	APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 325, 6, 0),
	63	APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 200, 4, 0),
	64	APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 2, 0, 275, 6, 0),
	65	APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 2, 0, 125, 3, 0),
	66	APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 150, 4, 0),
	67	APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 0),
	68	APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 175, 3, 1),
	69	APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 200, 4, 1),
	70	APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 125, 3, 1),
	71	APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 1),
	72	APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 2, 0, 200, 4, 2),
	73	APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 2, 0, 100, 3, 2),
a35c5051 JL	74	};
a35c5051 JL	75
9d0554ff	76	static struct apll_freq apll_freq_4412[] = {
a35c5051	77	/*
9d0554ff JC	78	* values:
	79	* freq
	80	* clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
	81	* clock divider for COPY, HPM, CORES
	82	* PLL M, P, S
a35c5051	83	*/
9d0554ff JC	84	APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 7, 250, 4, 0),
	85	APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 6, 175, 3, 0),
	86	APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 6, 325, 6, 0),
	87	APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 5, 200, 4, 0),
	88	APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 0, 5, 275, 6, 0),
	89	APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 0, 4, 125, 3, 0),
	90	APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 4, 150, 4, 0),
	91	APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 3, 100, 3, 0),
	92	APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 3, 175, 3, 1),
	93	APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 200, 4, 1),
	94	APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 125, 3, 1),
	95	APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 1, 100, 3, 1),
	96	APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 0, 1, 200, 4, 2),
	97	APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 0, 0, 100, 3, 2),
a35c5051 JL	98	};
	99
	100	static void exynos4x12_set_clkdiv(unsigned int div_index)
	101	{
	102	unsigned int tmp;
	103	unsigned int stat_cpu1;
	104
	105	/* Change Divider - CPU0 */
	106
9d0554ff	107	tmp = apll_freq_4x12[div_index].clk_div_cpu0;
a35c5051 JL	108
	109	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
	110
	111	while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
	112	cpu_relax();
	113
	114	/* Change Divider - CPU1 */
9d0554ff	115	tmp = apll_freq_4x12[div_index].clk_div_cpu1;
a35c5051 JL	116
	117	__raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
	118	if (soc_is_exynos4212())
	119	stat_cpu1 = 0x11;
	120	else
	121	stat_cpu1 = 0x111;
	122
	123	while (__raw_readl(EXYNOS4_CLKDIV_STATCPU1) & stat_cpu1)
	124	cpu_relax();
	125	}
	126
	127	static void exynos4x12_set_apll(unsigned int index)
	128	{
cf467155	129	unsigned int tmp, freq = apll_freq_4x12[index].freq;
a35c5051	130
cf467155	131	/* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
a35c5051 JL	132	clk_set_parent(moutcore, mout_mpll);
	133
	134	do {
	135	cpu_relax();
	136	tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
	137	>> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
	138	tmp &= 0x7;
	139	} while (tmp != 0x2);
	140
cf467155	141	clk_set_rate(mout_apll, freq * 1000);
a35c5051	142
cf467155	143	/* MUX_CORE_SEL = APLL */
a35c5051 JL	144	clk_set_parent(moutcore, mout_apll);
	145
	146	do {
	147	cpu_relax();
	148	tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
	149	tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
	150	} while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
	151	}
	152
a35c5051 JL	153	static void exynos4x12_set_frequency(unsigned int old_index,
	154	unsigned int new_index)
	155	{
a35c5051	156	if (old_index > new_index) {
cf467155 LM	157	exynos4x12_set_clkdiv(new_index);
cf467155 LM	158	exynos4x12_set_apll(new_index);
a35c5051	159	} else if (old_index < new_index) {
cf467155 LM	160	exynos4x12_set_apll(new_index);
cf467155 LM	161	exynos4x12_set_clkdiv(new_index);
a35c5051 JL	162	}
	163	}
	164
a35c5051 JL	165	int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
a35c5051 JL	166	{
a35c5051 JL	167	unsigned long rate;
a35c5051 JL	168
a35c5051 JL	169	cpu_clk = clk_get(NULL, "armclk");
	170	if (IS_ERR(cpu_clk))
	171	return PTR_ERR(cpu_clk);
	172
	173	moutcore = clk_get(NULL, "moutcore");
	174	if (IS_ERR(moutcore))
	175	goto err_moutcore;
	176
	177	mout_mpll = clk_get(NULL, "mout_mpll");
	178	if (IS_ERR(mout_mpll))
	179	goto err_mout_mpll;
	180
	181	rate = clk_get_rate(mout_mpll) / 1000;
	182
	183	mout_apll = clk_get(NULL, "mout_apll");
	184	if (IS_ERR(mout_apll))
	185	goto err_mout_apll;
	186
9d0554ff JC	187	if (soc_is_exynos4212())
	188	apll_freq_4x12 = apll_freq_4212;
	189	else
	190	apll_freq_4x12 = apll_freq_4412;
a35c5051 JL	191
a35c5051 JL	192	info->mpll_freq_khz = rate;
9d0554ff	193	/* 800Mhz */
a35c5051	194	info->pll_safe_idx = L7;
a35c5051 JL	195	info->cpu_clk = cpu_clk;
	196	info->volt_table = exynos4x12_volt_table;
	197	info->freq_table = exynos4x12_freq_table;
	198	info->set_freq = exynos4x12_set_frequency;
a35c5051 JL	199
	200	return 0;
	201
	202	err_mout_apll:
	203	clk_put(mout_mpll);
	204	err_mout_mpll:
	205	clk_put(moutcore);
	206	err_moutcore:
	207	clk_put(cpu_clk);
	208
	209	pr_debug("%s: failed initialization\n", __func__);
	210	return -EINVAL;
	211	}