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562a6cbe JL |
1 | /* |
2 | * Copyright (c) 2010-20122Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com | |
4 | * | |
5 | * EXYNOS5250 - CPU frequency scaling support | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/cpufreq.h> | |
4c8d8193 TF |
19 | #include <linux/of.h> |
20 | #include <linux/of_address.h> | |
c4aaa295 KK |
21 | |
22 | #include "exynos-cpufreq.h" | |
562a6cbe | 23 | |
562a6cbe JL |
24 | static struct clk *cpu_clk; |
25 | static struct clk *moutcore; | |
26 | static struct clk *mout_mpll; | |
27 | static struct clk *mout_apll; | |
4c8d8193 | 28 | static struct exynos_dvfs_info *cpufreq; |
562a6cbe | 29 | |
9d0554ff JC |
30 | static unsigned int exynos5250_volt_table[] = { |
31 | 1300000, 1250000, 1225000, 1200000, 1150000, | |
32 | 1125000, 1100000, 1075000, 1050000, 1025000, | |
33 | 1012500, 1000000, 975000, 950000, 937500, | |
34 | 925000 | |
562a6cbe JL |
35 | }; |
36 | ||
562a6cbe | 37 | static struct cpufreq_frequency_table exynos5250_freq_table[] = { |
7f4b0461 VK |
38 | {0, L0, 1700 * 1000}, |
39 | {0, L1, 1600 * 1000}, | |
40 | {0, L2, 1500 * 1000}, | |
41 | {0, L3, 1400 * 1000}, | |
42 | {0, L4, 1300 * 1000}, | |
43 | {0, L5, 1200 * 1000}, | |
44 | {0, L6, 1100 * 1000}, | |
45 | {0, L7, 1000 * 1000}, | |
46 | {0, L8, 900 * 1000}, | |
47 | {0, L9, 800 * 1000}, | |
48 | {0, L10, 700 * 1000}, | |
49 | {0, L11, 600 * 1000}, | |
50 | {0, L12, 500 * 1000}, | |
51 | {0, L13, 400 * 1000}, | |
52 | {0, L14, 300 * 1000}, | |
53 | {0, L15, 200 * 1000}, | |
54 | {0, 0, CPUFREQ_TABLE_END}, | |
562a6cbe JL |
55 | }; |
56 | ||
9d0554ff | 57 | static struct apll_freq apll_freq_5250[] = { |
562a6cbe | 58 | /* |
9d0554ff JC |
59 | * values: |
60 | * freq | |
61 | * clock divider for ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2 | |
62 | * clock divider for COPY, HPM, RESERVED | |
63 | * PLL M, P, S | |
562a6cbe | 64 | */ |
9d0554ff JC |
65 | APLL_FREQ(1700, 0, 3, 7, 7, 7, 3, 5, 0, 0, 2, 0, 425, 6, 0), |
66 | APLL_FREQ(1600, 0, 3, 7, 7, 7, 1, 4, 0, 0, 2, 0, 200, 3, 0), | |
67 | APLL_FREQ(1500, 0, 2, 7, 7, 7, 1, 4, 0, 0, 2, 0, 250, 4, 0), | |
68 | APLL_FREQ(1400, 0, 2, 7, 7, 6, 1, 4, 0, 0, 2, 0, 175, 3, 0), | |
69 | APLL_FREQ(1300, 0, 2, 7, 7, 6, 1, 3, 0, 0, 2, 0, 325, 6, 0), | |
70 | APLL_FREQ(1200, 0, 2, 7, 7, 5, 1, 3, 0, 0, 2, 0, 200, 4, 0), | |
71 | APLL_FREQ(1100, 0, 3, 7, 7, 5, 1, 3, 0, 0, 2, 0, 275, 6, 0), | |
72 | APLL_FREQ(1000, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 125, 3, 0), | |
73 | APLL_FREQ(900, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 150, 4, 0), | |
74 | APLL_FREQ(800, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 100, 3, 0), | |
75 | APLL_FREQ(700, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 175, 3, 1), | |
76 | APLL_FREQ(600, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 200, 4, 1), | |
77 | APLL_FREQ(500, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 125, 3, 1), | |
78 | APLL_FREQ(400, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 100, 3, 1), | |
79 | APLL_FREQ(300, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 200, 4, 2), | |
80 | APLL_FREQ(200, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 100, 3, 2), | |
562a6cbe JL |
81 | }; |
82 | ||
83 | static void set_clkdiv(unsigned int div_index) | |
84 | { | |
85 | unsigned int tmp; | |
86 | ||
87 | /* Change Divider - CPU0 */ | |
88 | ||
9d0554ff | 89 | tmp = apll_freq_5250[div_index].clk_div_cpu0; |
562a6cbe | 90 | |
4c8d8193 | 91 | __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU0); |
562a6cbe | 92 | |
4c8d8193 TF |
93 | while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU0) |
94 | & 0x11111111) | |
562a6cbe JL |
95 | cpu_relax(); |
96 | ||
97 | /* Change Divider - CPU1 */ | |
9d0554ff | 98 | tmp = apll_freq_5250[div_index].clk_div_cpu1; |
562a6cbe | 99 | |
4c8d8193 | 100 | __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS5_CLKDIV_CPU1); |
562a6cbe | 101 | |
4c8d8193 | 102 | while (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKDIV_STATCPU1) & 0x11) |
562a6cbe JL |
103 | cpu_relax(); |
104 | } | |
105 | ||
26ab1c62 | 106 | static void set_apll(unsigned int index) |
562a6cbe | 107 | { |
26ab1c62 SK |
108 | unsigned int tmp; |
109 | unsigned int freq = apll_freq_5250[index].freq; | |
562a6cbe | 110 | |
26ab1c62 | 111 | /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ |
562a6cbe JL |
112 | clk_set_parent(moutcore, mout_mpll); |
113 | ||
114 | do { | |
115 | cpu_relax(); | |
4c8d8193 TF |
116 | tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU) |
117 | >> 16); | |
562a6cbe JL |
118 | tmp &= 0x7; |
119 | } while (tmp != 0x2); | |
120 | ||
26ab1c62 | 121 | clk_set_rate(mout_apll, freq * 1000); |
562a6cbe | 122 | |
26ab1c62 | 123 | /* MUX_CORE_SEL = APLL */ |
562a6cbe JL |
124 | clk_set_parent(moutcore, mout_apll); |
125 | ||
126 | do { | |
127 | cpu_relax(); | |
4c8d8193 | 128 | tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS5_CLKMUX_STATCPU); |
562a6cbe JL |
129 | tmp &= (0x7 << 16); |
130 | } while (tmp != (0x1 << 16)); | |
562a6cbe JL |
131 | } |
132 | ||
133 | static void exynos5250_set_frequency(unsigned int old_index, | |
134 | unsigned int new_index) | |
135 | { | |
562a6cbe | 136 | if (old_index > new_index) { |
26ab1c62 SK |
137 | set_clkdiv(new_index); |
138 | set_apll(new_index); | |
562a6cbe | 139 | } else if (old_index < new_index) { |
26ab1c62 SK |
140 | set_apll(new_index); |
141 | set_clkdiv(new_index); | |
562a6cbe JL |
142 | } |
143 | } | |
144 | ||
562a6cbe JL |
145 | int exynos5250_cpufreq_init(struct exynos_dvfs_info *info) |
146 | { | |
4c8d8193 | 147 | struct device_node *np; |
562a6cbe JL |
148 | unsigned long rate; |
149 | ||
4c8d8193 TF |
150 | /* |
151 | * HACK: This is a temporary workaround to get access to clock | |
152 | * controller registers directly and remove static mappings and | |
153 | * dependencies on platform headers. It is necessary to enable | |
154 | * Exynos multi-platform support and will be removed together with | |
155 | * this whole driver as soon as Exynos gets migrated to use | |
156 | * cpufreq-cpu0 driver. | |
157 | */ | |
158 | np = of_find_compatible_node(NULL, NULL, "samsung,exynos5250-clock"); | |
159 | if (!np) { | |
160 | pr_err("%s: failed to find clock controller DT node\n", | |
161 | __func__); | |
162 | return -ENODEV; | |
163 | } | |
164 | ||
165 | info->cmu_regs = of_iomap(np, 0); | |
166 | if (!info->cmu_regs) { | |
167 | pr_err("%s: failed to map CMU registers\n", __func__); | |
168 | return -EFAULT; | |
169 | } | |
170 | ||
562a6cbe JL |
171 | cpu_clk = clk_get(NULL, "armclk"); |
172 | if (IS_ERR(cpu_clk)) | |
173 | return PTR_ERR(cpu_clk); | |
174 | ||
175 | moutcore = clk_get(NULL, "mout_cpu"); | |
176 | if (IS_ERR(moutcore)) | |
177 | goto err_moutcore; | |
178 | ||
179 | mout_mpll = clk_get(NULL, "mout_mpll"); | |
180 | if (IS_ERR(mout_mpll)) | |
181 | goto err_mout_mpll; | |
182 | ||
183 | rate = clk_get_rate(mout_mpll) / 1000; | |
184 | ||
185 | mout_apll = clk_get(NULL, "mout_apll"); | |
186 | if (IS_ERR(mout_apll)) | |
187 | goto err_mout_apll; | |
188 | ||
562a6cbe | 189 | info->mpll_freq_khz = rate; |
562a6cbe JL |
190 | /* 800Mhz */ |
191 | info->pll_safe_idx = L9; | |
562a6cbe JL |
192 | info->cpu_clk = cpu_clk; |
193 | info->volt_table = exynos5250_volt_table; | |
194 | info->freq_table = exynos5250_freq_table; | |
195 | info->set_freq = exynos5250_set_frequency; | |
562a6cbe | 196 | |
4c8d8193 TF |
197 | cpufreq = info; |
198 | ||
562a6cbe JL |
199 | return 0; |
200 | ||
201 | err_mout_apll: | |
202 | clk_put(mout_mpll); | |
203 | err_mout_mpll: | |
204 | clk_put(moutcore); | |
205 | err_moutcore: | |
206 | clk_put(cpu_clk); | |
207 | ||
208 | pr_err("%s: failed initialization\n", __func__); | |
209 | return -EINVAL; | |
210 | } |