[deliverable/linux.git] / drivers / cpufreq / imx6q-cpufreq.c

/*
 * Copyright (C) 2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/cpu.h>
#include <linux/cpufreq.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pm_opp.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>

#define PU_SOC_VOLTAGE_NORMAL	1250000
#define PU_SOC_VOLTAGE_HIGH	1275000
#define FREQ_1P2_GHZ		1200000000

static struct regulator *arm_reg;
static struct regulator *pu_reg;
static struct regulator *soc_reg;

static struct clk *arm_clk;
static struct clk *pll1_sys_clk;
static struct clk *pll1_sw_clk;
static struct clk *step_clk;
static struct clk *pll2_pfd2_396m_clk;

static struct device *cpu_dev;
static struct cpufreq_frequency_table *freq_table;
static unsigned int transition_latency;

static u32 *imx6_soc_volt;
static u32 soc_opp_count;

static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
{
	struct dev_pm_opp *opp;
	unsigned long freq_hz, volt, volt_old;
	unsigned int old_freq, new_freq;
	int ret;

	new_freq = freq_table[index].frequency;
	freq_hz = new_freq * 1000;
	old_freq = clk_get_rate(arm_clk) / 1000;

	rcu_read_lock();
	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
	if (IS_ERR(opp)) {
		rcu_read_unlock();
		dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
		return PTR_ERR(opp);
	}

	volt = dev_pm_opp_get_voltage(opp);
	rcu_read_unlock();
	volt_old = regulator_get_voltage(arm_reg);

	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
		old_freq / 1000, volt_old / 1000,
		new_freq / 1000, volt / 1000);

	/* scaling up?  scale voltage before frequency */
	if (new_freq > old_freq) {
		if (!IS_ERR(pu_reg)) {
			ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
			if (ret) {
				dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
				return ret;
			}
		}
		ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
		if (ret) {
			dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
			return ret;
		}
		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
		if (ret) {
			dev_err(cpu_dev,
				"failed to scale vddarm up: %d\n", ret);
			return ret;
		}
	}

	/*
	 * The setpoints are selected per PLL/PDF frequencies, so we need to
	 * reprogram PLL for frequency scaling.  The procedure of reprogramming
	 * PLL1 is as below.
	 *
	 *  - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
	 *  - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
	 *  - Disable pll2_pfd2_396m_clk
	 */
	clk_set_parent(step_clk, pll2_pfd2_396m_clk);
	clk_set_parent(pll1_sw_clk, step_clk);
	if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
		clk_set_rate(pll1_sys_clk, new_freq * 1000);
		clk_set_parent(pll1_sw_clk, pll1_sys_clk);
	}

	/* Ensure the arm clock divider is what we expect */
	ret = clk_set_rate(arm_clk, new_freq * 1000);
	if (ret) {
		dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
		regulator_set_voltage_tol(arm_reg, volt_old, 0);
		return ret;
	}

	/* scaling down?  scale voltage after frequency */
	if (new_freq < old_freq) {
		ret = regulator_set_voltage_tol(arm_reg, volt, 0);
		if (ret) {
			dev_warn(cpu_dev,
				 "failed to scale vddarm down: %d\n", ret);
			ret = 0;
		}
		ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
		if (ret) {
			dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
			ret = 0;
		}
		if (!IS_ERR(pu_reg)) {
			ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
			if (ret) {
				dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
				ret = 0;
			}
		}
	}

	return 0;
}

static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
{
	policy->clk = arm_clk;
	return cpufreq_generic_init(policy, freq_table, transition_latency);
}

static struct cpufreq_driver imx6q_cpufreq_driver = {
	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
	.verify = cpufreq_generic_frequency_table_verify,
	.target_index = imx6q_set_target,
	.get = cpufreq_generic_get,
	.init = imx6q_cpufreq_init,
	.name = "imx6q-cpufreq",
	.attr = cpufreq_generic_attr,
};

static int imx6q_cpufreq_probe(struct platform_device *pdev)
{
	struct device_node *np;
	struct dev_pm_opp *opp;
	unsigned long min_volt, max_volt;
	int num, ret;
	const struct property *prop;
	const __be32 *val;
	u32 nr, i, j;

	cpu_dev = get_cpu_device(0);
	if (!cpu_dev) {
		pr_err("failed to get cpu0 device\n");
		return -ENODEV;
	}

	np = of_node_get(cpu_dev->of_node);
	if (!np) {
		dev_err(cpu_dev, "failed to find cpu0 node\n");
		return -ENOENT;
	}

	arm_clk = clk_get(cpu_dev, "arm");
	pll1_sys_clk = clk_get(cpu_dev, "pll1_sys");
	pll1_sw_clk = clk_get(cpu_dev, "pll1_sw");
	step_clk = clk_get(cpu_dev, "step");
	pll2_pfd2_396m_clk = clk_get(cpu_dev, "pll2_pfd2_396m");
	if (IS_ERR(arm_clk) || IS_ERR(pll1_sys_clk) || IS_ERR(pll1_sw_clk) ||
	    IS_ERR(step_clk) || IS_ERR(pll2_pfd2_396m_clk)) {
		dev_err(cpu_dev, "failed to get clocks\n");
		ret = -ENOENT;
		goto put_clk;
	}

	arm_reg = regulator_get(cpu_dev, "arm");
	pu_reg = regulator_get_optional(cpu_dev, "pu");
	soc_reg = regulator_get(cpu_dev, "soc");
	if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
		dev_err(cpu_dev, "failed to get regulators\n");
		ret = -ENOENT;
		goto put_reg;
	}

	/*
	 * We expect an OPP table supplied by platform.
	 * Just, incase the platform did not supply the OPP
	 * table, it will try to get it.
	 */
	num = dev_pm_opp_get_opp_count(cpu_dev);
	if (num < 0) {
		ret = of_init_opp_table(cpu_dev);
		if (ret < 0) {
			dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
			goto put_reg;
		}

		num = dev_pm_opp_get_opp_count(cpu_dev);
		if (num < 0) {
			ret = num;
			dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
			goto put_reg;
		}
	}

	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
	if (ret) {
		dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
		goto put_reg;
	}

	/* Make imx6_soc_volt array's size same as arm opp number */
	imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(*imx6_soc_volt) * num, GFP_KERNEL);
	if (imx6_soc_volt == NULL) {
		ret = -ENOMEM;
		goto free_freq_table;
	}

	prop = of_find_property(np, "fsl,soc-operating-points", NULL);
	if (!prop || !prop->value)
		goto soc_opp_out;

	/*
	 * Each OPP is a set of tuples consisting of frequency and
	 * voltage like <freq-kHz vol-uV>.
	 */
	nr = prop->length / sizeof(u32);
	if (nr % 2 || (nr / 2) < num)
		goto soc_opp_out;

	for (j = 0; j < num; j++) {
		val = prop->value;
		for (i = 0; i < nr / 2; i++) {
			unsigned long freq = be32_to_cpup(val++);
			unsigned long volt = be32_to_cpup(val++);
			if (freq_table[j].frequency == freq) {
				imx6_soc_volt[soc_opp_count++] = volt;
				break;
			}
		}
	}

soc_opp_out:
	/* use fixed soc opp volt if no valid soc opp info found in dtb */
	if (soc_opp_count != num) {
		dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
		for (j = 0; j < num; j++)
			imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
		if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
			imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
	}

	if (of_property_read_u32(np, "clock-latency", &transition_latency))
		transition_latency = CPUFREQ_ETERNAL;

	/*
	 * Calculate the ramp time for max voltage change in the
	 * VDDSOC and VDDPU regulators.
	 */
	ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
	if (ret > 0)
		transition_latency += ret * 1000;
	if (!IS_ERR(pu_reg)) {
		ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
		if (ret > 0)
			transition_latency += ret * 1000;
	}

	/*
	 * OPP is maintained in order of increasing frequency, and
	 * freq_table initialised from OPP is therefore sorted in the
	 * same order.
	 */
	rcu_read_lock();
	opp = dev_pm_opp_find_freq_exact(cpu_dev,
				  freq_table[0].frequency * 1000, true);
	min_volt = dev_pm_opp_get_voltage(opp);
	opp = dev_pm_opp_find_freq_exact(cpu_dev,
				  freq_table[--num].frequency * 1000, true);
	max_volt = dev_pm_opp_get_voltage(opp);
	rcu_read_unlock();
	ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
	if (ret > 0)
		transition_latency += ret * 1000;

	ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
	if (ret) {
		dev_err(cpu_dev, "failed register driver: %d\n", ret);
		goto free_freq_table;
	}

	of_node_put(np);
	return 0;

free_freq_table:
	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
put_reg:
	if (!IS_ERR(arm_reg))
		regulator_put(arm_reg);
	if (!IS_ERR(pu_reg))
		regulator_put(pu_reg);
	if (!IS_ERR(soc_reg))
		regulator_put(soc_reg);
put_clk:
	if (!IS_ERR(arm_clk))
		clk_put(arm_clk);
	if (!IS_ERR(pll1_sys_clk))
		clk_put(pll1_sys_clk);
	if (!IS_ERR(pll1_sw_clk))
		clk_put(pll1_sw_clk);
	if (!IS_ERR(step_clk))
		clk_put(step_clk);
	if (!IS_ERR(pll2_pfd2_396m_clk))
		clk_put(pll2_pfd2_396m_clk);
	of_node_put(np);
	return ret;
}

static int imx6q_cpufreq_remove(struct platform_device *pdev)
{
	cpufreq_unregister_driver(&imx6q_cpufreq_driver);
	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
	regulator_put(arm_reg);
	if (!IS_ERR(pu_reg))
		regulator_put(pu_reg);
	regulator_put(soc_reg);
	clk_put(arm_clk);
	clk_put(pll1_sys_clk);
	clk_put(pll1_sw_clk);
	clk_put(step_clk);
	clk_put(pll2_pfd2_396m_clk);

	return 0;
}

static struct platform_driver imx6q_cpufreq_platdrv = {
	.driver = {
		.name	= "imx6q-cpufreq",
		.owner	= THIS_MODULE,
	},
	.probe		= imx6q_cpufreq_probe,
	.remove		= imx6q_cpufreq_remove,
};
module_platform_driver(imx6q_cpufreq_platdrv);

MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1dd538f0 SG	1	/*
	2	* Copyright (C) 2013 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	#include <linux/clk.h>
b494b48d	10	#include <linux/cpu.h>
1dd538f0	11	#include <linux/cpufreq.h>
1dd538f0 SG	12	#include <linux/err.h>
	13	#include <linux/module.h>
	14	#include <linux/of.h>
e4db1c74	15	#include <linux/pm_opp.h>
1dd538f0 SG	16	#include <linux/platform_device.h>
	17	#include <linux/regulator/consumer.h>
	18
	19	#define PU_SOC_VOLTAGE_NORMAL 1250000
	20	#define PU_SOC_VOLTAGE_HIGH 1275000
	21	#define FREQ_1P2_GHZ 1200000000
	22
	23	static struct regulator *arm_reg;
	24	static struct regulator *pu_reg;
	25	static struct regulator *soc_reg;
	26
	27	static struct clk *arm_clk;
	28	static struct clk *pll1_sys_clk;
	29	static struct clk *pll1_sw_clk;
	30	static struct clk *step_clk;
	31	static struct clk *pll2_pfd2_396m_clk;
	32
	33	static struct device *cpu_dev;
	34	static struct cpufreq_frequency_table *freq_table;
	35	static unsigned int transition_latency;
	36
b4573d1d AH	37	static u32 *imx6_soc_volt;
	38	static u32 soc_opp_count;
	39
9c0ebcf7	40	static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
1dd538f0	41	{
47d43ba7	42	struct dev_pm_opp *opp;
1dd538f0	43	unsigned long freq_hz, volt, volt_old;
d4019f0a	44	unsigned int old_freq, new_freq;
1dd538f0 SG	45	int ret;
1dd538f0 SG	46
d4019f0a VK	47	new_freq = freq_table[index].frequency;
	48	freq_hz = new_freq * 1000;
	49	old_freq = clk_get_rate(arm_clk) / 1000;
1dd538f0	50
1dd538f0	51	rcu_read_lock();
5d4879cd	52	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
1dd538f0 SG	53	if (IS_ERR(opp)) {
	54	rcu_read_unlock();
	55	dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
	56	return PTR_ERR(opp);
	57	}
	58
5d4879cd	59	volt = dev_pm_opp_get_voltage(opp);
1dd538f0 SG	60	rcu_read_unlock();
	61	volt_old = regulator_get_voltage(arm_reg);
	62
	63	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
d4019f0a VK	64	old_freq / 1000, volt_old / 1000,
d4019f0a VK	65	new_freq / 1000, volt / 1000);
5a571c35	66
1dd538f0	67	/* scaling up? scale voltage before frequency */
d4019f0a	68	if (new_freq > old_freq) {
22d0628a AH	69	if (!IS_ERR(pu_reg)) {
	70	ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
	71	if (ret) {
	72	dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
	73	return ret;
	74	}
b4573d1d AH	75	}
	76	ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
	77	if (ret) {
	78	dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
	79	return ret;
	80	}
1dd538f0 SG	81	ret = regulator_set_voltage_tol(arm_reg, volt, 0);
	82	if (ret) {
	83	dev_err(cpu_dev,
	84	"failed to scale vddarm up: %d\n", ret);
d4019f0a	85	return ret;
1dd538f0	86	}
1dd538f0 SG	87	}
	88
	89	/*
	90	* The setpoints are selected per PLL/PDF frequencies, so we need to
	91	* reprogram PLL for frequency scaling. The procedure of reprogramming
	92	* PLL1 is as below.
	93	*
	94	* - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
	95	* - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
	96	* - Disable pll2_pfd2_396m_clk
	97	*/
1dd538f0 SG	98	clk_set_parent(step_clk, pll2_pfd2_396m_clk);
	99	clk_set_parent(pll1_sw_clk, step_clk);
	100	if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
d4019f0a	101	clk_set_rate(pll1_sys_clk, new_freq * 1000);
1dd538f0	102	clk_set_parent(pll1_sw_clk, pll1_sys_clk);
1dd538f0 SG	103	}
	104
	105	/* Ensure the arm clock divider is what we expect */
d4019f0a	106	ret = clk_set_rate(arm_clk, new_freq * 1000);
1dd538f0 SG	107	if (ret) {
	108	dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
	109	regulator_set_voltage_tol(arm_reg, volt_old, 0);
d4019f0a	110	return ret;
1dd538f0 SG	111	}
	112
	113	/* scaling down? scale voltage after frequency */
d4019f0a	114	if (new_freq < old_freq) {
1dd538f0	115	ret = regulator_set_voltage_tol(arm_reg, volt, 0);
5a571c35	116	if (ret) {
1dd538f0 SG	117	dev_warn(cpu_dev,
1dd538f0 SG	118	"failed to scale vddarm down: %d\n", ret);
5a571c35 VK	119	ret = 0;
5a571c35 VK	120	}
b4573d1d AH	121	ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
	122	if (ret) {
	123	dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
	124	ret = 0;
	125	}
22d0628a AH	126	if (!IS_ERR(pu_reg)) {
	127	ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
	128	if (ret) {
	129	dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
	130	ret = 0;
	131	}
1dd538f0 SG	132	}
	133	}
	134
d4019f0a	135	return 0;
1dd538f0 SG	136	}
	137
	138	static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
	139	{
652ed95d	140	policy->clk = arm_clk;
17922ddd	141	return cpufreq_generic_init(policy, freq_table, transition_latency);
1dd538f0 SG	142	}
1dd538f0 SG	143
1dd538f0	144	static struct cpufreq_driver imx6q_cpufreq_driver = {
ae6b4271	145	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
4f6ba385	146	.verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7	147	.target_index = imx6q_set_target,
652ed95d	148	.get = cpufreq_generic_get,
1dd538f0	149	.init = imx6q_cpufreq_init,
1dd538f0	150	.name = "imx6q-cpufreq",
4f6ba385	151	.attr = cpufreq_generic_attr,
1dd538f0 SG	152	};
	153
	154	static int imx6q_cpufreq_probe(struct platform_device *pdev)
	155	{
	156	struct device_node *np;
47d43ba7	157	struct dev_pm_opp *opp;
1dd538f0 SG	158	unsigned long min_volt, max_volt;
1dd538f0 SG	159	int num, ret;
b4573d1d AH	160	const struct property *prop;
	161	const __be32 *val;
	162	u32 nr, i, j;
1dd538f0	163
b494b48d SK	164	cpu_dev = get_cpu_device(0);
	165	if (!cpu_dev) {
	166	pr_err("failed to get cpu0 device\n");
	167	return -ENODEV;
	168	}
1dd538f0	169
cdc58d60	170	np = of_node_get(cpu_dev->of_node);
1dd538f0 SG	171	if (!np) {
	172	dev_err(cpu_dev, "failed to find cpu0 node\n");
	173	return -ENOENT;
	174	}
	175
f8269c19 PZ	176	arm_clk = clk_get(cpu_dev, "arm");
	177	pll1_sys_clk = clk_get(cpu_dev, "pll1_sys");
	178	pll1_sw_clk = clk_get(cpu_dev, "pll1_sw");
	179	step_clk = clk_get(cpu_dev, "step");
	180	pll2_pfd2_396m_clk = clk_get(cpu_dev, "pll2_pfd2_396m");
1dd538f0 SG	181	if (IS_ERR(arm_clk) \|\| IS_ERR(pll1_sys_clk) \|\| IS_ERR(pll1_sw_clk) \|\|
	182	IS_ERR(step_clk) \|\| IS_ERR(pll2_pfd2_396m_clk)) {
	183	dev_err(cpu_dev, "failed to get clocks\n");
	184	ret = -ENOENT;
f8269c19	185	goto put_clk;
1dd538f0 SG	186	}
1dd538f0 SG	187
f8269c19	188	arm_reg = regulator_get(cpu_dev, "arm");
22d0628a	189	pu_reg = regulator_get_optional(cpu_dev, "pu");
f8269c19	190	soc_reg = regulator_get(cpu_dev, "soc");
22d0628a	191	if (IS_ERR(arm_reg) \|\| IS_ERR(soc_reg)) {
1dd538f0 SG	192	dev_err(cpu_dev, "failed to get regulators\n");
1dd538f0 SG	193	ret = -ENOENT;
f8269c19	194	goto put_reg;
1dd538f0 SG	195	}
1dd538f0 SG	196
20b7cbe2 JT	197	/*
	198	* We expect an OPP table supplied by platform.
	199	* Just, incase the platform did not supply the OPP
	200	* table, it will try to get it.
	201	*/
5d4879cd	202	num = dev_pm_opp_get_opp_count(cpu_dev);
1dd538f0	203	if (num < 0) {
20b7cbe2 JT	204	ret = of_init_opp_table(cpu_dev);
	205	if (ret < 0) {
	206	dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
f8269c19	207	goto put_reg;
20b7cbe2 JT	208	}
	209
	210	num = dev_pm_opp_get_opp_count(cpu_dev);
	211	if (num < 0) {
	212	ret = num;
	213	dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
f8269c19	214	goto put_reg;
20b7cbe2	215	}
1dd538f0 SG	216	}
1dd538f0 SG	217
5d4879cd	218	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
1dd538f0 SG	219	if (ret) {
1dd538f0 SG	220	dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
f8269c19	221	goto put_reg;
1dd538f0 SG	222	}
1dd538f0 SG	223
b4573d1d AH	224	/* Make imx6_soc_volt array's size same as arm opp number */
	225	imx6_soc_volt = devm_kzalloc(cpu_dev, sizeof(imx6_soc_volt) num, GFP_KERNEL);
	226	if (imx6_soc_volt == NULL) {
	227	ret = -ENOMEM;
	228	goto free_freq_table;
	229	}
	230
	231	prop = of_find_property(np, "fsl,soc-operating-points", NULL);
	232	if (!prop \|\| !prop->value)
	233	goto soc_opp_out;
	234
	235	/*
	236	* Each OPP is a set of tuples consisting of frequency and
	237	* voltage like <freq-kHz vol-uV>.
	238	*/
	239	nr = prop->length / sizeof(u32);
	240	if (nr % 2 \|\| (nr / 2) < num)
	241	goto soc_opp_out;
	242
	243	for (j = 0; j < num; j++) {
	244	val = prop->value;
	245	for (i = 0; i < nr / 2; i++) {
	246	unsigned long freq = be32_to_cpup(val++);
	247	unsigned long volt = be32_to_cpup(val++);
	248	if (freq_table[j].frequency == freq) {
	249	imx6_soc_volt[soc_opp_count++] = volt;
	250	break;
	251	}
	252	}
	253	}
	254
	255	soc_opp_out:
	256	/* use fixed soc opp volt if no valid soc opp info found in dtb */
	257	if (soc_opp_count != num) {
	258	dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
	259	for (j = 0; j < num; j++)
	260	imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
	261	if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
	262	imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
	263	}
	264
1dd538f0 SG	265	if (of_property_read_u32(np, "clock-latency", &transition_latency))
	266	transition_latency = CPUFREQ_ETERNAL;
	267
b4573d1d AH	268	/*
	269	* Calculate the ramp time for max voltage change in the
	270	* VDDSOC and VDDPU regulators.
	271	*/
	272	ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
	273	if (ret > 0)
	274	transition_latency += ret * 1000;
22d0628a AH	275	if (!IS_ERR(pu_reg)) {
	276	ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
	277	if (ret > 0)
	278	transition_latency += ret * 1000;
	279	}
b4573d1d	280
1dd538f0 SG	281	/*
	282	* OPP is maintained in order of increasing frequency, and
	283	* freq_table initialised from OPP is therefore sorted in the
	284	* same order.
	285	*/
	286	rcu_read_lock();
5d4879cd	287	opp = dev_pm_opp_find_freq_exact(cpu_dev,
1dd538f0	288	freq_table[0].frequency * 1000, true);
5d4879cd NM	289	min_volt = dev_pm_opp_get_voltage(opp);
5d4879cd NM	290	opp = dev_pm_opp_find_freq_exact(cpu_dev,
1dd538f0	291	freq_table[--num].frequency * 1000, true);
5d4879cd	292	max_volt = dev_pm_opp_get_voltage(opp);
1dd538f0 SG	293	rcu_read_unlock();
	294	ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
	295	if (ret > 0)
	296	transition_latency += ret * 1000;
	297
1dd538f0 SG	298	ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
	299	if (ret) {
	300	dev_err(cpu_dev, "failed register driver: %d\n", ret);
	301	goto free_freq_table;
	302	}
	303
	304	of_node_put(np);
	305	return 0;
	306
	307	free_freq_table:
5d4879cd	308	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
f8269c19 PZ	309	put_reg:
	310	if (!IS_ERR(arm_reg))
	311	regulator_put(arm_reg);
	312	if (!IS_ERR(pu_reg))
	313	regulator_put(pu_reg);
	314	if (!IS_ERR(soc_reg))
	315	regulator_put(soc_reg);
	316	put_clk:
	317	if (!IS_ERR(arm_clk))
	318	clk_put(arm_clk);
	319	if (!IS_ERR(pll1_sys_clk))
	320	clk_put(pll1_sys_clk);
	321	if (!IS_ERR(pll1_sw_clk))
	322	clk_put(pll1_sw_clk);
	323	if (!IS_ERR(step_clk))
	324	clk_put(step_clk);
	325	if (!IS_ERR(pll2_pfd2_396m_clk))
	326	clk_put(pll2_pfd2_396m_clk);
1dd538f0 SG	327	of_node_put(np);
	328	return ret;
	329	}
	330
	331	static int imx6q_cpufreq_remove(struct platform_device *pdev)
	332	{
	333	cpufreq_unregister_driver(&imx6q_cpufreq_driver);
5d4879cd	334	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
f8269c19	335	regulator_put(arm_reg);
22d0628a AH	336	if (!IS_ERR(pu_reg))
22d0628a AH	337	regulator_put(pu_reg);
f8269c19 PZ	338	regulator_put(soc_reg);
	339	clk_put(arm_clk);
	340	clk_put(pll1_sys_clk);
	341	clk_put(pll1_sw_clk);
	342	clk_put(step_clk);
	343	clk_put(pll2_pfd2_396m_clk);
1dd538f0 SG	344
	345	return 0;
	346	}
	347
	348	static struct platform_driver imx6q_cpufreq_platdrv = {
	349	.driver = {
	350	.name = "imx6q-cpufreq",
	351	.owner = THIS_MODULE,
	352	},
	353	.probe = imx6q_cpufreq_probe,
	354	.remove = imx6q_cpufreq_remove,
	355	};
	356	module_platform_driver(imx6q_cpufreq_platdrv);
	357
	358	MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
	359	MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
	360	MODULE_LICENSE("GPL");