[deliverable/linux.git] / drivers / cpufreq / integrator-cpufreq.c

/*
 *  Copyright (C) 2001-2002 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * CPU support functions
 */
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/cpufreq.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_address.h>

#include <asm/mach-types.h>
#include <asm/hardware/icst.h>

static void __iomem *cm_base;
/* The cpufreq driver only use the OSC register */
#define INTEGRATOR_HDR_OSC_OFFSET       0x08
#define INTEGRATOR_HDR_LOCK_OFFSET      0x14

static struct cpufreq_driver integrator_driver;

static const struct icst_params lclk_params = {
	.ref		= 24000000,
	.vco_max	= ICST525_VCO_MAX_5V,
	.vco_min	= ICST525_VCO_MIN,
	.vd_min		= 8,
	.vd_max		= 132,
	.rd_min		= 24,
	.rd_max		= 24,
	.s2div		= icst525_s2div,
	.idx2s		= icst525_idx2s,
};

static const struct icst_params cclk_params = {
	.ref		= 24000000,
	.vco_max	= ICST525_VCO_MAX_5V,
	.vco_min	= ICST525_VCO_MIN,
	.vd_min		= 12,
	.vd_max		= 160,
	.rd_min		= 24,
	.rd_max		= 24,
	.s2div		= icst525_s2div,
	.idx2s		= icst525_idx2s,
};

/*
 * Validate the speed policy.
 */
static int integrator_verify_policy(struct cpufreq_policy *policy)
{
	struct icst_vco vco;

	cpufreq_verify_within_limits(policy, 
				     policy->cpuinfo.min_freq, 
				     policy->cpuinfo.max_freq);

	vco = icst_hz_to_vco(&cclk_params, policy->max * 1000);
	policy->max = icst_hz(&cclk_params, vco) / 1000;

	vco = icst_hz_to_vco(&cclk_params, policy->min * 1000);
	policy->min = icst_hz(&cclk_params, vco) / 1000;

	cpufreq_verify_within_limits(policy, 
				     policy->cpuinfo.min_freq, 
				     policy->cpuinfo.max_freq);

	return 0;
}


static int integrator_set_target(struct cpufreq_policy *policy,
				 unsigned int target_freq,
				 unsigned int relation)
{
	cpumask_t cpus_allowed;
	int cpu = policy->cpu;
	struct icst_vco vco;
	struct cpufreq_freqs freqs;
	u_int cm_osc;

	/*
	 * Save this threads cpus_allowed mask.
	 */
	cpus_allowed = current->cpus_allowed;

	/*
	 * Bind to the specified CPU.  When this call returns,
	 * we should be running on the right CPU.
	 */
	set_cpus_allowed(current, cpumask_of_cpu(cpu));
	BUG_ON(cpu != smp_processor_id());

	/* get current setting */
	cm_osc = __raw_readl(cm_base + INTEGRATOR_HDR_OSC_OFFSET);

	if (machine_is_integrator()) {
		vco.s = (cm_osc >> 8) & 7;
	} else if (machine_is_cintegrator()) {
		vco.s = 1;
	}
	vco.v = cm_osc & 255;
	vco.r = 22;
	freqs.old = icst_hz(&cclk_params, vco) / 1000;

	/* icst_hz_to_vco rounds down -- so we need the next
	 * larger freq in case of CPUFREQ_RELATION_L.
	 */
	if (relation == CPUFREQ_RELATION_L)
		target_freq += 999;
	if (target_freq > policy->max)
		target_freq = policy->max;
	vco = icst_hz_to_vco(&cclk_params, target_freq * 1000);
	freqs.new = icst_hz(&cclk_params, vco) / 1000;

	if (freqs.old == freqs.new) {
		set_cpus_allowed(current, cpus_allowed);
		return 0;
	}

	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);

	cm_osc = __raw_readl(cm_base + INTEGRATOR_HDR_OSC_OFFSET);

	if (machine_is_integrator()) {
		cm_osc &= 0xfffff800;
		cm_osc |= vco.s << 8;
	} else if (machine_is_cintegrator()) {
		cm_osc &= 0xffffff00;
	}
	cm_osc |= vco.v;

	__raw_writel(0xa05f, cm_base + INTEGRATOR_HDR_LOCK_OFFSET);
	__raw_writel(cm_osc, cm_base + INTEGRATOR_HDR_OSC_OFFSET);
	__raw_writel(0, cm_base + INTEGRATOR_HDR_LOCK_OFFSET);

	/*
	 * Restore the CPUs allowed mask.
	 */
	set_cpus_allowed(current, cpus_allowed);

	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);

	return 0;
}

static unsigned int integrator_get(unsigned int cpu)
{
	cpumask_t cpus_allowed;
	unsigned int current_freq;
	u_int cm_osc;
	struct icst_vco vco;

	cpus_allowed = current->cpus_allowed;

	set_cpus_allowed(current, cpumask_of_cpu(cpu));
	BUG_ON(cpu != smp_processor_id());

	/* detect memory etc. */
	cm_osc = __raw_readl(cm_base + INTEGRATOR_HDR_OSC_OFFSET);

	if (machine_is_integrator()) {
		vco.s = (cm_osc >> 8) & 7;
	} else {
		vco.s = 1;
	}
	vco.v = cm_osc & 255;
	vco.r = 22;

	current_freq = icst_hz(&cclk_params, vco) / 1000; /* current freq */

	set_cpus_allowed(current, cpus_allowed);

	return current_freq;
}

static int integrator_cpufreq_init(struct cpufreq_policy *policy)
{

	/* set default policy and cpuinfo */
	policy->cpuinfo.max_freq = 160000;
	policy->cpuinfo.min_freq = 12000;
	policy->cpuinfo.transition_latency = 1000000; /* 1 ms, assumed */
	policy->cur = policy->min = policy->max = integrator_get(policy->cpu);

	return 0;
}

static struct cpufreq_driver integrator_driver = {
	.verify		= integrator_verify_policy,
	.target		= integrator_set_target,
	.get		= integrator_get,
	.init		= integrator_cpufreq_init,
	.name		= "integrator",
};

static int __init integrator_cpufreq_probe(struct platform_device *pdev)
{
	struct resource *res;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        if (!res)
		return -ENODEV;

	cm_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
	if (!cm_base)
		return -ENODEV;

	return cpufreq_register_driver(&integrator_driver);
}

static void __exit integrator_cpufreq_remove(struct platform_device *pdev)
{
	cpufreq_unregister_driver(&integrator_driver);
}

static const struct of_device_id integrator_cpufreq_match[] = {
	{ .compatible = "arm,core-module-integrator"},
	{ },
};

static struct platform_driver integrator_cpufreq_driver = {
	.driver = {
		.name = "integrator-cpufreq",
		.owner = THIS_MODULE,
		.of_match_table = integrator_cpufreq_match,
	},
	.remove = __exit_p(integrator_cpufreq_remove),
};

module_platform_driver_probe(integrator_cpufreq_driver,
			     integrator_cpufreq_probe);

MODULE_AUTHOR ("Russell M. King");
MODULE_DESCRIPTION ("cpufreq driver for ARM Integrator CPUs");
MODULE_LICENSE ("GPL");
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Copyright (C) 2001-2002 Deep Blue Solutions Ltd.
1da177e4 LT	3	*
1da177e4 LT	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* CPU support functions
	9	*/
	10	#include <linux/module.h>
	11	#include <linux/types.h>
	12	#include <linux/kernel.h>
	13	#include <linux/cpufreq.h>
1da177e4 LT	14	#include <linux/sched.h>
	15	#include <linux/smp.h>
	16	#include <linux/init.h>
fced80c7	17	#include <linux/io.h>
bdac7eac LW	18	#include <linux/platform_device.h>
	19	#include <linux/of.h>
	20	#include <linux/of_address.h>
1da177e4	21
1da177e4	22	#include <asm/mach-types.h>
c5a0adb5	23	#include <asm/hardware/icst.h>
1da177e4	24
bdac7eac LW	25	static void __iomem *cm_base;
	26	/* The cpufreq driver only use the OSC register */
	27	#define INTEGRATOR_HDR_OSC_OFFSET 0x08
	28	#define INTEGRATOR_HDR_LOCK_OFFSET 0x14
1da177e4	29
bdac7eac	30	static struct cpufreq_driver integrator_driver;
1da177e4	31
39c0cb02	32	static const struct icst_params lclk_params = {
64fceb1d	33	.ref = 24000000,
4de2edbd	34	.vco_max = ICST525_VCO_MAX_5V,
e73a46a3	35	.vco_min = ICST525_VCO_MIN,
1da177e4 LT	36	.vd_min = 8,
	37	.vd_max = 132,
	38	.rd_min = 24,
	39	.rd_max = 24,
232eaf7f RK	40	.s2div = icst525_s2div,
232eaf7f RK	41	.idx2s = icst525_idx2s,
1da177e4 LT	42	};
1da177e4 LT	43
39c0cb02	44	static const struct icst_params cclk_params = {
64fceb1d	45	.ref = 24000000,
4de2edbd	46	.vco_max = ICST525_VCO_MAX_5V,
e73a46a3	47	.vco_min = ICST525_VCO_MIN,
1da177e4 LT	48	.vd_min = 12,
	49	.vd_max = 160,
	50	.rd_min = 24,
	51	.rd_max = 24,
232eaf7f RK	52	.s2div = icst525_s2div,
232eaf7f RK	53	.idx2s = icst525_idx2s,
1da177e4 LT	54	};
	55
	56	/*
	57	* Validate the speed policy.
	58	*/
	59	static int integrator_verify_policy(struct cpufreq_policy *policy)
	60	{
39c0cb02	61	struct icst_vco vco;
1da177e4 LT	62
	63	cpufreq_verify_within_limits(policy,
	64	policy->cpuinfo.min_freq,
	65	policy->cpuinfo.max_freq);
	66
c5a0adb5 RK	67	vco = icst_hz_to_vco(&cclk_params, policy->max * 1000);
c5a0adb5 RK	68	policy->max = icst_hz(&cclk_params, vco) / 1000;
1da177e4	69
c5a0adb5 RK	70	vco = icst_hz_to_vco(&cclk_params, policy->min * 1000);
c5a0adb5 RK	71	policy->min = icst_hz(&cclk_params, vco) / 1000;
1da177e4 LT	72
	73	cpufreq_verify_within_limits(policy,
	74	policy->cpuinfo.min_freq,
	75	policy->cpuinfo.max_freq);
	76
	77	return 0;
	78	}
	79
	80
	81	static int integrator_set_target(struct cpufreq_policy *policy,
	82	unsigned int target_freq,
	83	unsigned int relation)
	84	{
	85	cpumask_t cpus_allowed;
	86	int cpu = policy->cpu;
39c0cb02	87	struct icst_vco vco;
1da177e4 LT	88	struct cpufreq_freqs freqs;
	89	u_int cm_osc;
	90
	91	/*
	92	* Save this threads cpus_allowed mask.
	93	*/
	94	cpus_allowed = current->cpus_allowed;
	95
	96	/*
	97	* Bind to the specified CPU. When this call returns,
	98	* we should be running on the right CPU.
	99	*/
	100	set_cpus_allowed(current, cpumask_of_cpu(cpu));
	101	BUG_ON(cpu != smp_processor_id());
	102
	103	/* get current setting */
bdac7eac	104	cm_osc = __raw_readl(cm_base + INTEGRATOR_HDR_OSC_OFFSET);
1da177e4 LT	105
	106	if (machine_is_integrator()) {
	107	vco.s = (cm_osc >> 8) & 7;
	108	} else if (machine_is_cintegrator()) {
	109	vco.s = 1;
	110	}
	111	vco.v = cm_osc & 255;
	112	vco.r = 22;
c5a0adb5	113	freqs.old = icst_hz(&cclk_params, vco) / 1000;
1da177e4	114
c5a0adb5	115	/* icst_hz_to_vco rounds down -- so we need the next
1da177e4 LT	116	* larger freq in case of CPUFREQ_RELATION_L.
	117	*/
	118	if (relation == CPUFREQ_RELATION_L)
	119	target_freq += 999;
	120	if (target_freq > policy->max)
	121	target_freq = policy->max;
c5a0adb5 RK	122	vco = icst_hz_to_vco(&cclk_params, target_freq * 1000);
c5a0adb5 RK	123	freqs.new = icst_hz(&cclk_params, vco) / 1000;
1da177e4	124
1da177e4 LT	125	if (freqs.old == freqs.new) {
	126	set_cpus_allowed(current, cpus_allowed);
	127	return 0;
	128	}
	129
b43a7ffb	130	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
1da177e4	131
bdac7eac	132	cm_osc = __raw_readl(cm_base + INTEGRATOR_HDR_OSC_OFFSET);
1da177e4 LT	133
	134	if (machine_is_integrator()) {
	135	cm_osc &= 0xfffff800;
	136	cm_osc \|= vco.s << 8;
	137	} else if (machine_is_cintegrator()) {
	138	cm_osc &= 0xffffff00;
	139	}
	140	cm_osc \|= vco.v;
	141
bdac7eac LW	142	__raw_writel(0xa05f, cm_base + INTEGRATOR_HDR_LOCK_OFFSET);
	143	__raw_writel(cm_osc, cm_base + INTEGRATOR_HDR_OSC_OFFSET);
	144	__raw_writel(0, cm_base + INTEGRATOR_HDR_LOCK_OFFSET);
1da177e4 LT	145
	146	/*
	147	* Restore the CPUs allowed mask.
	148	*/
	149	set_cpus_allowed(current, cpus_allowed);
	150
b43a7ffb	151	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
1da177e4 LT	152
	153	return 0;
	154	}
	155
	156	static unsigned int integrator_get(unsigned int cpu)
	157	{
	158	cpumask_t cpus_allowed;
	159	unsigned int current_freq;
	160	u_int cm_osc;
39c0cb02	161	struct icst_vco vco;
1da177e4 LT	162
	163	cpus_allowed = current->cpus_allowed;
	164
	165	set_cpus_allowed(current, cpumask_of_cpu(cpu));
	166	BUG_ON(cpu != smp_processor_id());
	167
	168	/* detect memory etc. */
bdac7eac	169	cm_osc = __raw_readl(cm_base + INTEGRATOR_HDR_OSC_OFFSET);
1da177e4 LT	170
	171	if (machine_is_integrator()) {
	172	vco.s = (cm_osc >> 8) & 7;
1aa023b8	173	} else {
1da177e4 LT	174	vco.s = 1;
	175	}
	176	vco.v = cm_osc & 255;
	177	vco.r = 22;
	178
c5a0adb5	179	current_freq = icst_hz(&cclk_params, vco) / 1000; /* current freq */
1da177e4 LT	180
	181	set_cpus_allowed(current, cpus_allowed);
	182
	183	return current_freq;
	184	}
	185
	186	static int integrator_cpufreq_init(struct cpufreq_policy *policy)
	187	{
	188
	189	/* set default policy and cpuinfo */
1da177e4 LT	190	policy->cpuinfo.max_freq = 160000;
	191	policy->cpuinfo.min_freq = 12000;
	192	policy->cpuinfo.transition_latency = 1000000; /* 1 ms, assumed */
	193	policy->cur = policy->min = policy->max = integrator_get(policy->cpu);
	194
	195	return 0;
	196	}
	197
	198	static struct cpufreq_driver integrator_driver = {
	199	.verify = integrator_verify_policy,
	200	.target = integrator_set_target,
	201	.get = integrator_get,
	202	.init = integrator_cpufreq_init,
	203	.name = "integrator",
	204	};
	205
bdac7eac	206	static int __init integrator_cpufreq_probe(struct platform_device *pdev)
1da177e4	207	{
bdac7eac LW	208	struct resource *res;
	209
	210	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	211	if (!res)
	212	return -ENODEV;
	213
	214	cm_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
	215	if (!cm_base)
	216	return -ENODEV;
	217
1da177e4 LT	218	return cpufreq_register_driver(&integrator_driver);
	219	}
	220
bdac7eac	221	static void __exit integrator_cpufreq_remove(struct platform_device *pdev)
1da177e4 LT	222	{
	223	cpufreq_unregister_driver(&integrator_driver);
	224	}
	225
bdac7eac LW	226	static const struct of_device_id integrator_cpufreq_match[] = {
	227	{ .compatible = "arm,core-module-integrator"},
	228	{ },
	229	};
	230
	231	static struct platform_driver integrator_cpufreq_driver = {
	232	.driver = {
	233	.name = "integrator-cpufreq",
	234	.owner = THIS_MODULE,
	235	.of_match_table = integrator_cpufreq_match,
	236	},
	237	.remove = __exit_p(integrator_cpufreq_remove),
	238	};
	239
	240	module_platform_driver_probe(integrator_cpufreq_driver,
	241	integrator_cpufreq_probe);
	242
1da177e4 LT	243	MODULE_AUTHOR ("Russell M. King");
	244	MODULE_DESCRIPTION ("cpufreq driver for ARM Integrator CPUs");
	245	MODULE_LICENSE ("GPL");