Commit | Line | Data |
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93f0822d | 1 | /* |
d1b68485 | 2 | * intel_pstate.c: Native P state management for Intel processors |
93f0822d DB |
3 | * |
4 | * (C) Copyright 2012 Intel Corporation | |
5 | * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/ktime.h> | |
17 | #include <linux/hrtimer.h> | |
18 | #include <linux/tick.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/cpu.h> | |
23 | #include <linux/cpufreq.h> | |
24 | #include <linux/sysfs.h> | |
25 | #include <linux/types.h> | |
26 | #include <linux/fs.h> | |
27 | #include <linux/debugfs.h> | |
fbbcdc07 | 28 | #include <linux/acpi.h> |
93f0822d DB |
29 | #include <trace/events/power.h> |
30 | ||
31 | #include <asm/div64.h> | |
32 | #include <asm/msr.h> | |
33 | #include <asm/cpu_device_id.h> | |
34 | ||
35 | #define SAMPLE_COUNT 3 | |
36 | ||
19e77c28 DB |
37 | #define BYT_RATIOS 0x66a |
38 | ||
93f0822d DB |
39 | #define FRAC_BITS 8 |
40 | #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) | |
41 | #define fp_toint(X) ((X) >> FRAC_BITS) | |
42 | ||
43 | static inline int32_t mul_fp(int32_t x, int32_t y) | |
44 | { | |
45 | return ((int64_t)x * (int64_t)y) >> FRAC_BITS; | |
46 | } | |
47 | ||
48 | static inline int32_t div_fp(int32_t x, int32_t y) | |
49 | { | |
50 | return div_s64((int64_t)x << FRAC_BITS, (int64_t)y); | |
51 | } | |
52 | ||
53 | struct sample { | |
d253d2a5 | 54 | int32_t core_pct_busy; |
93f0822d DB |
55 | u64 aperf; |
56 | u64 mperf; | |
57 | int freq; | |
58 | }; | |
59 | ||
60 | struct pstate_data { | |
61 | int current_pstate; | |
62 | int min_pstate; | |
63 | int max_pstate; | |
64 | int turbo_pstate; | |
65 | }; | |
66 | ||
67 | struct _pid { | |
68 | int setpoint; | |
69 | int32_t integral; | |
70 | int32_t p_gain; | |
71 | int32_t i_gain; | |
72 | int32_t d_gain; | |
73 | int deadband; | |
d253d2a5 | 74 | int32_t last_err; |
93f0822d DB |
75 | }; |
76 | ||
77 | struct cpudata { | |
78 | int cpu; | |
79 | ||
80 | char name[64]; | |
81 | ||
82 | struct timer_list timer; | |
83 | ||
93f0822d DB |
84 | struct pstate_data pstate; |
85 | struct _pid pid; | |
93f0822d DB |
86 | |
87 | int min_pstate_count; | |
93f0822d | 88 | |
93f0822d DB |
89 | u64 prev_aperf; |
90 | u64 prev_mperf; | |
91 | int sample_ptr; | |
92 | struct sample samples[SAMPLE_COUNT]; | |
93 | }; | |
94 | ||
95 | static struct cpudata **all_cpu_data; | |
96 | struct pstate_adjust_policy { | |
97 | int sample_rate_ms; | |
98 | int deadband; | |
99 | int setpoint; | |
100 | int p_gain_pct; | |
101 | int d_gain_pct; | |
102 | int i_gain_pct; | |
103 | }; | |
104 | ||
016c8150 DB |
105 | struct pstate_funcs { |
106 | int (*get_max)(void); | |
107 | int (*get_min)(void); | |
108 | int (*get_turbo)(void); | |
109 | void (*set)(int pstate); | |
93f0822d DB |
110 | }; |
111 | ||
016c8150 DB |
112 | struct cpu_defaults { |
113 | struct pstate_adjust_policy pid_policy; | |
114 | struct pstate_funcs funcs; | |
93f0822d DB |
115 | }; |
116 | ||
016c8150 DB |
117 | static struct pstate_adjust_policy pid_params; |
118 | static struct pstate_funcs pstate_funcs; | |
119 | ||
93f0822d DB |
120 | struct perf_limits { |
121 | int no_turbo; | |
122 | int max_perf_pct; | |
123 | int min_perf_pct; | |
124 | int32_t max_perf; | |
125 | int32_t min_perf; | |
d8f469e9 DB |
126 | int max_policy_pct; |
127 | int max_sysfs_pct; | |
93f0822d DB |
128 | }; |
129 | ||
130 | static struct perf_limits limits = { | |
131 | .no_turbo = 0, | |
132 | .max_perf_pct = 100, | |
133 | .max_perf = int_tofp(1), | |
134 | .min_perf_pct = 0, | |
135 | .min_perf = 0, | |
d8f469e9 DB |
136 | .max_policy_pct = 100, |
137 | .max_sysfs_pct = 100, | |
93f0822d DB |
138 | }; |
139 | ||
140 | static inline void pid_reset(struct _pid *pid, int setpoint, int busy, | |
141 | int deadband, int integral) { | |
142 | pid->setpoint = setpoint; | |
143 | pid->deadband = deadband; | |
144 | pid->integral = int_tofp(integral); | |
145 | pid->last_err = setpoint - busy; | |
146 | } | |
147 | ||
148 | static inline void pid_p_gain_set(struct _pid *pid, int percent) | |
149 | { | |
150 | pid->p_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
151 | } | |
152 | ||
153 | static inline void pid_i_gain_set(struct _pid *pid, int percent) | |
154 | { | |
155 | pid->i_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
156 | } | |
157 | ||
158 | static inline void pid_d_gain_set(struct _pid *pid, int percent) | |
159 | { | |
160 | ||
161 | pid->d_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
162 | } | |
163 | ||
d253d2a5 | 164 | static signed int pid_calc(struct _pid *pid, int32_t busy) |
93f0822d | 165 | { |
d253d2a5 | 166 | signed int result; |
93f0822d DB |
167 | int32_t pterm, dterm, fp_error; |
168 | int32_t integral_limit; | |
169 | ||
d253d2a5 | 170 | fp_error = int_tofp(pid->setpoint) - busy; |
93f0822d | 171 | |
d253d2a5 | 172 | if (abs(fp_error) <= int_tofp(pid->deadband)) |
93f0822d DB |
173 | return 0; |
174 | ||
175 | pterm = mul_fp(pid->p_gain, fp_error); | |
176 | ||
177 | pid->integral += fp_error; | |
178 | ||
179 | /* limit the integral term */ | |
180 | integral_limit = int_tofp(30); | |
181 | if (pid->integral > integral_limit) | |
182 | pid->integral = integral_limit; | |
183 | if (pid->integral < -integral_limit) | |
184 | pid->integral = -integral_limit; | |
185 | ||
d253d2a5 BS |
186 | dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); |
187 | pid->last_err = fp_error; | |
93f0822d DB |
188 | |
189 | result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; | |
190 | ||
191 | return (signed int)fp_toint(result); | |
192 | } | |
193 | ||
194 | static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) | |
195 | { | |
016c8150 DB |
196 | pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); |
197 | pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); | |
198 | pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); | |
93f0822d DB |
199 | |
200 | pid_reset(&cpu->pid, | |
016c8150 | 201 | pid_params.setpoint, |
93f0822d | 202 | 100, |
016c8150 | 203 | pid_params.deadband, |
93f0822d DB |
204 | 0); |
205 | } | |
206 | ||
93f0822d DB |
207 | static inline void intel_pstate_reset_all_pid(void) |
208 | { | |
209 | unsigned int cpu; | |
210 | for_each_online_cpu(cpu) { | |
211 | if (all_cpu_data[cpu]) | |
212 | intel_pstate_busy_pid_reset(all_cpu_data[cpu]); | |
213 | } | |
214 | } | |
215 | ||
216 | /************************** debugfs begin ************************/ | |
217 | static int pid_param_set(void *data, u64 val) | |
218 | { | |
219 | *(u32 *)data = val; | |
220 | intel_pstate_reset_all_pid(); | |
221 | return 0; | |
222 | } | |
223 | static int pid_param_get(void *data, u64 *val) | |
224 | { | |
225 | *val = *(u32 *)data; | |
226 | return 0; | |
227 | } | |
228 | DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, | |
229 | pid_param_set, "%llu\n"); | |
230 | ||
231 | struct pid_param { | |
232 | char *name; | |
233 | void *value; | |
234 | }; | |
235 | ||
236 | static struct pid_param pid_files[] = { | |
016c8150 DB |
237 | {"sample_rate_ms", &pid_params.sample_rate_ms}, |
238 | {"d_gain_pct", &pid_params.d_gain_pct}, | |
239 | {"i_gain_pct", &pid_params.i_gain_pct}, | |
240 | {"deadband", &pid_params.deadband}, | |
241 | {"setpoint", &pid_params.setpoint}, | |
242 | {"p_gain_pct", &pid_params.p_gain_pct}, | |
93f0822d DB |
243 | {NULL, NULL} |
244 | }; | |
245 | ||
246 | static struct dentry *debugfs_parent; | |
247 | static void intel_pstate_debug_expose_params(void) | |
248 | { | |
249 | int i = 0; | |
250 | ||
251 | debugfs_parent = debugfs_create_dir("pstate_snb", NULL); | |
252 | if (IS_ERR_OR_NULL(debugfs_parent)) | |
253 | return; | |
254 | while (pid_files[i].name) { | |
255 | debugfs_create_file(pid_files[i].name, 0660, | |
256 | debugfs_parent, pid_files[i].value, | |
257 | &fops_pid_param); | |
258 | i++; | |
259 | } | |
260 | } | |
261 | ||
262 | /************************** debugfs end ************************/ | |
263 | ||
264 | /************************** sysfs begin ************************/ | |
265 | #define show_one(file_name, object) \ | |
266 | static ssize_t show_##file_name \ | |
267 | (struct kobject *kobj, struct attribute *attr, char *buf) \ | |
268 | { \ | |
269 | return sprintf(buf, "%u\n", limits.object); \ | |
270 | } | |
271 | ||
272 | static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, | |
273 | const char *buf, size_t count) | |
274 | { | |
275 | unsigned int input; | |
276 | int ret; | |
277 | ret = sscanf(buf, "%u", &input); | |
278 | if (ret != 1) | |
279 | return -EINVAL; | |
280 | limits.no_turbo = clamp_t(int, input, 0 , 1); | |
281 | ||
282 | return count; | |
283 | } | |
284 | ||
285 | static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, | |
286 | const char *buf, size_t count) | |
287 | { | |
288 | unsigned int input; | |
289 | int ret; | |
290 | ret = sscanf(buf, "%u", &input); | |
291 | if (ret != 1) | |
292 | return -EINVAL; | |
293 | ||
d8f469e9 DB |
294 | limits.max_sysfs_pct = clamp_t(int, input, 0 , 100); |
295 | limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct); | |
93f0822d DB |
296 | limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100)); |
297 | return count; | |
298 | } | |
299 | ||
300 | static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, | |
301 | const char *buf, size_t count) | |
302 | { | |
303 | unsigned int input; | |
304 | int ret; | |
305 | ret = sscanf(buf, "%u", &input); | |
306 | if (ret != 1) | |
307 | return -EINVAL; | |
308 | limits.min_perf_pct = clamp_t(int, input, 0 , 100); | |
309 | limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100)); | |
310 | ||
311 | return count; | |
312 | } | |
313 | ||
314 | show_one(no_turbo, no_turbo); | |
315 | show_one(max_perf_pct, max_perf_pct); | |
316 | show_one(min_perf_pct, min_perf_pct); | |
317 | ||
318 | define_one_global_rw(no_turbo); | |
319 | define_one_global_rw(max_perf_pct); | |
320 | define_one_global_rw(min_perf_pct); | |
321 | ||
322 | static struct attribute *intel_pstate_attributes[] = { | |
323 | &no_turbo.attr, | |
324 | &max_perf_pct.attr, | |
325 | &min_perf_pct.attr, | |
326 | NULL | |
327 | }; | |
328 | ||
329 | static struct attribute_group intel_pstate_attr_group = { | |
330 | .attrs = intel_pstate_attributes, | |
331 | }; | |
332 | static struct kobject *intel_pstate_kobject; | |
333 | ||
334 | static void intel_pstate_sysfs_expose_params(void) | |
335 | { | |
336 | int rc; | |
337 | ||
338 | intel_pstate_kobject = kobject_create_and_add("intel_pstate", | |
339 | &cpu_subsys.dev_root->kobj); | |
340 | BUG_ON(!intel_pstate_kobject); | |
341 | rc = sysfs_create_group(intel_pstate_kobject, | |
342 | &intel_pstate_attr_group); | |
343 | BUG_ON(rc); | |
344 | } | |
345 | ||
346 | /************************** sysfs end ************************/ | |
19e77c28 DB |
347 | static int byt_get_min_pstate(void) |
348 | { | |
349 | u64 value; | |
350 | rdmsrl(BYT_RATIOS, value); | |
351 | return value & 0xFF; | |
352 | } | |
353 | ||
354 | static int byt_get_max_pstate(void) | |
355 | { | |
356 | u64 value; | |
357 | rdmsrl(BYT_RATIOS, value); | |
358 | return (value >> 16) & 0xFF; | |
359 | } | |
93f0822d | 360 | |
016c8150 | 361 | static int core_get_min_pstate(void) |
93f0822d DB |
362 | { |
363 | u64 value; | |
05e99c8c | 364 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
365 | return (value >> 40) & 0xFF; |
366 | } | |
367 | ||
016c8150 | 368 | static int core_get_max_pstate(void) |
93f0822d DB |
369 | { |
370 | u64 value; | |
05e99c8c | 371 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
372 | return (value >> 8) & 0xFF; |
373 | } | |
374 | ||
016c8150 | 375 | static int core_get_turbo_pstate(void) |
93f0822d DB |
376 | { |
377 | u64 value; | |
378 | int nont, ret; | |
05e99c8c | 379 | rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); |
016c8150 | 380 | nont = core_get_max_pstate(); |
93f0822d DB |
381 | ret = ((value) & 255); |
382 | if (ret <= nont) | |
383 | ret = nont; | |
384 | return ret; | |
385 | } | |
386 | ||
016c8150 DB |
387 | static void core_set_pstate(int pstate) |
388 | { | |
389 | u64 val; | |
390 | ||
391 | val = pstate << 8; | |
392 | if (limits.no_turbo) | |
393 | val |= (u64)1 << 32; | |
394 | ||
395 | wrmsrl(MSR_IA32_PERF_CTL, val); | |
396 | } | |
397 | ||
398 | static struct cpu_defaults core_params = { | |
399 | .pid_policy = { | |
400 | .sample_rate_ms = 10, | |
401 | .deadband = 0, | |
402 | .setpoint = 97, | |
403 | .p_gain_pct = 20, | |
404 | .d_gain_pct = 0, | |
405 | .i_gain_pct = 0, | |
406 | }, | |
407 | .funcs = { | |
408 | .get_max = core_get_max_pstate, | |
409 | .get_min = core_get_min_pstate, | |
410 | .get_turbo = core_get_turbo_pstate, | |
411 | .set = core_set_pstate, | |
412 | }, | |
413 | }; | |
414 | ||
19e77c28 DB |
415 | static struct cpu_defaults byt_params = { |
416 | .pid_policy = { | |
417 | .sample_rate_ms = 10, | |
418 | .deadband = 0, | |
419 | .setpoint = 97, | |
420 | .p_gain_pct = 14, | |
421 | .d_gain_pct = 0, | |
422 | .i_gain_pct = 4, | |
423 | }, | |
424 | .funcs = { | |
425 | .get_max = byt_get_max_pstate, | |
426 | .get_min = byt_get_min_pstate, | |
427 | .get_turbo = byt_get_max_pstate, | |
428 | .set = core_set_pstate, | |
429 | }, | |
430 | }; | |
431 | ||
432 | ||
93f0822d DB |
433 | static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) |
434 | { | |
435 | int max_perf = cpu->pstate.turbo_pstate; | |
7244cb62 | 436 | int max_perf_adj; |
93f0822d DB |
437 | int min_perf; |
438 | if (limits.no_turbo) | |
439 | max_perf = cpu->pstate.max_pstate; | |
440 | ||
7244cb62 DB |
441 | max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf)); |
442 | *max = clamp_t(int, max_perf_adj, | |
93f0822d DB |
443 | cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); |
444 | ||
445 | min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf)); | |
446 | *min = clamp_t(int, min_perf, | |
447 | cpu->pstate.min_pstate, max_perf); | |
448 | } | |
449 | ||
450 | static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) | |
451 | { | |
452 | int max_perf, min_perf; | |
453 | ||
454 | intel_pstate_get_min_max(cpu, &min_perf, &max_perf); | |
455 | ||
456 | pstate = clamp_t(int, pstate, min_perf, max_perf); | |
457 | ||
458 | if (pstate == cpu->pstate.current_pstate) | |
459 | return; | |
460 | ||
93f0822d | 461 | trace_cpu_frequency(pstate * 100000, cpu->cpu); |
35363e94 | 462 | |
93f0822d | 463 | cpu->pstate.current_pstate = pstate; |
93f0822d | 464 | |
016c8150 | 465 | pstate_funcs.set(pstate); |
93f0822d DB |
466 | } |
467 | ||
468 | static inline void intel_pstate_pstate_increase(struct cpudata *cpu, int steps) | |
469 | { | |
470 | int target; | |
471 | target = cpu->pstate.current_pstate + steps; | |
472 | ||
473 | intel_pstate_set_pstate(cpu, target); | |
474 | } | |
475 | ||
476 | static inline void intel_pstate_pstate_decrease(struct cpudata *cpu, int steps) | |
477 | { | |
478 | int target; | |
479 | target = cpu->pstate.current_pstate - steps; | |
480 | intel_pstate_set_pstate(cpu, target); | |
481 | } | |
482 | ||
483 | static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) | |
484 | { | |
485 | sprintf(cpu->name, "Intel 2nd generation core"); | |
486 | ||
016c8150 DB |
487 | cpu->pstate.min_pstate = pstate_funcs.get_min(); |
488 | cpu->pstate.max_pstate = pstate_funcs.get_max(); | |
489 | cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); | |
93f0822d DB |
490 | |
491 | /* | |
492 | * goto max pstate so we don't slow up boot if we are built-in if we are | |
493 | * a module we will take care of it during normal operation | |
494 | */ | |
495 | intel_pstate_set_pstate(cpu, cpu->pstate.max_pstate); | |
496 | } | |
497 | ||
498 | static inline void intel_pstate_calc_busy(struct cpudata *cpu, | |
499 | struct sample *sample) | |
500 | { | |
501 | u64 core_pct; | |
d253d2a5 BS |
502 | core_pct = div64_u64(int_tofp(sample->aperf * 100), |
503 | sample->mperf); | |
504 | sample->freq = fp_toint(cpu->pstate.max_pstate * core_pct * 1000); | |
93f0822d | 505 | |
1abc4b20 | 506 | sample->core_pct_busy = core_pct; |
93f0822d DB |
507 | } |
508 | ||
509 | static inline void intel_pstate_sample(struct cpudata *cpu) | |
510 | { | |
93f0822d DB |
511 | u64 aperf, mperf; |
512 | ||
93f0822d DB |
513 | rdmsrl(MSR_IA32_APERF, aperf); |
514 | rdmsrl(MSR_IA32_MPERF, mperf); | |
1abc4b20 DB |
515 | cpu->sample_ptr = (cpu->sample_ptr + 1) % SAMPLE_COUNT; |
516 | cpu->samples[cpu->sample_ptr].aperf = aperf; | |
517 | cpu->samples[cpu->sample_ptr].mperf = mperf; | |
518 | cpu->samples[cpu->sample_ptr].aperf -= cpu->prev_aperf; | |
519 | cpu->samples[cpu->sample_ptr].mperf -= cpu->prev_mperf; | |
520 | ||
521 | intel_pstate_calc_busy(cpu, &cpu->samples[cpu->sample_ptr]); | |
93f0822d | 522 | |
93f0822d DB |
523 | cpu->prev_aperf = aperf; |
524 | cpu->prev_mperf = mperf; | |
525 | } | |
526 | ||
527 | static inline void intel_pstate_set_sample_time(struct cpudata *cpu) | |
528 | { | |
529 | int sample_time, delay; | |
530 | ||
016c8150 | 531 | sample_time = pid_params.sample_rate_ms; |
93f0822d | 532 | delay = msecs_to_jiffies(sample_time); |
93f0822d DB |
533 | mod_timer_pinned(&cpu->timer, jiffies + delay); |
534 | } | |
535 | ||
d253d2a5 | 536 | static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu) |
93f0822d | 537 | { |
2134ed4d | 538 | int32_t core_busy, max_pstate, current_pstate; |
93f0822d | 539 | |
d253d2a5 | 540 | core_busy = cpu->samples[cpu->sample_ptr].core_pct_busy; |
2134ed4d | 541 | max_pstate = int_tofp(cpu->pstate.max_pstate); |
93f0822d | 542 | current_pstate = int_tofp(cpu->pstate.current_pstate); |
d253d2a5 | 543 | return mul_fp(core_busy, div_fp(max_pstate, current_pstate)); |
93f0822d DB |
544 | } |
545 | ||
546 | static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) | |
547 | { | |
d253d2a5 | 548 | int32_t busy_scaled; |
93f0822d DB |
549 | struct _pid *pid; |
550 | signed int ctl = 0; | |
551 | int steps; | |
552 | ||
553 | pid = &cpu->pid; | |
554 | busy_scaled = intel_pstate_get_scaled_busy(cpu); | |
555 | ||
556 | ctl = pid_calc(pid, busy_scaled); | |
557 | ||
558 | steps = abs(ctl); | |
559 | if (ctl < 0) | |
560 | intel_pstate_pstate_increase(cpu, steps); | |
561 | else | |
562 | intel_pstate_pstate_decrease(cpu, steps); | |
563 | } | |
564 | ||
93f0822d DB |
565 | static void intel_pstate_timer_func(unsigned long __data) |
566 | { | |
567 | struct cpudata *cpu = (struct cpudata *) __data; | |
568 | ||
569 | intel_pstate_sample(cpu); | |
ca182aee | 570 | intel_pstate_adjust_busy_pstate(cpu); |
93f0822d | 571 | |
93f0822d DB |
572 | if (cpu->pstate.current_pstate == cpu->pstate.min_pstate) { |
573 | cpu->min_pstate_count++; | |
574 | if (!(cpu->min_pstate_count % 5)) { | |
575 | intel_pstate_set_pstate(cpu, cpu->pstate.max_pstate); | |
93f0822d DB |
576 | } |
577 | } else | |
578 | cpu->min_pstate_count = 0; | |
ca182aee | 579 | |
93f0822d DB |
580 | intel_pstate_set_sample_time(cpu); |
581 | } | |
582 | ||
583 | #define ICPU(model, policy) \ | |
584 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&policy } | |
585 | ||
586 | static const struct x86_cpu_id intel_pstate_cpu_ids[] = { | |
016c8150 DB |
587 | ICPU(0x2a, core_params), |
588 | ICPU(0x2d, core_params), | |
19e77c28 | 589 | ICPU(0x37, byt_params), |
016c8150 DB |
590 | ICPU(0x3a, core_params), |
591 | ICPU(0x3c, core_params), | |
592 | ICPU(0x3e, core_params), | |
593 | ICPU(0x3f, core_params), | |
594 | ICPU(0x45, core_params), | |
595 | ICPU(0x46, core_params), | |
93f0822d DB |
596 | {} |
597 | }; | |
598 | MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); | |
599 | ||
600 | static int intel_pstate_init_cpu(unsigned int cpunum) | |
601 | { | |
602 | ||
603 | const struct x86_cpu_id *id; | |
604 | struct cpudata *cpu; | |
605 | ||
606 | id = x86_match_cpu(intel_pstate_cpu_ids); | |
607 | if (!id) | |
608 | return -ENODEV; | |
609 | ||
610 | all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), GFP_KERNEL); | |
611 | if (!all_cpu_data[cpunum]) | |
612 | return -ENOMEM; | |
613 | ||
614 | cpu = all_cpu_data[cpunum]; | |
615 | ||
616 | intel_pstate_get_cpu_pstates(cpu); | |
617 | ||
618 | cpu->cpu = cpunum; | |
016c8150 | 619 | |
93f0822d DB |
620 | init_timer_deferrable(&cpu->timer); |
621 | cpu->timer.function = intel_pstate_timer_func; | |
622 | cpu->timer.data = | |
623 | (unsigned long)cpu; | |
624 | cpu->timer.expires = jiffies + HZ/100; | |
625 | intel_pstate_busy_pid_reset(cpu); | |
93f0822d DB |
626 | intel_pstate_sample(cpu); |
627 | intel_pstate_set_pstate(cpu, cpu->pstate.max_pstate); | |
628 | ||
629 | add_timer_on(&cpu->timer, cpunum); | |
630 | ||
631 | pr_info("Intel pstate controlling: cpu %d\n", cpunum); | |
632 | ||
633 | return 0; | |
634 | } | |
635 | ||
636 | static unsigned int intel_pstate_get(unsigned int cpu_num) | |
637 | { | |
638 | struct sample *sample; | |
639 | struct cpudata *cpu; | |
640 | ||
641 | cpu = all_cpu_data[cpu_num]; | |
642 | if (!cpu) | |
643 | return 0; | |
644 | sample = &cpu->samples[cpu->sample_ptr]; | |
645 | return sample->freq; | |
646 | } | |
647 | ||
648 | static int intel_pstate_set_policy(struct cpufreq_policy *policy) | |
649 | { | |
650 | struct cpudata *cpu; | |
93f0822d DB |
651 | |
652 | cpu = all_cpu_data[policy->cpu]; | |
653 | ||
d3929b83 DB |
654 | if (!policy->cpuinfo.max_freq) |
655 | return -ENODEV; | |
656 | ||
93f0822d DB |
657 | if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { |
658 | limits.min_perf_pct = 100; | |
659 | limits.min_perf = int_tofp(1); | |
660 | limits.max_perf_pct = 100; | |
661 | limits.max_perf = int_tofp(1); | |
662 | limits.no_turbo = 0; | |
d1b68485 | 663 | return 0; |
93f0822d | 664 | } |
d1b68485 SP |
665 | limits.min_perf_pct = (policy->min * 100) / policy->cpuinfo.max_freq; |
666 | limits.min_perf_pct = clamp_t(int, limits.min_perf_pct, 0 , 100); | |
667 | limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100)); | |
668 | ||
d8f469e9 DB |
669 | limits.max_policy_pct = policy->max * 100 / policy->cpuinfo.max_freq; |
670 | limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100); | |
671 | limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct); | |
d1b68485 | 672 | limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100)); |
93f0822d DB |
673 | |
674 | return 0; | |
675 | } | |
676 | ||
677 | static int intel_pstate_verify_policy(struct cpufreq_policy *policy) | |
678 | { | |
be49e346 | 679 | cpufreq_verify_within_cpu_limits(policy); |
93f0822d DB |
680 | |
681 | if ((policy->policy != CPUFREQ_POLICY_POWERSAVE) && | |
682 | (policy->policy != CPUFREQ_POLICY_PERFORMANCE)) | |
683 | return -EINVAL; | |
684 | ||
685 | return 0; | |
686 | } | |
687 | ||
2760984f | 688 | static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) |
93f0822d DB |
689 | { |
690 | int cpu = policy->cpu; | |
691 | ||
692 | del_timer(&all_cpu_data[cpu]->timer); | |
693 | kfree(all_cpu_data[cpu]); | |
694 | all_cpu_data[cpu] = NULL; | |
695 | return 0; | |
696 | } | |
697 | ||
2760984f | 698 | static int intel_pstate_cpu_init(struct cpufreq_policy *policy) |
93f0822d | 699 | { |
93f0822d | 700 | struct cpudata *cpu; |
52e0a509 | 701 | int rc; |
93f0822d DB |
702 | |
703 | rc = intel_pstate_init_cpu(policy->cpu); | |
704 | if (rc) | |
705 | return rc; | |
706 | ||
707 | cpu = all_cpu_data[policy->cpu]; | |
708 | ||
709 | if (!limits.no_turbo && | |
710 | limits.min_perf_pct == 100 && limits.max_perf_pct == 100) | |
711 | policy->policy = CPUFREQ_POLICY_PERFORMANCE; | |
712 | else | |
713 | policy->policy = CPUFREQ_POLICY_POWERSAVE; | |
714 | ||
52e0a509 DB |
715 | policy->min = cpu->pstate.min_pstate * 100000; |
716 | policy->max = cpu->pstate.turbo_pstate * 100000; | |
93f0822d DB |
717 | |
718 | /* cpuinfo and default policy values */ | |
719 | policy->cpuinfo.min_freq = cpu->pstate.min_pstate * 100000; | |
720 | policy->cpuinfo.max_freq = cpu->pstate.turbo_pstate * 100000; | |
721 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; | |
722 | cpumask_set_cpu(policy->cpu, policy->cpus); | |
723 | ||
724 | return 0; | |
725 | } | |
726 | ||
727 | static struct cpufreq_driver intel_pstate_driver = { | |
728 | .flags = CPUFREQ_CONST_LOOPS, | |
729 | .verify = intel_pstate_verify_policy, | |
730 | .setpolicy = intel_pstate_set_policy, | |
731 | .get = intel_pstate_get, | |
732 | .init = intel_pstate_cpu_init, | |
733 | .exit = intel_pstate_cpu_exit, | |
734 | .name = "intel_pstate", | |
93f0822d DB |
735 | }; |
736 | ||
6be26498 DB |
737 | static int __initdata no_load; |
738 | ||
b563b4e3 DB |
739 | static int intel_pstate_msrs_not_valid(void) |
740 | { | |
741 | /* Check that all the msr's we are using are valid. */ | |
742 | u64 aperf, mperf, tmp; | |
743 | ||
744 | rdmsrl(MSR_IA32_APERF, aperf); | |
745 | rdmsrl(MSR_IA32_MPERF, mperf); | |
746 | ||
016c8150 DB |
747 | if (!pstate_funcs.get_max() || |
748 | !pstate_funcs.get_min() || | |
749 | !pstate_funcs.get_turbo()) | |
b563b4e3 DB |
750 | return -ENODEV; |
751 | ||
752 | rdmsrl(MSR_IA32_APERF, tmp); | |
753 | if (!(tmp - aperf)) | |
754 | return -ENODEV; | |
755 | ||
756 | rdmsrl(MSR_IA32_MPERF, tmp); | |
757 | if (!(tmp - mperf)) | |
758 | return -ENODEV; | |
759 | ||
760 | return 0; | |
761 | } | |
016c8150 | 762 | |
e0a261a2 | 763 | static void copy_pid_params(struct pstate_adjust_policy *policy) |
016c8150 DB |
764 | { |
765 | pid_params.sample_rate_ms = policy->sample_rate_ms; | |
766 | pid_params.p_gain_pct = policy->p_gain_pct; | |
767 | pid_params.i_gain_pct = policy->i_gain_pct; | |
768 | pid_params.d_gain_pct = policy->d_gain_pct; | |
769 | pid_params.deadband = policy->deadband; | |
770 | pid_params.setpoint = policy->setpoint; | |
771 | } | |
772 | ||
e0a261a2 | 773 | static void copy_cpu_funcs(struct pstate_funcs *funcs) |
016c8150 DB |
774 | { |
775 | pstate_funcs.get_max = funcs->get_max; | |
776 | pstate_funcs.get_min = funcs->get_min; | |
777 | pstate_funcs.get_turbo = funcs->get_turbo; | |
778 | pstate_funcs.set = funcs->set; | |
779 | } | |
780 | ||
fbbcdc07 AH |
781 | #if IS_ENABLED(CONFIG_ACPI) |
782 | #include <acpi/processor.h> | |
783 | ||
784 | static bool intel_pstate_no_acpi_pss(void) | |
785 | { | |
786 | int i; | |
787 | ||
788 | for_each_possible_cpu(i) { | |
789 | acpi_status status; | |
790 | union acpi_object *pss; | |
791 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
792 | struct acpi_processor *pr = per_cpu(processors, i); | |
793 | ||
794 | if (!pr) | |
795 | continue; | |
796 | ||
797 | status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); | |
798 | if (ACPI_FAILURE(status)) | |
799 | continue; | |
800 | ||
801 | pss = buffer.pointer; | |
802 | if (pss && pss->type == ACPI_TYPE_PACKAGE) { | |
803 | kfree(pss); | |
804 | return false; | |
805 | } | |
806 | ||
807 | kfree(pss); | |
808 | } | |
809 | ||
810 | return true; | |
811 | } | |
812 | ||
813 | struct hw_vendor_info { | |
814 | u16 valid; | |
815 | char oem_id[ACPI_OEM_ID_SIZE]; | |
816 | char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; | |
817 | }; | |
818 | ||
819 | /* Hardware vendor-specific info that has its own power management modes */ | |
820 | static struct hw_vendor_info vendor_info[] = { | |
821 | {1, "HP ", "ProLiant"}, | |
822 | {0, "", ""}, | |
823 | }; | |
824 | ||
825 | static bool intel_pstate_platform_pwr_mgmt_exists(void) | |
826 | { | |
827 | struct acpi_table_header hdr; | |
828 | struct hw_vendor_info *v_info; | |
829 | ||
830 | if (acpi_disabled | |
831 | || ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) | |
832 | return false; | |
833 | ||
834 | for (v_info = vendor_info; v_info->valid; v_info++) { | |
835 | if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) | |
836 | && !strncmp(hdr.oem_table_id, v_info->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) | |
837 | && intel_pstate_no_acpi_pss()) | |
838 | return true; | |
839 | } | |
840 | ||
841 | return false; | |
842 | } | |
843 | #else /* CONFIG_ACPI not enabled */ | |
844 | static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } | |
845 | #endif /* CONFIG_ACPI */ | |
846 | ||
93f0822d DB |
847 | static int __init intel_pstate_init(void) |
848 | { | |
907cc908 | 849 | int cpu, rc = 0; |
93f0822d | 850 | const struct x86_cpu_id *id; |
016c8150 | 851 | struct cpu_defaults *cpu_info; |
93f0822d | 852 | |
6be26498 DB |
853 | if (no_load) |
854 | return -ENODEV; | |
855 | ||
93f0822d DB |
856 | id = x86_match_cpu(intel_pstate_cpu_ids); |
857 | if (!id) | |
858 | return -ENODEV; | |
859 | ||
fbbcdc07 AH |
860 | /* |
861 | * The Intel pstate driver will be ignored if the platform | |
862 | * firmware has its own power management modes. | |
863 | */ | |
864 | if (intel_pstate_platform_pwr_mgmt_exists()) | |
865 | return -ENODEV; | |
866 | ||
016c8150 DB |
867 | cpu_info = (struct cpu_defaults *)id->driver_data; |
868 | ||
869 | copy_pid_params(&cpu_info->pid_policy); | |
870 | copy_cpu_funcs(&cpu_info->funcs); | |
871 | ||
b563b4e3 DB |
872 | if (intel_pstate_msrs_not_valid()) |
873 | return -ENODEV; | |
874 | ||
93f0822d DB |
875 | pr_info("Intel P-state driver initializing.\n"); |
876 | ||
b57ffac5 | 877 | all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); |
93f0822d DB |
878 | if (!all_cpu_data) |
879 | return -ENOMEM; | |
93f0822d DB |
880 | |
881 | rc = cpufreq_register_driver(&intel_pstate_driver); | |
882 | if (rc) | |
883 | goto out; | |
884 | ||
885 | intel_pstate_debug_expose_params(); | |
886 | intel_pstate_sysfs_expose_params(); | |
887 | return rc; | |
888 | out: | |
907cc908 DB |
889 | get_online_cpus(); |
890 | for_each_online_cpu(cpu) { | |
891 | if (all_cpu_data[cpu]) { | |
892 | del_timer_sync(&all_cpu_data[cpu]->timer); | |
893 | kfree(all_cpu_data[cpu]); | |
894 | } | |
895 | } | |
896 | ||
897 | put_online_cpus(); | |
898 | vfree(all_cpu_data); | |
93f0822d DB |
899 | return -ENODEV; |
900 | } | |
901 | device_initcall(intel_pstate_init); | |
902 | ||
6be26498 DB |
903 | static int __init intel_pstate_setup(char *str) |
904 | { | |
905 | if (!str) | |
906 | return -EINVAL; | |
907 | ||
908 | if (!strcmp(str, "disable")) | |
909 | no_load = 1; | |
910 | return 0; | |
911 | } | |
912 | early_param("intel_pstate", intel_pstate_setup); | |
913 | ||
93f0822d DB |
914 | MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); |
915 | MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); | |
916 | MODULE_LICENSE("GPL"); |