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93f0822d | 1 | /* |
d1b68485 | 2 | * intel_pstate.c: Native P state management for Intel processors |
93f0822d DB |
3 | * |
4 | * (C) Copyright 2012 Intel Corporation | |
5 | * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/ktime.h> | |
17 | #include <linux/hrtimer.h> | |
18 | #include <linux/tick.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/cpu.h> | |
23 | #include <linux/cpufreq.h> | |
24 | #include <linux/sysfs.h> | |
25 | #include <linux/types.h> | |
26 | #include <linux/fs.h> | |
27 | #include <linux/debugfs.h> | |
28 | #include <trace/events/power.h> | |
29 | ||
30 | #include <asm/div64.h> | |
31 | #include <asm/msr.h> | |
32 | #include <asm/cpu_device_id.h> | |
33 | ||
34 | #define SAMPLE_COUNT 3 | |
35 | ||
36 | #define FRAC_BITS 8 | |
37 | #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) | |
38 | #define fp_toint(X) ((X) >> FRAC_BITS) | |
39 | ||
40 | static inline int32_t mul_fp(int32_t x, int32_t y) | |
41 | { | |
42 | return ((int64_t)x * (int64_t)y) >> FRAC_BITS; | |
43 | } | |
44 | ||
45 | static inline int32_t div_fp(int32_t x, int32_t y) | |
46 | { | |
47 | return div_s64((int64_t)x << FRAC_BITS, (int64_t)y); | |
48 | } | |
49 | ||
50 | struct sample { | |
d253d2a5 | 51 | int32_t core_pct_busy; |
93f0822d DB |
52 | u64 aperf; |
53 | u64 mperf; | |
54 | int freq; | |
55 | }; | |
56 | ||
57 | struct pstate_data { | |
58 | int current_pstate; | |
59 | int min_pstate; | |
60 | int max_pstate; | |
61 | int turbo_pstate; | |
62 | }; | |
63 | ||
64 | struct _pid { | |
65 | int setpoint; | |
66 | int32_t integral; | |
67 | int32_t p_gain; | |
68 | int32_t i_gain; | |
69 | int32_t d_gain; | |
70 | int deadband; | |
d253d2a5 | 71 | int32_t last_err; |
93f0822d DB |
72 | }; |
73 | ||
74 | struct cpudata { | |
75 | int cpu; | |
76 | ||
77 | char name[64]; | |
78 | ||
79 | struct timer_list timer; | |
80 | ||
81 | struct pstate_adjust_policy *pstate_policy; | |
82 | struct pstate_data pstate; | |
83 | struct _pid pid; | |
93f0822d DB |
84 | |
85 | int min_pstate_count; | |
93f0822d | 86 | |
93f0822d DB |
87 | u64 prev_aperf; |
88 | u64 prev_mperf; | |
89 | int sample_ptr; | |
90 | struct sample samples[SAMPLE_COUNT]; | |
91 | }; | |
92 | ||
93 | static struct cpudata **all_cpu_data; | |
94 | struct pstate_adjust_policy { | |
95 | int sample_rate_ms; | |
96 | int deadband; | |
97 | int setpoint; | |
98 | int p_gain_pct; | |
99 | int d_gain_pct; | |
100 | int i_gain_pct; | |
101 | }; | |
102 | ||
103 | static struct pstate_adjust_policy default_policy = { | |
104 | .sample_rate_ms = 10, | |
105 | .deadband = 0, | |
2134ed4d DB |
106 | .setpoint = 97, |
107 | .p_gain_pct = 20, | |
93f0822d | 108 | .d_gain_pct = 0, |
2134ed4d | 109 | .i_gain_pct = 0, |
93f0822d DB |
110 | }; |
111 | ||
112 | struct perf_limits { | |
113 | int no_turbo; | |
114 | int max_perf_pct; | |
115 | int min_perf_pct; | |
116 | int32_t max_perf; | |
117 | int32_t min_perf; | |
d8f469e9 DB |
118 | int max_policy_pct; |
119 | int max_sysfs_pct; | |
93f0822d DB |
120 | }; |
121 | ||
122 | static struct perf_limits limits = { | |
123 | .no_turbo = 0, | |
124 | .max_perf_pct = 100, | |
125 | .max_perf = int_tofp(1), | |
126 | .min_perf_pct = 0, | |
127 | .min_perf = 0, | |
d8f469e9 DB |
128 | .max_policy_pct = 100, |
129 | .max_sysfs_pct = 100, | |
93f0822d DB |
130 | }; |
131 | ||
132 | static inline void pid_reset(struct _pid *pid, int setpoint, int busy, | |
133 | int deadband, int integral) { | |
134 | pid->setpoint = setpoint; | |
135 | pid->deadband = deadband; | |
136 | pid->integral = int_tofp(integral); | |
137 | pid->last_err = setpoint - busy; | |
138 | } | |
139 | ||
140 | static inline void pid_p_gain_set(struct _pid *pid, int percent) | |
141 | { | |
142 | pid->p_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
143 | } | |
144 | ||
145 | static inline void pid_i_gain_set(struct _pid *pid, int percent) | |
146 | { | |
147 | pid->i_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
148 | } | |
149 | ||
150 | static inline void pid_d_gain_set(struct _pid *pid, int percent) | |
151 | { | |
152 | ||
153 | pid->d_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
154 | } | |
155 | ||
d253d2a5 | 156 | static signed int pid_calc(struct _pid *pid, int32_t busy) |
93f0822d | 157 | { |
d253d2a5 | 158 | signed int result; |
93f0822d DB |
159 | int32_t pterm, dterm, fp_error; |
160 | int32_t integral_limit; | |
161 | ||
d253d2a5 | 162 | fp_error = int_tofp(pid->setpoint) - busy; |
93f0822d | 163 | |
d253d2a5 | 164 | if (abs(fp_error) <= int_tofp(pid->deadband)) |
93f0822d DB |
165 | return 0; |
166 | ||
167 | pterm = mul_fp(pid->p_gain, fp_error); | |
168 | ||
169 | pid->integral += fp_error; | |
170 | ||
171 | /* limit the integral term */ | |
172 | integral_limit = int_tofp(30); | |
173 | if (pid->integral > integral_limit) | |
174 | pid->integral = integral_limit; | |
175 | if (pid->integral < -integral_limit) | |
176 | pid->integral = -integral_limit; | |
177 | ||
d253d2a5 BS |
178 | dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); |
179 | pid->last_err = fp_error; | |
93f0822d DB |
180 | |
181 | result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; | |
182 | ||
183 | return (signed int)fp_toint(result); | |
184 | } | |
185 | ||
186 | static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) | |
187 | { | |
188 | pid_p_gain_set(&cpu->pid, cpu->pstate_policy->p_gain_pct); | |
189 | pid_d_gain_set(&cpu->pid, cpu->pstate_policy->d_gain_pct); | |
190 | pid_i_gain_set(&cpu->pid, cpu->pstate_policy->i_gain_pct); | |
191 | ||
192 | pid_reset(&cpu->pid, | |
193 | cpu->pstate_policy->setpoint, | |
194 | 100, | |
195 | cpu->pstate_policy->deadband, | |
196 | 0); | |
197 | } | |
198 | ||
93f0822d DB |
199 | static inline void intel_pstate_reset_all_pid(void) |
200 | { | |
201 | unsigned int cpu; | |
202 | for_each_online_cpu(cpu) { | |
203 | if (all_cpu_data[cpu]) | |
204 | intel_pstate_busy_pid_reset(all_cpu_data[cpu]); | |
205 | } | |
206 | } | |
207 | ||
208 | /************************** debugfs begin ************************/ | |
209 | static int pid_param_set(void *data, u64 val) | |
210 | { | |
211 | *(u32 *)data = val; | |
212 | intel_pstate_reset_all_pid(); | |
213 | return 0; | |
214 | } | |
215 | static int pid_param_get(void *data, u64 *val) | |
216 | { | |
217 | *val = *(u32 *)data; | |
218 | return 0; | |
219 | } | |
220 | DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, | |
221 | pid_param_set, "%llu\n"); | |
222 | ||
223 | struct pid_param { | |
224 | char *name; | |
225 | void *value; | |
226 | }; | |
227 | ||
228 | static struct pid_param pid_files[] = { | |
229 | {"sample_rate_ms", &default_policy.sample_rate_ms}, | |
230 | {"d_gain_pct", &default_policy.d_gain_pct}, | |
231 | {"i_gain_pct", &default_policy.i_gain_pct}, | |
232 | {"deadband", &default_policy.deadband}, | |
233 | {"setpoint", &default_policy.setpoint}, | |
234 | {"p_gain_pct", &default_policy.p_gain_pct}, | |
235 | {NULL, NULL} | |
236 | }; | |
237 | ||
238 | static struct dentry *debugfs_parent; | |
239 | static void intel_pstate_debug_expose_params(void) | |
240 | { | |
241 | int i = 0; | |
242 | ||
243 | debugfs_parent = debugfs_create_dir("pstate_snb", NULL); | |
244 | if (IS_ERR_OR_NULL(debugfs_parent)) | |
245 | return; | |
246 | while (pid_files[i].name) { | |
247 | debugfs_create_file(pid_files[i].name, 0660, | |
248 | debugfs_parent, pid_files[i].value, | |
249 | &fops_pid_param); | |
250 | i++; | |
251 | } | |
252 | } | |
253 | ||
254 | /************************** debugfs end ************************/ | |
255 | ||
256 | /************************** sysfs begin ************************/ | |
257 | #define show_one(file_name, object) \ | |
258 | static ssize_t show_##file_name \ | |
259 | (struct kobject *kobj, struct attribute *attr, char *buf) \ | |
260 | { \ | |
261 | return sprintf(buf, "%u\n", limits.object); \ | |
262 | } | |
263 | ||
264 | static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, | |
265 | const char *buf, size_t count) | |
266 | { | |
267 | unsigned int input; | |
268 | int ret; | |
269 | ret = sscanf(buf, "%u", &input); | |
270 | if (ret != 1) | |
271 | return -EINVAL; | |
272 | limits.no_turbo = clamp_t(int, input, 0 , 1); | |
273 | ||
274 | return count; | |
275 | } | |
276 | ||
277 | static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, | |
278 | const char *buf, size_t count) | |
279 | { | |
280 | unsigned int input; | |
281 | int ret; | |
282 | ret = sscanf(buf, "%u", &input); | |
283 | if (ret != 1) | |
284 | return -EINVAL; | |
285 | ||
d8f469e9 DB |
286 | limits.max_sysfs_pct = clamp_t(int, input, 0 , 100); |
287 | limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct); | |
93f0822d DB |
288 | limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100)); |
289 | return count; | |
290 | } | |
291 | ||
292 | static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, | |
293 | const char *buf, size_t count) | |
294 | { | |
295 | unsigned int input; | |
296 | int ret; | |
297 | ret = sscanf(buf, "%u", &input); | |
298 | if (ret != 1) | |
299 | return -EINVAL; | |
300 | limits.min_perf_pct = clamp_t(int, input, 0 , 100); | |
301 | limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100)); | |
302 | ||
303 | return count; | |
304 | } | |
305 | ||
306 | show_one(no_turbo, no_turbo); | |
307 | show_one(max_perf_pct, max_perf_pct); | |
308 | show_one(min_perf_pct, min_perf_pct); | |
309 | ||
310 | define_one_global_rw(no_turbo); | |
311 | define_one_global_rw(max_perf_pct); | |
312 | define_one_global_rw(min_perf_pct); | |
313 | ||
314 | static struct attribute *intel_pstate_attributes[] = { | |
315 | &no_turbo.attr, | |
316 | &max_perf_pct.attr, | |
317 | &min_perf_pct.attr, | |
318 | NULL | |
319 | }; | |
320 | ||
321 | static struct attribute_group intel_pstate_attr_group = { | |
322 | .attrs = intel_pstate_attributes, | |
323 | }; | |
324 | static struct kobject *intel_pstate_kobject; | |
325 | ||
326 | static void intel_pstate_sysfs_expose_params(void) | |
327 | { | |
328 | int rc; | |
329 | ||
330 | intel_pstate_kobject = kobject_create_and_add("intel_pstate", | |
331 | &cpu_subsys.dev_root->kobj); | |
332 | BUG_ON(!intel_pstate_kobject); | |
333 | rc = sysfs_create_group(intel_pstate_kobject, | |
334 | &intel_pstate_attr_group); | |
335 | BUG_ON(rc); | |
336 | } | |
337 | ||
338 | /************************** sysfs end ************************/ | |
339 | ||
340 | static int intel_pstate_min_pstate(void) | |
341 | { | |
342 | u64 value; | |
05e99c8c | 343 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
344 | return (value >> 40) & 0xFF; |
345 | } | |
346 | ||
347 | static int intel_pstate_max_pstate(void) | |
348 | { | |
349 | u64 value; | |
05e99c8c | 350 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
351 | return (value >> 8) & 0xFF; |
352 | } | |
353 | ||
354 | static int intel_pstate_turbo_pstate(void) | |
355 | { | |
356 | u64 value; | |
357 | int nont, ret; | |
05e99c8c | 358 | rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); |
93f0822d DB |
359 | nont = intel_pstate_max_pstate(); |
360 | ret = ((value) & 255); | |
361 | if (ret <= nont) | |
362 | ret = nont; | |
363 | return ret; | |
364 | } | |
365 | ||
366 | static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) | |
367 | { | |
368 | int max_perf = cpu->pstate.turbo_pstate; | |
7244cb62 | 369 | int max_perf_adj; |
93f0822d DB |
370 | int min_perf; |
371 | if (limits.no_turbo) | |
372 | max_perf = cpu->pstate.max_pstate; | |
373 | ||
7244cb62 DB |
374 | max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf)); |
375 | *max = clamp_t(int, max_perf_adj, | |
93f0822d DB |
376 | cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); |
377 | ||
378 | min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf)); | |
379 | *min = clamp_t(int, min_perf, | |
380 | cpu->pstate.min_pstate, max_perf); | |
381 | } | |
382 | ||
383 | static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) | |
384 | { | |
385 | int max_perf, min_perf; | |
09c87e2f | 386 | u64 val; |
93f0822d DB |
387 | |
388 | intel_pstate_get_min_max(cpu, &min_perf, &max_perf); | |
389 | ||
390 | pstate = clamp_t(int, pstate, min_perf, max_perf); | |
391 | ||
392 | if (pstate == cpu->pstate.current_pstate) | |
393 | return; | |
394 | ||
93f0822d | 395 | trace_cpu_frequency(pstate * 100000, cpu->cpu); |
35363e94 | 396 | |
93f0822d | 397 | cpu->pstate.current_pstate = pstate; |
09c87e2f | 398 | val = pstate << 8; |
1ccf7a1c | 399 | if (limits.no_turbo) |
09c87e2f | 400 | val |= (u64)1 << 32; |
93f0822d | 401 | |
09c87e2f | 402 | wrmsrl(MSR_IA32_PERF_CTL, val); |
93f0822d DB |
403 | } |
404 | ||
405 | static inline void intel_pstate_pstate_increase(struct cpudata *cpu, int steps) | |
406 | { | |
407 | int target; | |
408 | target = cpu->pstate.current_pstate + steps; | |
409 | ||
410 | intel_pstate_set_pstate(cpu, target); | |
411 | } | |
412 | ||
413 | static inline void intel_pstate_pstate_decrease(struct cpudata *cpu, int steps) | |
414 | { | |
415 | int target; | |
416 | target = cpu->pstate.current_pstate - steps; | |
417 | intel_pstate_set_pstate(cpu, target); | |
418 | } | |
419 | ||
420 | static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) | |
421 | { | |
422 | sprintf(cpu->name, "Intel 2nd generation core"); | |
423 | ||
424 | cpu->pstate.min_pstate = intel_pstate_min_pstate(); | |
425 | cpu->pstate.max_pstate = intel_pstate_max_pstate(); | |
426 | cpu->pstate.turbo_pstate = intel_pstate_turbo_pstate(); | |
427 | ||
428 | /* | |
429 | * goto max pstate so we don't slow up boot if we are built-in if we are | |
430 | * a module we will take care of it during normal operation | |
431 | */ | |
432 | intel_pstate_set_pstate(cpu, cpu->pstate.max_pstate); | |
433 | } | |
434 | ||
435 | static inline void intel_pstate_calc_busy(struct cpudata *cpu, | |
436 | struct sample *sample) | |
437 | { | |
438 | u64 core_pct; | |
d253d2a5 BS |
439 | core_pct = div64_u64(int_tofp(sample->aperf * 100), |
440 | sample->mperf); | |
441 | sample->freq = fp_toint(cpu->pstate.max_pstate * core_pct * 1000); | |
93f0822d | 442 | |
1abc4b20 | 443 | sample->core_pct_busy = core_pct; |
93f0822d DB |
444 | } |
445 | ||
446 | static inline void intel_pstate_sample(struct cpudata *cpu) | |
447 | { | |
93f0822d DB |
448 | u64 aperf, mperf; |
449 | ||
93f0822d DB |
450 | rdmsrl(MSR_IA32_APERF, aperf); |
451 | rdmsrl(MSR_IA32_MPERF, mperf); | |
1abc4b20 DB |
452 | cpu->sample_ptr = (cpu->sample_ptr + 1) % SAMPLE_COUNT; |
453 | cpu->samples[cpu->sample_ptr].aperf = aperf; | |
454 | cpu->samples[cpu->sample_ptr].mperf = mperf; | |
455 | cpu->samples[cpu->sample_ptr].aperf -= cpu->prev_aperf; | |
456 | cpu->samples[cpu->sample_ptr].mperf -= cpu->prev_mperf; | |
457 | ||
458 | intel_pstate_calc_busy(cpu, &cpu->samples[cpu->sample_ptr]); | |
93f0822d | 459 | |
93f0822d DB |
460 | cpu->prev_aperf = aperf; |
461 | cpu->prev_mperf = mperf; | |
462 | } | |
463 | ||
464 | static inline void intel_pstate_set_sample_time(struct cpudata *cpu) | |
465 | { | |
466 | int sample_time, delay; | |
467 | ||
468 | sample_time = cpu->pstate_policy->sample_rate_ms; | |
469 | delay = msecs_to_jiffies(sample_time); | |
93f0822d DB |
470 | mod_timer_pinned(&cpu->timer, jiffies + delay); |
471 | } | |
472 | ||
d253d2a5 | 473 | static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu) |
93f0822d | 474 | { |
2134ed4d | 475 | int32_t core_busy, max_pstate, current_pstate; |
93f0822d | 476 | |
d253d2a5 | 477 | core_busy = cpu->samples[cpu->sample_ptr].core_pct_busy; |
2134ed4d | 478 | max_pstate = int_tofp(cpu->pstate.max_pstate); |
93f0822d | 479 | current_pstate = int_tofp(cpu->pstate.current_pstate); |
d253d2a5 | 480 | return mul_fp(core_busy, div_fp(max_pstate, current_pstate)); |
93f0822d DB |
481 | } |
482 | ||
483 | static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) | |
484 | { | |
d253d2a5 | 485 | int32_t busy_scaled; |
93f0822d DB |
486 | struct _pid *pid; |
487 | signed int ctl = 0; | |
488 | int steps; | |
489 | ||
490 | pid = &cpu->pid; | |
491 | busy_scaled = intel_pstate_get_scaled_busy(cpu); | |
492 | ||
493 | ctl = pid_calc(pid, busy_scaled); | |
494 | ||
495 | steps = abs(ctl); | |
496 | if (ctl < 0) | |
497 | intel_pstate_pstate_increase(cpu, steps); | |
498 | else | |
499 | intel_pstate_pstate_decrease(cpu, steps); | |
500 | } | |
501 | ||
93f0822d DB |
502 | static void intel_pstate_timer_func(unsigned long __data) |
503 | { | |
504 | struct cpudata *cpu = (struct cpudata *) __data; | |
505 | ||
506 | intel_pstate_sample(cpu); | |
ca182aee | 507 | intel_pstate_adjust_busy_pstate(cpu); |
93f0822d | 508 | |
93f0822d DB |
509 | if (cpu->pstate.current_pstate == cpu->pstate.min_pstate) { |
510 | cpu->min_pstate_count++; | |
511 | if (!(cpu->min_pstate_count % 5)) { | |
512 | intel_pstate_set_pstate(cpu, cpu->pstate.max_pstate); | |
93f0822d DB |
513 | } |
514 | } else | |
515 | cpu->min_pstate_count = 0; | |
ca182aee | 516 | |
93f0822d DB |
517 | intel_pstate_set_sample_time(cpu); |
518 | } | |
519 | ||
520 | #define ICPU(model, policy) \ | |
521 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&policy } | |
522 | ||
523 | static const struct x86_cpu_id intel_pstate_cpu_ids[] = { | |
524 | ICPU(0x2a, default_policy), | |
525 | ICPU(0x2d, default_policy), | |
c96d53d6 | 526 | ICPU(0x3a, default_policy), |
6cdcdb79 NH |
527 | ICPU(0x3c, default_policy), |
528 | ICPU(0x3e, default_policy), | |
529 | ICPU(0x3f, default_policy), | |
530 | ICPU(0x45, default_policy), | |
531 | ICPU(0x46, default_policy), | |
93f0822d DB |
532 | {} |
533 | }; | |
534 | MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); | |
535 | ||
536 | static int intel_pstate_init_cpu(unsigned int cpunum) | |
537 | { | |
538 | ||
539 | const struct x86_cpu_id *id; | |
540 | struct cpudata *cpu; | |
541 | ||
542 | id = x86_match_cpu(intel_pstate_cpu_ids); | |
543 | if (!id) | |
544 | return -ENODEV; | |
545 | ||
546 | all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), GFP_KERNEL); | |
547 | if (!all_cpu_data[cpunum]) | |
548 | return -ENOMEM; | |
549 | ||
550 | cpu = all_cpu_data[cpunum]; | |
551 | ||
552 | intel_pstate_get_cpu_pstates(cpu); | |
553 | ||
554 | cpu->cpu = cpunum; | |
555 | cpu->pstate_policy = | |
556 | (struct pstate_adjust_policy *)id->driver_data; | |
557 | init_timer_deferrable(&cpu->timer); | |
558 | cpu->timer.function = intel_pstate_timer_func; | |
559 | cpu->timer.data = | |
560 | (unsigned long)cpu; | |
561 | cpu->timer.expires = jiffies + HZ/100; | |
562 | intel_pstate_busy_pid_reset(cpu); | |
93f0822d DB |
563 | intel_pstate_sample(cpu); |
564 | intel_pstate_set_pstate(cpu, cpu->pstate.max_pstate); | |
565 | ||
566 | add_timer_on(&cpu->timer, cpunum); | |
567 | ||
568 | pr_info("Intel pstate controlling: cpu %d\n", cpunum); | |
569 | ||
570 | return 0; | |
571 | } | |
572 | ||
573 | static unsigned int intel_pstate_get(unsigned int cpu_num) | |
574 | { | |
575 | struct sample *sample; | |
576 | struct cpudata *cpu; | |
577 | ||
578 | cpu = all_cpu_data[cpu_num]; | |
579 | if (!cpu) | |
580 | return 0; | |
581 | sample = &cpu->samples[cpu->sample_ptr]; | |
582 | return sample->freq; | |
583 | } | |
584 | ||
585 | static int intel_pstate_set_policy(struct cpufreq_policy *policy) | |
586 | { | |
587 | struct cpudata *cpu; | |
93f0822d DB |
588 | |
589 | cpu = all_cpu_data[policy->cpu]; | |
590 | ||
d3929b83 DB |
591 | if (!policy->cpuinfo.max_freq) |
592 | return -ENODEV; | |
593 | ||
93f0822d DB |
594 | if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { |
595 | limits.min_perf_pct = 100; | |
596 | limits.min_perf = int_tofp(1); | |
597 | limits.max_perf_pct = 100; | |
598 | limits.max_perf = int_tofp(1); | |
599 | limits.no_turbo = 0; | |
d1b68485 | 600 | return 0; |
93f0822d | 601 | } |
d1b68485 SP |
602 | limits.min_perf_pct = (policy->min * 100) / policy->cpuinfo.max_freq; |
603 | limits.min_perf_pct = clamp_t(int, limits.min_perf_pct, 0 , 100); | |
604 | limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100)); | |
605 | ||
d8f469e9 DB |
606 | limits.max_policy_pct = policy->max * 100 / policy->cpuinfo.max_freq; |
607 | limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100); | |
608 | limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct); | |
d1b68485 | 609 | limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100)); |
93f0822d DB |
610 | |
611 | return 0; | |
612 | } | |
613 | ||
614 | static int intel_pstate_verify_policy(struct cpufreq_policy *policy) | |
615 | { | |
616 | cpufreq_verify_within_limits(policy, | |
617 | policy->cpuinfo.min_freq, | |
618 | policy->cpuinfo.max_freq); | |
619 | ||
620 | if ((policy->policy != CPUFREQ_POLICY_POWERSAVE) && | |
621 | (policy->policy != CPUFREQ_POLICY_PERFORMANCE)) | |
622 | return -EINVAL; | |
623 | ||
624 | return 0; | |
625 | } | |
626 | ||
2760984f | 627 | static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) |
93f0822d DB |
628 | { |
629 | int cpu = policy->cpu; | |
630 | ||
631 | del_timer(&all_cpu_data[cpu]->timer); | |
632 | kfree(all_cpu_data[cpu]); | |
633 | all_cpu_data[cpu] = NULL; | |
634 | return 0; | |
635 | } | |
636 | ||
2760984f | 637 | static int intel_pstate_cpu_init(struct cpufreq_policy *policy) |
93f0822d | 638 | { |
93f0822d | 639 | struct cpudata *cpu; |
52e0a509 | 640 | int rc; |
93f0822d DB |
641 | |
642 | rc = intel_pstate_init_cpu(policy->cpu); | |
643 | if (rc) | |
644 | return rc; | |
645 | ||
646 | cpu = all_cpu_data[policy->cpu]; | |
647 | ||
648 | if (!limits.no_turbo && | |
649 | limits.min_perf_pct == 100 && limits.max_perf_pct == 100) | |
650 | policy->policy = CPUFREQ_POLICY_PERFORMANCE; | |
651 | else | |
652 | policy->policy = CPUFREQ_POLICY_POWERSAVE; | |
653 | ||
52e0a509 DB |
654 | policy->min = cpu->pstate.min_pstate * 100000; |
655 | policy->max = cpu->pstate.turbo_pstate * 100000; | |
93f0822d DB |
656 | |
657 | /* cpuinfo and default policy values */ | |
658 | policy->cpuinfo.min_freq = cpu->pstate.min_pstate * 100000; | |
659 | policy->cpuinfo.max_freq = cpu->pstate.turbo_pstate * 100000; | |
660 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; | |
661 | cpumask_set_cpu(policy->cpu, policy->cpus); | |
662 | ||
663 | return 0; | |
664 | } | |
665 | ||
666 | static struct cpufreq_driver intel_pstate_driver = { | |
667 | .flags = CPUFREQ_CONST_LOOPS, | |
668 | .verify = intel_pstate_verify_policy, | |
669 | .setpolicy = intel_pstate_set_policy, | |
670 | .get = intel_pstate_get, | |
671 | .init = intel_pstate_cpu_init, | |
672 | .exit = intel_pstate_cpu_exit, | |
673 | .name = "intel_pstate", | |
93f0822d DB |
674 | }; |
675 | ||
6be26498 DB |
676 | static int __initdata no_load; |
677 | ||
b563b4e3 DB |
678 | static int intel_pstate_msrs_not_valid(void) |
679 | { | |
680 | /* Check that all the msr's we are using are valid. */ | |
681 | u64 aperf, mperf, tmp; | |
682 | ||
683 | rdmsrl(MSR_IA32_APERF, aperf); | |
684 | rdmsrl(MSR_IA32_MPERF, mperf); | |
685 | ||
686 | if (!intel_pstate_min_pstate() || | |
687 | !intel_pstate_max_pstate() || | |
688 | !intel_pstate_turbo_pstate()) | |
689 | return -ENODEV; | |
690 | ||
691 | rdmsrl(MSR_IA32_APERF, tmp); | |
692 | if (!(tmp - aperf)) | |
693 | return -ENODEV; | |
694 | ||
695 | rdmsrl(MSR_IA32_MPERF, tmp); | |
696 | if (!(tmp - mperf)) | |
697 | return -ENODEV; | |
698 | ||
699 | return 0; | |
700 | } | |
93f0822d DB |
701 | static int __init intel_pstate_init(void) |
702 | { | |
907cc908 | 703 | int cpu, rc = 0; |
93f0822d DB |
704 | const struct x86_cpu_id *id; |
705 | ||
6be26498 DB |
706 | if (no_load) |
707 | return -ENODEV; | |
708 | ||
93f0822d DB |
709 | id = x86_match_cpu(intel_pstate_cpu_ids); |
710 | if (!id) | |
711 | return -ENODEV; | |
712 | ||
b563b4e3 DB |
713 | if (intel_pstate_msrs_not_valid()) |
714 | return -ENODEV; | |
715 | ||
93f0822d DB |
716 | pr_info("Intel P-state driver initializing.\n"); |
717 | ||
b57ffac5 | 718 | all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); |
93f0822d DB |
719 | if (!all_cpu_data) |
720 | return -ENOMEM; | |
93f0822d DB |
721 | |
722 | rc = cpufreq_register_driver(&intel_pstate_driver); | |
723 | if (rc) | |
724 | goto out; | |
725 | ||
726 | intel_pstate_debug_expose_params(); | |
727 | intel_pstate_sysfs_expose_params(); | |
728 | return rc; | |
729 | out: | |
907cc908 DB |
730 | get_online_cpus(); |
731 | for_each_online_cpu(cpu) { | |
732 | if (all_cpu_data[cpu]) { | |
733 | del_timer_sync(&all_cpu_data[cpu]->timer); | |
734 | kfree(all_cpu_data[cpu]); | |
735 | } | |
736 | } | |
737 | ||
738 | put_online_cpus(); | |
739 | vfree(all_cpu_data); | |
93f0822d DB |
740 | return -ENODEV; |
741 | } | |
742 | device_initcall(intel_pstate_init); | |
743 | ||
6be26498 DB |
744 | static int __init intel_pstate_setup(char *str) |
745 | { | |
746 | if (!str) | |
747 | return -EINVAL; | |
748 | ||
749 | if (!strcmp(str, "disable")) | |
750 | no_load = 1; | |
751 | return 0; | |
752 | } | |
753 | early_param("intel_pstate", intel_pstate_setup); | |
754 | ||
93f0822d DB |
755 | MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); |
756 | MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); | |
757 | MODULE_LICENSE("GPL"); |