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1453863f PCC |
1 | /* |
2 | * Copyright (c) 2015 Linaro Ltd. | |
3 | * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
15 | #include <linux/clk.h> | |
16 | #include <linux/cpu.h> | |
17 | #include <linux/cpu_cooling.h> | |
18 | #include <linux/cpufreq.h> | |
19 | #include <linux/cpumask.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/pm_opp.h> | |
23 | #include <linux/regulator/consumer.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/thermal.h> | |
26 | ||
27 | #define MIN_VOLT_SHIFT (100000) | |
28 | #define MAX_VOLT_SHIFT (200000) | |
29 | #define MAX_VOLT_LIMIT (1150000) | |
30 | #define VOLT_TOL (10000) | |
31 | ||
32 | /* | |
33 | * The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS | |
34 | * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in | |
35 | * Mediatek SoCs has two voltage inputs, Vproc and Vsram. In some cases the two | |
36 | * voltage inputs need to be controlled under a hardware limitation: | |
37 | * 100mV < Vsram - Vproc < 200mV | |
38 | * | |
39 | * When scaling the clock frequency of a CPU clock domain, the clock source | |
40 | * needs to be switched to another stable PLL clock temporarily until | |
41 | * the original PLL becomes stable at target frequency. | |
42 | */ | |
43 | struct mtk_cpu_dvfs_info { | |
89b56047 | 44 | struct cpumask cpus; |
1453863f PCC |
45 | struct device *cpu_dev; |
46 | struct regulator *proc_reg; | |
47 | struct regulator *sram_reg; | |
48 | struct clk *cpu_clk; | |
49 | struct clk *inter_clk; | |
50 | struct thermal_cooling_device *cdev; | |
89b56047 | 51 | struct list_head list_head; |
1453863f PCC |
52 | int intermediate_voltage; |
53 | bool need_voltage_tracking; | |
54 | }; | |
55 | ||
89b56047 PCC |
56 | static LIST_HEAD(dvfs_info_list); |
57 | ||
58 | static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu) | |
59 | { | |
60 | struct mtk_cpu_dvfs_info *info; | |
61 | struct list_head *list; | |
62 | ||
63 | list_for_each(list, &dvfs_info_list) { | |
64 | info = list_entry(list, struct mtk_cpu_dvfs_info, list_head); | |
65 | ||
66 | if (cpumask_test_cpu(cpu, &info->cpus)) | |
67 | return info; | |
68 | } | |
69 | ||
70 | return NULL; | |
71 | } | |
72 | ||
1453863f PCC |
73 | static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info, |
74 | int new_vproc) | |
75 | { | |
76 | struct regulator *proc_reg = info->proc_reg; | |
77 | struct regulator *sram_reg = info->sram_reg; | |
78 | int old_vproc, old_vsram, new_vsram, vsram, vproc, ret; | |
79 | ||
80 | old_vproc = regulator_get_voltage(proc_reg); | |
40be4c3c PCC |
81 | if (old_vproc < 0) { |
82 | pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc); | |
83 | return old_vproc; | |
84 | } | |
1453863f PCC |
85 | /* Vsram should not exceed the maximum allowed voltage of SoC. */ |
86 | new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT); | |
87 | ||
88 | if (old_vproc < new_vproc) { | |
89 | /* | |
90 | * When scaling up voltages, Vsram and Vproc scale up step | |
91 | * by step. At each step, set Vsram to (Vproc + 200mV) first, | |
92 | * then set Vproc to (Vsram - 100mV). | |
93 | * Keep doing it until Vsram and Vproc hit target voltages. | |
94 | */ | |
95 | do { | |
96 | old_vsram = regulator_get_voltage(sram_reg); | |
40be4c3c PCC |
97 | if (old_vsram < 0) { |
98 | pr_err("%s: invalid Vsram value: %d\n", | |
99 | __func__, old_vsram); | |
100 | return old_vsram; | |
101 | } | |
1453863f | 102 | old_vproc = regulator_get_voltage(proc_reg); |
40be4c3c PCC |
103 | if (old_vproc < 0) { |
104 | pr_err("%s: invalid Vproc value: %d\n", | |
105 | __func__, old_vproc); | |
106 | return old_vproc; | |
107 | } | |
1453863f PCC |
108 | |
109 | vsram = min(new_vsram, old_vproc + MAX_VOLT_SHIFT); | |
110 | ||
111 | if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) { | |
112 | vsram = MAX_VOLT_LIMIT; | |
113 | ||
114 | /* | |
115 | * If the target Vsram hits the maximum voltage, | |
116 | * try to set the exact voltage value first. | |
117 | */ | |
118 | ret = regulator_set_voltage(sram_reg, vsram, | |
119 | vsram); | |
120 | if (ret) | |
121 | ret = regulator_set_voltage(sram_reg, | |
122 | vsram - VOLT_TOL, | |
123 | vsram); | |
124 | ||
125 | vproc = new_vproc; | |
126 | } else { | |
127 | ret = regulator_set_voltage(sram_reg, vsram, | |
128 | vsram + VOLT_TOL); | |
129 | ||
130 | vproc = vsram - MIN_VOLT_SHIFT; | |
131 | } | |
132 | if (ret) | |
133 | return ret; | |
134 | ||
135 | ret = regulator_set_voltage(proc_reg, vproc, | |
136 | vproc + VOLT_TOL); | |
137 | if (ret) { | |
138 | regulator_set_voltage(sram_reg, old_vsram, | |
139 | old_vsram); | |
140 | return ret; | |
141 | } | |
142 | } while (vproc < new_vproc || vsram < new_vsram); | |
143 | } else if (old_vproc > new_vproc) { | |
144 | /* | |
145 | * When scaling down voltages, Vsram and Vproc scale down step | |
146 | * by step. At each step, set Vproc to (Vsram - 200mV) first, | |
147 | * then set Vproc to (Vproc + 100mV). | |
148 | * Keep doing it until Vsram and Vproc hit target voltages. | |
149 | */ | |
150 | do { | |
151 | old_vproc = regulator_get_voltage(proc_reg); | |
40be4c3c PCC |
152 | if (old_vproc < 0) { |
153 | pr_err("%s: invalid Vproc value: %d\n", | |
154 | __func__, old_vproc); | |
155 | return old_vproc; | |
156 | } | |
1453863f | 157 | old_vsram = regulator_get_voltage(sram_reg); |
40be4c3c PCC |
158 | if (old_vsram < 0) { |
159 | pr_err("%s: invalid Vsram value: %d\n", | |
160 | __func__, old_vsram); | |
161 | return old_vsram; | |
162 | } | |
1453863f PCC |
163 | |
164 | vproc = max(new_vproc, old_vsram - MAX_VOLT_SHIFT); | |
165 | ret = regulator_set_voltage(proc_reg, vproc, | |
166 | vproc + VOLT_TOL); | |
167 | if (ret) | |
168 | return ret; | |
169 | ||
170 | if (vproc == new_vproc) | |
171 | vsram = new_vsram; | |
172 | else | |
173 | vsram = max(new_vsram, vproc + MIN_VOLT_SHIFT); | |
174 | ||
175 | if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) { | |
176 | vsram = MAX_VOLT_LIMIT; | |
177 | ||
178 | /* | |
179 | * If the target Vsram hits the maximum voltage, | |
180 | * try to set the exact voltage value first. | |
181 | */ | |
182 | ret = regulator_set_voltage(sram_reg, vsram, | |
183 | vsram); | |
184 | if (ret) | |
185 | ret = regulator_set_voltage(sram_reg, | |
186 | vsram - VOLT_TOL, | |
187 | vsram); | |
188 | } else { | |
189 | ret = regulator_set_voltage(sram_reg, vsram, | |
190 | vsram + VOLT_TOL); | |
191 | } | |
192 | ||
193 | if (ret) { | |
194 | regulator_set_voltage(proc_reg, old_vproc, | |
195 | old_vproc); | |
196 | return ret; | |
197 | } | |
198 | } while (vproc > new_vproc + VOLT_TOL || | |
199 | vsram > new_vsram + VOLT_TOL); | |
200 | } | |
201 | ||
202 | return 0; | |
203 | } | |
204 | ||
205 | static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc) | |
206 | { | |
207 | if (info->need_voltage_tracking) | |
208 | return mtk_cpufreq_voltage_tracking(info, vproc); | |
209 | else | |
210 | return regulator_set_voltage(info->proc_reg, vproc, | |
211 | vproc + VOLT_TOL); | |
212 | } | |
213 | ||
214 | static int mtk_cpufreq_set_target(struct cpufreq_policy *policy, | |
215 | unsigned int index) | |
216 | { | |
217 | struct cpufreq_frequency_table *freq_table = policy->freq_table; | |
218 | struct clk *cpu_clk = policy->clk; | |
219 | struct clk *armpll = clk_get_parent(cpu_clk); | |
220 | struct mtk_cpu_dvfs_info *info = policy->driver_data; | |
221 | struct device *cpu_dev = info->cpu_dev; | |
222 | struct dev_pm_opp *opp; | |
223 | long freq_hz, old_freq_hz; | |
224 | int vproc, old_vproc, inter_vproc, target_vproc, ret; | |
225 | ||
226 | inter_vproc = info->intermediate_voltage; | |
227 | ||
228 | old_freq_hz = clk_get_rate(cpu_clk); | |
229 | old_vproc = regulator_get_voltage(info->proc_reg); | |
40be4c3c PCC |
230 | if (old_vproc < 0) { |
231 | pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc); | |
232 | return old_vproc; | |
233 | } | |
1453863f PCC |
234 | |
235 | freq_hz = freq_table[index].frequency * 1000; | |
236 | ||
237 | rcu_read_lock(); | |
238 | opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz); | |
239 | if (IS_ERR(opp)) { | |
240 | rcu_read_unlock(); | |
241 | pr_err("cpu%d: failed to find OPP for %ld\n", | |
242 | policy->cpu, freq_hz); | |
243 | return PTR_ERR(opp); | |
244 | } | |
245 | vproc = dev_pm_opp_get_voltage(opp); | |
246 | rcu_read_unlock(); | |
247 | ||
248 | /* | |
249 | * If the new voltage or the intermediate voltage is higher than the | |
250 | * current voltage, scale up voltage first. | |
251 | */ | |
252 | target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc; | |
253 | if (old_vproc < target_vproc) { | |
254 | ret = mtk_cpufreq_set_voltage(info, target_vproc); | |
255 | if (ret) { | |
256 | pr_err("cpu%d: failed to scale up voltage!\n", | |
257 | policy->cpu); | |
258 | mtk_cpufreq_set_voltage(info, old_vproc); | |
259 | return ret; | |
260 | } | |
261 | } | |
262 | ||
263 | /* Reparent the CPU clock to intermediate clock. */ | |
264 | ret = clk_set_parent(cpu_clk, info->inter_clk); | |
265 | if (ret) { | |
266 | pr_err("cpu%d: failed to re-parent cpu clock!\n", | |
267 | policy->cpu); | |
268 | mtk_cpufreq_set_voltage(info, old_vproc); | |
269 | WARN_ON(1); | |
270 | return ret; | |
271 | } | |
272 | ||
273 | /* Set the original PLL to target rate. */ | |
274 | ret = clk_set_rate(armpll, freq_hz); | |
275 | if (ret) { | |
276 | pr_err("cpu%d: failed to scale cpu clock rate!\n", | |
277 | policy->cpu); | |
278 | clk_set_parent(cpu_clk, armpll); | |
279 | mtk_cpufreq_set_voltage(info, old_vproc); | |
280 | return ret; | |
281 | } | |
282 | ||
283 | /* Set parent of CPU clock back to the original PLL. */ | |
284 | ret = clk_set_parent(cpu_clk, armpll); | |
285 | if (ret) { | |
286 | pr_err("cpu%d: failed to re-parent cpu clock!\n", | |
287 | policy->cpu); | |
288 | mtk_cpufreq_set_voltage(info, inter_vproc); | |
289 | WARN_ON(1); | |
290 | return ret; | |
291 | } | |
292 | ||
293 | /* | |
294 | * If the new voltage is lower than the intermediate voltage or the | |
295 | * original voltage, scale down to the new voltage. | |
296 | */ | |
297 | if (vproc < inter_vproc || vproc < old_vproc) { | |
298 | ret = mtk_cpufreq_set_voltage(info, vproc); | |
299 | if (ret) { | |
300 | pr_err("cpu%d: failed to scale down voltage!\n", | |
301 | policy->cpu); | |
302 | clk_set_parent(cpu_clk, info->inter_clk); | |
303 | clk_set_rate(armpll, old_freq_hz); | |
304 | clk_set_parent(cpu_clk, armpll); | |
305 | return ret; | |
306 | } | |
307 | } | |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
312 | static void mtk_cpufreq_ready(struct cpufreq_policy *policy) | |
313 | { | |
314 | struct mtk_cpu_dvfs_info *info = policy->driver_data; | |
315 | struct device_node *np = of_node_get(info->cpu_dev->of_node); | |
316 | ||
317 | if (WARN_ON(!np)) | |
318 | return; | |
319 | ||
320 | if (of_find_property(np, "#cooling-cells", NULL)) { | |
321 | info->cdev = of_cpufreq_cooling_register(np, | |
322 | policy->related_cpus); | |
323 | ||
324 | if (IS_ERR(info->cdev)) { | |
325 | dev_err(info->cpu_dev, | |
326 | "running cpufreq without cooling device: %ld\n", | |
327 | PTR_ERR(info->cdev)); | |
328 | ||
329 | info->cdev = NULL; | |
330 | } | |
331 | } | |
332 | ||
333 | of_node_put(np); | |
334 | } | |
335 | ||
336 | static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu) | |
337 | { | |
338 | struct device *cpu_dev; | |
339 | struct regulator *proc_reg = ERR_PTR(-ENODEV); | |
340 | struct regulator *sram_reg = ERR_PTR(-ENODEV); | |
341 | struct clk *cpu_clk = ERR_PTR(-ENODEV); | |
342 | struct clk *inter_clk = ERR_PTR(-ENODEV); | |
343 | struct dev_pm_opp *opp; | |
344 | unsigned long rate; | |
345 | int ret; | |
346 | ||
347 | cpu_dev = get_cpu_device(cpu); | |
348 | if (!cpu_dev) { | |
349 | pr_err("failed to get cpu%d device\n", cpu); | |
350 | return -ENODEV; | |
351 | } | |
352 | ||
353 | cpu_clk = clk_get(cpu_dev, "cpu"); | |
354 | if (IS_ERR(cpu_clk)) { | |
355 | if (PTR_ERR(cpu_clk) == -EPROBE_DEFER) | |
356 | pr_warn("cpu clk for cpu%d not ready, retry.\n", cpu); | |
357 | else | |
358 | pr_err("failed to get cpu clk for cpu%d\n", cpu); | |
359 | ||
360 | ret = PTR_ERR(cpu_clk); | |
361 | return ret; | |
362 | } | |
363 | ||
364 | inter_clk = clk_get(cpu_dev, "intermediate"); | |
365 | if (IS_ERR(inter_clk)) { | |
366 | if (PTR_ERR(inter_clk) == -EPROBE_DEFER) | |
367 | pr_warn("intermediate clk for cpu%d not ready, retry.\n", | |
368 | cpu); | |
369 | else | |
370 | pr_err("failed to get intermediate clk for cpu%d\n", | |
371 | cpu); | |
372 | ||
373 | ret = PTR_ERR(inter_clk); | |
374 | goto out_free_resources; | |
375 | } | |
376 | ||
377 | proc_reg = regulator_get_exclusive(cpu_dev, "proc"); | |
378 | if (IS_ERR(proc_reg)) { | |
379 | if (PTR_ERR(proc_reg) == -EPROBE_DEFER) | |
380 | pr_warn("proc regulator for cpu%d not ready, retry.\n", | |
381 | cpu); | |
382 | else | |
383 | pr_err("failed to get proc regulator for cpu%d\n", | |
384 | cpu); | |
385 | ||
386 | ret = PTR_ERR(proc_reg); | |
387 | goto out_free_resources; | |
388 | } | |
389 | ||
390 | /* Both presence and absence of sram regulator are valid cases. */ | |
391 | sram_reg = regulator_get_exclusive(cpu_dev, "sram"); | |
392 | ||
a889331d PCC |
393 | /* Get OPP-sharing information from "operating-points-v2" bindings */ |
394 | ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus); | |
395 | if (ret) { | |
396 | pr_err("failed to get OPP-sharing information for cpu%d\n", | |
397 | cpu); | |
398 | goto out_free_resources; | |
399 | } | |
400 | ||
401 | ret = dev_pm_opp_of_cpumask_add_table(&info->cpus); | |
1453863f PCC |
402 | if (ret) { |
403 | pr_warn("no OPP table for cpu%d\n", cpu); | |
404 | goto out_free_resources; | |
405 | } | |
406 | ||
407 | /* Search a safe voltage for intermediate frequency. */ | |
408 | rate = clk_get_rate(inter_clk); | |
409 | rcu_read_lock(); | |
410 | opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate); | |
411 | if (IS_ERR(opp)) { | |
412 | rcu_read_unlock(); | |
413 | pr_err("failed to get intermediate opp for cpu%d\n", cpu); | |
414 | ret = PTR_ERR(opp); | |
415 | goto out_free_opp_table; | |
416 | } | |
417 | info->intermediate_voltage = dev_pm_opp_get_voltage(opp); | |
418 | rcu_read_unlock(); | |
419 | ||
420 | info->cpu_dev = cpu_dev; | |
421 | info->proc_reg = proc_reg; | |
422 | info->sram_reg = IS_ERR(sram_reg) ? NULL : sram_reg; | |
423 | info->cpu_clk = cpu_clk; | |
424 | info->inter_clk = inter_clk; | |
425 | ||
426 | /* | |
427 | * If SRAM regulator is present, software "voltage tracking" is needed | |
428 | * for this CPU power domain. | |
429 | */ | |
430 | info->need_voltage_tracking = !IS_ERR(sram_reg); | |
431 | ||
432 | return 0; | |
433 | ||
434 | out_free_opp_table: | |
a889331d | 435 | dev_pm_opp_of_cpumask_remove_table(&info->cpus); |
1453863f PCC |
436 | |
437 | out_free_resources: | |
438 | if (!IS_ERR(proc_reg)) | |
439 | regulator_put(proc_reg); | |
440 | if (!IS_ERR(sram_reg)) | |
441 | regulator_put(sram_reg); | |
442 | if (!IS_ERR(cpu_clk)) | |
443 | clk_put(cpu_clk); | |
444 | if (!IS_ERR(inter_clk)) | |
445 | clk_put(inter_clk); | |
446 | ||
447 | return ret; | |
448 | } | |
449 | ||
450 | static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info) | |
451 | { | |
452 | if (!IS_ERR(info->proc_reg)) | |
453 | regulator_put(info->proc_reg); | |
454 | if (!IS_ERR(info->sram_reg)) | |
455 | regulator_put(info->sram_reg); | |
456 | if (!IS_ERR(info->cpu_clk)) | |
457 | clk_put(info->cpu_clk); | |
458 | if (!IS_ERR(info->inter_clk)) | |
459 | clk_put(info->inter_clk); | |
460 | ||
a889331d | 461 | dev_pm_opp_of_cpumask_remove_table(&info->cpus); |
1453863f PCC |
462 | } |
463 | ||
464 | static int mtk_cpufreq_init(struct cpufreq_policy *policy) | |
465 | { | |
466 | struct mtk_cpu_dvfs_info *info; | |
467 | struct cpufreq_frequency_table *freq_table; | |
468 | int ret; | |
469 | ||
89b56047 PCC |
470 | info = mtk_cpu_dvfs_info_lookup(policy->cpu); |
471 | if (!info) { | |
472 | pr_err("dvfs info for cpu%d is not initialized.\n", | |
473 | policy->cpu); | |
474 | return -EINVAL; | |
1453863f PCC |
475 | } |
476 | ||
477 | ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table); | |
478 | if (ret) { | |
479 | pr_err("failed to init cpufreq table for cpu%d: %d\n", | |
480 | policy->cpu, ret); | |
89b56047 | 481 | return ret; |
1453863f PCC |
482 | } |
483 | ||
484 | ret = cpufreq_table_validate_and_show(policy, freq_table); | |
485 | if (ret) { | |
486 | pr_err("%s: invalid frequency table: %d\n", __func__, ret); | |
487 | goto out_free_cpufreq_table; | |
488 | } | |
489 | ||
89b56047 | 490 | cpumask_copy(policy->cpus, &info->cpus); |
1453863f PCC |
491 | policy->driver_data = info; |
492 | policy->clk = info->cpu_clk; | |
493 | ||
494 | return 0; | |
495 | ||
496 | out_free_cpufreq_table: | |
497 | dev_pm_opp_free_cpufreq_table(info->cpu_dev, &freq_table); | |
1453863f PCC |
498 | return ret; |
499 | } | |
500 | ||
501 | static int mtk_cpufreq_exit(struct cpufreq_policy *policy) | |
502 | { | |
503 | struct mtk_cpu_dvfs_info *info = policy->driver_data; | |
504 | ||
505 | cpufreq_cooling_unregister(info->cdev); | |
506 | dev_pm_opp_free_cpufreq_table(info->cpu_dev, &policy->freq_table); | |
1453863f PCC |
507 | |
508 | return 0; | |
509 | } | |
510 | ||
511 | static struct cpufreq_driver mt8173_cpufreq_driver = { | |
9bb46b87 PCC |
512 | .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK | |
513 | CPUFREQ_HAVE_GOVERNOR_PER_POLICY, | |
1453863f PCC |
514 | .verify = cpufreq_generic_frequency_table_verify, |
515 | .target_index = mtk_cpufreq_set_target, | |
516 | .get = cpufreq_generic_get, | |
517 | .init = mtk_cpufreq_init, | |
518 | .exit = mtk_cpufreq_exit, | |
519 | .ready = mtk_cpufreq_ready, | |
520 | .name = "mtk-cpufreq", | |
521 | .attr = cpufreq_generic_attr, | |
522 | }; | |
523 | ||
524 | static int mt8173_cpufreq_probe(struct platform_device *pdev) | |
525 | { | |
89b56047 PCC |
526 | struct mtk_cpu_dvfs_info *info; |
527 | struct list_head *list, *tmp; | |
528 | int cpu, ret; | |
529 | ||
530 | for_each_possible_cpu(cpu) { | |
531 | info = mtk_cpu_dvfs_info_lookup(cpu); | |
532 | if (info) | |
533 | continue; | |
534 | ||
535 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); | |
536 | if (!info) { | |
537 | ret = -ENOMEM; | |
538 | goto release_dvfs_info_list; | |
539 | } | |
540 | ||
541 | ret = mtk_cpu_dvfs_info_init(info, cpu); | |
542 | if (ret) { | |
543 | dev_err(&pdev->dev, | |
544 | "failed to initialize dvfs info for cpu%d\n", | |
545 | cpu); | |
546 | goto release_dvfs_info_list; | |
547 | } | |
548 | ||
549 | list_add(&info->list_head, &dvfs_info_list); | |
550 | } | |
1453863f PCC |
551 | |
552 | ret = cpufreq_register_driver(&mt8173_cpufreq_driver); | |
89b56047 PCC |
553 | if (ret) { |
554 | dev_err(&pdev->dev, "failed to register mtk cpufreq driver\n"); | |
555 | goto release_dvfs_info_list; | |
556 | } | |
557 | ||
558 | return 0; | |
559 | ||
560 | release_dvfs_info_list: | |
561 | list_for_each_safe(list, tmp, &dvfs_info_list) { | |
562 | info = list_entry(list, struct mtk_cpu_dvfs_info, list_head); | |
563 | ||
564 | mtk_cpu_dvfs_info_release(info); | |
565 | list_del(list); | |
566 | } | |
1453863f PCC |
567 | |
568 | return ret; | |
569 | } | |
570 | ||
571 | static struct platform_driver mt8173_cpufreq_platdrv = { | |
572 | .driver = { | |
573 | .name = "mt8173-cpufreq", | |
574 | }, | |
575 | .probe = mt8173_cpufreq_probe, | |
576 | }; | |
577 | ||
578 | static int mt8173_cpufreq_driver_init(void) | |
579 | { | |
580 | struct platform_device *pdev; | |
581 | int err; | |
582 | ||
583 | if (!of_machine_is_compatible("mediatek,mt8173")) | |
584 | return -ENODEV; | |
585 | ||
586 | err = platform_driver_register(&mt8173_cpufreq_platdrv); | |
587 | if (err) | |
588 | return err; | |
589 | ||
590 | /* | |
591 | * Since there's no place to hold device registration code and no | |
592 | * device tree based way to match cpufreq driver yet, both the driver | |
593 | * and the device registration codes are put here to handle defer | |
594 | * probing. | |
595 | */ | |
596 | pdev = platform_device_register_simple("mt8173-cpufreq", -1, NULL, 0); | |
597 | if (IS_ERR(pdev)) { | |
598 | pr_err("failed to register mtk-cpufreq platform device\n"); | |
599 | return PTR_ERR(pdev); | |
600 | } | |
601 | ||
602 | return 0; | |
603 | } | |
604 | device_initcall(mt8173_cpufreq_driver_init); |