Commit | Line | Data |
---|---|---|
ec6bced6 | 1 | /* |
ffe4f0f1 | 2 | * CPU frequency scaling for OMAP using OPP information |
ec6bced6 TL |
3 | * |
4 | * Copyright (C) 2005 Nokia Corporation | |
5 | * Written by Tony Lindgren <tony@atomide.com> | |
6 | * | |
7 | * Based on cpu-sa1110.c, Copyright (C) 2001 Russell King | |
8 | * | |
731e0cc6 SS |
9 | * Copyright (C) 2007-2011 Texas Instruments, Inc. |
10 | * - OMAP3/4 support by Rajendra Nayak, Santosh Shilimkar | |
11 | * | |
ec6bced6 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
1c5864e2 JP |
16 | |
17 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
18 | ||
ec6bced6 TL |
19 | #include <linux/types.h> |
20 | #include <linux/kernel.h> | |
21 | #include <linux/sched.h> | |
22 | #include <linux/cpufreq.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/err.h> | |
f8ce2547 | 26 | #include <linux/clk.h> |
fced80c7 | 27 | #include <linux/io.h> |
e4db1c74 | 28 | #include <linux/pm_opp.h> |
46c12216 | 29 | #include <linux/cpu.h> |
c1b547bc | 30 | #include <linux/module.h> |
49ded525 | 31 | #include <linux/platform_device.h> |
53dfe8a8 | 32 | #include <linux/regulator/consumer.h> |
ec6bced6 | 33 | |
731e0cc6 | 34 | #include <asm/smp_plat.h> |
46c12216 | 35 | #include <asm/cpu.h> |
ec6bced6 | 36 | |
42daffd2 AM |
37 | /* OPP tolerance in percentage */ |
38 | #define OPP_TOLERANCE 4 | |
39 | ||
731e0cc6 | 40 | static struct cpufreq_frequency_table *freq_table; |
1c78217f | 41 | static atomic_t freq_table_users = ATOMIC_INIT(0); |
a820ffa8 | 42 | static struct device *mpu_dev; |
53dfe8a8 | 43 | static struct regulator *mpu_reg; |
b8488fbe | 44 | |
9c0ebcf7 | 45 | static int omap_target(struct cpufreq_policy *policy, unsigned int index) |
ec6bced6 | 46 | { |
696d0b2c | 47 | int r, ret; |
47d43ba7 | 48 | struct dev_pm_opp *opp; |
42daffd2 | 49 | unsigned long freq, volt = 0, volt_old = 0, tol = 0; |
d4019f0a | 50 | unsigned int old_freq, new_freq; |
ec6bced6 | 51 | |
652ed95d | 52 | old_freq = policy->cur; |
d4019f0a | 53 | new_freq = freq_table[index].frequency; |
aeec2990 | 54 | |
d4019f0a | 55 | freq = new_freq * 1000; |
652ed95d | 56 | ret = clk_round_rate(policy->clk, freq); |
287980e4 | 57 | if (ret < 0) { |
8df0a663 KH |
58 | dev_warn(mpu_dev, |
59 | "CPUfreq: Cannot find matching frequency for %lu\n", | |
60 | freq); | |
61 | return ret; | |
62 | } | |
63 | freq = ret; | |
53dfe8a8 KH |
64 | |
65 | if (mpu_reg) { | |
f44d188a | 66 | rcu_read_lock(); |
5d4879cd | 67 | opp = dev_pm_opp_find_freq_ceil(mpu_dev, &freq); |
53dfe8a8 | 68 | if (IS_ERR(opp)) { |
f44d188a | 69 | rcu_read_unlock(); |
53dfe8a8 | 70 | dev_err(mpu_dev, "%s: unable to find MPU OPP for %d\n", |
d4019f0a | 71 | __func__, new_freq); |
53dfe8a8 KH |
72 | return -EINVAL; |
73 | } | |
5d4879cd | 74 | volt = dev_pm_opp_get_voltage(opp); |
f44d188a | 75 | rcu_read_unlock(); |
42daffd2 | 76 | tol = volt * OPP_TOLERANCE / 100; |
53dfe8a8 KH |
77 | volt_old = regulator_get_voltage(mpu_reg); |
78 | } | |
79 | ||
80 | dev_dbg(mpu_dev, "cpufreq-omap: %u MHz, %ld mV --> %u MHz, %ld mV\n", | |
d4019f0a VK |
81 | old_freq / 1000, volt_old ? volt_old / 1000 : -1, |
82 | new_freq / 1000, volt ? volt / 1000 : -1); | |
44a49a23 | 83 | |
53dfe8a8 | 84 | /* scaling up? scale voltage before frequency */ |
d4019f0a | 85 | if (mpu_reg && (new_freq > old_freq)) { |
42daffd2 | 86 | r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol); |
53dfe8a8 KH |
87 | if (r < 0) { |
88 | dev_warn(mpu_dev, "%s: unable to scale voltage up.\n", | |
89 | __func__); | |
d4019f0a | 90 | return r; |
53dfe8a8 KH |
91 | } |
92 | } | |
731e0cc6 | 93 | |
652ed95d | 94 | ret = clk_set_rate(policy->clk, new_freq * 1000); |
46c12216 | 95 | |
53dfe8a8 | 96 | /* scaling down? scale voltage after frequency */ |
d4019f0a | 97 | if (mpu_reg && (new_freq < old_freq)) { |
42daffd2 | 98 | r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol); |
53dfe8a8 KH |
99 | if (r < 0) { |
100 | dev_warn(mpu_dev, "%s: unable to scale voltage down.\n", | |
101 | __func__); | |
652ed95d | 102 | clk_set_rate(policy->clk, old_freq * 1000); |
d4019f0a | 103 | return r; |
53dfe8a8 KH |
104 | } |
105 | } | |
106 | ||
ec6bced6 TL |
107 | return ret; |
108 | } | |
109 | ||
1c78217f NM |
110 | static inline void freq_table_free(void) |
111 | { | |
112 | if (atomic_dec_and_test(&freq_table_users)) | |
5d4879cd | 113 | dev_pm_opp_free_cpufreq_table(mpu_dev, &freq_table); |
1c78217f NM |
114 | } |
115 | ||
2760984f | 116 | static int omap_cpu_init(struct cpufreq_policy *policy) |
ec6bced6 | 117 | { |
982bce11 | 118 | int result; |
731e0cc6 | 119 | |
652ed95d VK |
120 | policy->clk = clk_get(NULL, "cpufreq_ck"); |
121 | if (IS_ERR(policy->clk)) | |
122 | return PTR_ERR(policy->clk); | |
ec6bced6 | 123 | |
982bce11 | 124 | if (!freq_table) { |
5d4879cd | 125 | result = dev_pm_opp_init_cpufreq_table(mpu_dev, &freq_table); |
982bce11 VK |
126 | if (result) { |
127 | dev_err(mpu_dev, | |
128 | "%s: cpu%d: failed creating freq table[%d]\n", | |
bf2a359d | 129 | __func__, policy->cpu, result); |
982bce11 VK |
130 | goto fail; |
131 | } | |
aeec2990 KH |
132 | } |
133 | ||
1b865214 RN |
134 | atomic_inc_return(&freq_table_users); |
135 | ||
aeec2990 | 136 | /* FIXME: what's the actual transition time? */ |
982bce11 VK |
137 | result = cpufreq_generic_init(policy, freq_table, 300 * 1000); |
138 | if (!result) | |
139 | return 0; | |
11e04fdd | 140 | |
1c78217f | 141 | freq_table_free(); |
982bce11 | 142 | fail: |
652ed95d | 143 | clk_put(policy->clk); |
11e04fdd | 144 | return result; |
ec6bced6 TL |
145 | } |
146 | ||
b8488fbe HD |
147 | static int omap_cpu_exit(struct cpufreq_policy *policy) |
148 | { | |
1c78217f | 149 | freq_table_free(); |
652ed95d | 150 | clk_put(policy->clk); |
b8488fbe HD |
151 | return 0; |
152 | } | |
153 | ||
ec6bced6 | 154 | static struct cpufreq_driver omap_driver = { |
ae6b4271 | 155 | .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
d5ca1649 | 156 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 157 | .target_index = omap_target, |
652ed95d | 158 | .get = cpufreq_generic_get, |
ec6bced6 | 159 | .init = omap_cpu_init, |
b8488fbe | 160 | .exit = omap_cpu_exit, |
ec6bced6 | 161 | .name = "omap", |
d5ca1649 | 162 | .attr = cpufreq_generic_attr, |
ec6bced6 TL |
163 | }; |
164 | ||
49ded525 | 165 | static int omap_cpufreq_probe(struct platform_device *pdev) |
ec6bced6 | 166 | { |
747a7f64 KH |
167 | mpu_dev = get_cpu_device(0); |
168 | if (!mpu_dev) { | |
1c5864e2 | 169 | pr_warn("%s: unable to get the MPU device\n", __func__); |
747a7f64 | 170 | return -EINVAL; |
a820ffa8 NM |
171 | } |
172 | ||
53dfe8a8 KH |
173 | mpu_reg = regulator_get(mpu_dev, "vcc"); |
174 | if (IS_ERR(mpu_reg)) { | |
b49c22a6 | 175 | pr_warn("%s: unable to get MPU regulator\n", __func__); |
53dfe8a8 KH |
176 | mpu_reg = NULL; |
177 | } else { | |
178 | /* | |
179 | * Ensure physical regulator is present. | |
180 | * (e.g. could be dummy regulator.) | |
181 | */ | |
182 | if (regulator_get_voltage(mpu_reg) < 0) { | |
183 | pr_warn("%s: physical regulator not present for MPU\n", | |
184 | __func__); | |
185 | regulator_put(mpu_reg); | |
186 | mpu_reg = NULL; | |
187 | } | |
188 | } | |
189 | ||
ec6bced6 TL |
190 | return cpufreq_register_driver(&omap_driver); |
191 | } | |
192 | ||
49ded525 | 193 | static int omap_cpufreq_remove(struct platform_device *pdev) |
731e0cc6 | 194 | { |
49ded525 | 195 | return cpufreq_unregister_driver(&omap_driver); |
731e0cc6 | 196 | } |
aeec2990 | 197 | |
49ded525 NM |
198 | static struct platform_driver omap_cpufreq_platdrv = { |
199 | .driver = { | |
200 | .name = "omap-cpufreq", | |
49ded525 NM |
201 | }, |
202 | .probe = omap_cpufreq_probe, | |
203 | .remove = omap_cpufreq_remove, | |
204 | }; | |
205 | module_platform_driver(omap_cpufreq_platdrv); | |
206 | ||
731e0cc6 SS |
207 | MODULE_DESCRIPTION("cpufreq driver for OMAP SoCs"); |
208 | MODULE_LICENSE("GPL"); |