[deliverable/linux.git] / drivers / cpufreq / omap-cpufreq.c

/*
 *  CPU frequency scaling for OMAP using OPP information
 *
 *  Copyright (C) 2005 Nokia Corporation
 *  Written by Tony Lindgren <tony@atomide.com>
 *
 *  Based on cpu-sa1110.c, Copyright (C) 2001 Russell King
 *
 * Copyright (C) 2007-2011 Texas Instruments, Inc.
 * - OMAP3/4 support by Rajendra Nayak, Santosh Shilimkar
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/cpufreq.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/opp.h>
#include <linux/cpu.h>
#include <linux/module.h>
#include <linux/regulator/consumer.h>

#include <asm/smp_plat.h>
#include <asm/cpu.h>

#include <plat/clock.h>
#include <plat/common.h>
#include <plat/omap_device.h>

#include <mach/hardware.h>

/* OPP tolerance in percentage */
#define	OPP_TOLERANCE	4

static struct cpufreq_frequency_table *freq_table;
static atomic_t freq_table_users = ATOMIC_INIT(0);
static struct clk *mpu_clk;
static char *mpu_clk_name;
static struct device *mpu_dev;
static struct regulator *mpu_reg;

static int omap_verify_speed(struct cpufreq_policy *policy)
{
	if (!freq_table)
		return -EINVAL;
	return cpufreq_frequency_table_verify(policy, freq_table);
}

static unsigned int omap_getspeed(unsigned int cpu)
{
	unsigned long rate;

	if (cpu >= NR_CPUS)
		return 0;

	rate = clk_get_rate(mpu_clk) / 1000;
	return rate;
}

static int omap_target(struct cpufreq_policy *policy,
		       unsigned int target_freq,
		       unsigned int relation)
{
	unsigned int i;
	int r, ret = 0;
	struct cpufreq_freqs freqs;
	struct opp *opp;
	unsigned long freq, volt = 0, volt_old = 0, tol = 0;

	if (!freq_table) {
		dev_err(mpu_dev, "%s: cpu%d: no freq table!\n", __func__,
				policy->cpu);
		return -EINVAL;
	}

	ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
			relation, &i);
	if (ret) {
		dev_dbg(mpu_dev, "%s: cpu%d: no freq match for %d(ret=%d)\n",
			__func__, policy->cpu, target_freq, ret);
		return ret;
	}
	freqs.new = freq_table[i].frequency;
	if (!freqs.new) {
		dev_err(mpu_dev, "%s: cpu%d: no match for freq %d\n", __func__,
			policy->cpu, target_freq);
		return -EINVAL;
	}

	freqs.old = omap_getspeed(policy->cpu);
	freqs.cpu = policy->cpu;

	if (freqs.old == freqs.new && policy->cur == freqs.new)
		return ret;

	/* notifiers */
	for_each_cpu(i, policy->cpus) {
		freqs.cpu = i;
		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
	}

	freq = freqs.new * 1000;
	ret = clk_round_rate(mpu_clk, freq);
	if (IS_ERR_VALUE(ret)) {
		dev_warn(mpu_dev,
			 "CPUfreq: Cannot find matching frequency for %lu\n",
			 freq);
		return ret;
	}
	freq = ret;

	if (mpu_reg) {
		opp = opp_find_freq_ceil(mpu_dev, &freq);
		if (IS_ERR(opp)) {
			dev_err(mpu_dev, "%s: unable to find MPU OPP for %d\n",
				__func__, freqs.new);
			return -EINVAL;
		}
		volt = opp_get_voltage(opp);
		tol = volt * OPP_TOLERANCE / 100;
		volt_old = regulator_get_voltage(mpu_reg);
	}

	dev_dbg(mpu_dev, "cpufreq-omap: %u MHz, %ld mV --> %u MHz, %ld mV\n", 
		freqs.old / 1000, volt_old ? volt_old / 1000 : -1,
		freqs.new / 1000, volt ? volt / 1000 : -1);

	/* scaling up?  scale voltage before frequency */
	if (mpu_reg && (freqs.new > freqs.old)) {
		r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol);
		if (r < 0) {
			dev_warn(mpu_dev, "%s: unable to scale voltage up.\n",
				 __func__);
			freqs.new = freqs.old;
			goto done;
		}
	}

	ret = clk_set_rate(mpu_clk, freqs.new * 1000);

	/* scaling down?  scale voltage after frequency */
	if (mpu_reg && (freqs.new < freqs.old)) {
		r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol);
		if (r < 0) {
			dev_warn(mpu_dev, "%s: unable to scale voltage down.\n",
				 __func__);
			ret = clk_set_rate(mpu_clk, freqs.old * 1000);
			freqs.new = freqs.old;
			goto done;
		}
	}

	freqs.new = omap_getspeed(policy->cpu);

done:
	/* notifiers */
	for_each_cpu(i, policy->cpus) {
		freqs.cpu = i;
		cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
	}

	return ret;
}

static inline void freq_table_free(void)
{
	if (atomic_dec_and_test(&freq_table_users))
		opp_free_cpufreq_table(mpu_dev, &freq_table);
}

static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
{
	int result = 0;

	mpu_clk = clk_get(NULL, mpu_clk_name);
	if (IS_ERR(mpu_clk))
		return PTR_ERR(mpu_clk);

	if (policy->cpu >= NR_CPUS) {
		result = -EINVAL;
		goto fail_ck;
	}

	policy->cur = policy->min = policy->max = omap_getspeed(policy->cpu);

	if (!freq_table)
		result = opp_init_cpufreq_table(mpu_dev, &freq_table);

	if (result) {
		dev_err(mpu_dev, "%s: cpu%d: failed creating freq table[%d]\n",
				__func__, policy->cpu, result);
		goto fail_ck;
	}

	atomic_inc_return(&freq_table_users);

	result = cpufreq_frequency_table_cpuinfo(policy, freq_table);
	if (result)
		goto fail_table;

	cpufreq_frequency_table_get_attr(freq_table, policy->cpu);

	policy->min = policy->cpuinfo.min_freq;
	policy->max = policy->cpuinfo.max_freq;
	policy->cur = omap_getspeed(policy->cpu);

	/*
	 * On OMAP SMP configuartion, both processors share the voltage
	 * and clock. So both CPUs needs to be scaled together and hence
	 * needs software co-ordination. Use cpufreq affected_cpus
	 * interface to handle this scenario. Additional is_smp() check
	 * is to keep SMP_ON_UP build working.
	 */
	if (is_smp()) {
		policy->shared_type = CPUFREQ_SHARED_TYPE_ANY;
		cpumask_setall(policy->cpus);
	}

	/* FIXME: what's the actual transition time? */
	policy->cpuinfo.transition_latency = 300 * 1000;

	return 0;

fail_table:
	freq_table_free();
fail_ck:
	clk_put(mpu_clk);
	return result;
}

static int omap_cpu_exit(struct cpufreq_policy *policy)
{
	freq_table_free();
	clk_put(mpu_clk);
	return 0;
}

static struct freq_attr *omap_cpufreq_attr[] = {
	&cpufreq_freq_attr_scaling_available_freqs,
	NULL,
};

static struct cpufreq_driver omap_driver = {
	.flags		= CPUFREQ_STICKY,
	.verify		= omap_verify_speed,
	.target		= omap_target,
	.get		= omap_getspeed,
	.init		= omap_cpu_init,
	.exit		= omap_cpu_exit,
	.name		= "omap",
	.attr		= omap_cpufreq_attr,
};

static int __init omap_cpufreq_init(void)
{
	if (cpu_is_omap24xx())
		mpu_clk_name = "virt_prcm_set";
	else if (cpu_is_omap34xx())
		mpu_clk_name = "dpll1_ck";
	else if (cpu_is_omap44xx())
		mpu_clk_name = "dpll_mpu_ck";

	if (!mpu_clk_name) {
		pr_err("%s: unsupported Silicon?\n", __func__);
		return -EINVAL;
	}

	mpu_dev = omap_device_get_by_hwmod_name("mpu");
	if (IS_ERR(mpu_dev)) {
		pr_warning("%s: unable to get the mpu device\n", __func__);
		return PTR_ERR(mpu_dev);
	}

	mpu_reg = regulator_get(mpu_dev, "vcc");
	if (IS_ERR(mpu_reg)) {
		pr_warning("%s: unable to get MPU regulator\n", __func__);
		mpu_reg = NULL;
	} else {
		/* 
		 * Ensure physical regulator is present.
		 * (e.g. could be dummy regulator.)
		 */
		if (regulator_get_voltage(mpu_reg) < 0) {
			pr_warn("%s: physical regulator not present for MPU\n",
				__func__);
			regulator_put(mpu_reg);
			mpu_reg = NULL;
		}
	}

	return cpufreq_register_driver(&omap_driver);
}

static void __exit omap_cpufreq_exit(void)
{
	cpufreq_unregister_driver(&omap_driver);
}

MODULE_DESCRIPTION("cpufreq driver for OMAP SoCs");
MODULE_LICENSE("GPL");
module_init(omap_cpufreq_init);
module_exit(omap_cpufreq_exit);
Commit	Line	Data
ec6bced6	1	/*
ffe4f0f1	2	* CPU frequency scaling for OMAP using OPP information
ec6bced6 TL	3	*
	4	* Copyright (C) 2005 Nokia Corporation
	5	* Written by Tony Lindgren <tony@atomide.com>
	6	*
	7	* Based on cpu-sa1110.c, Copyright (C) 2001 Russell King
	8	*
731e0cc6 SS	9	* Copyright (C) 2007-2011 Texas Instruments, Inc.
	10	* - OMAP3/4 support by Rajendra Nayak, Santosh Shilimkar
	11	*
ec6bced6 TL	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*/
	16	#include <linux/types.h>
	17	#include <linux/kernel.h>
	18	#include <linux/sched.h>
	19	#include <linux/cpufreq.h>
	20	#include <linux/delay.h>
	21	#include <linux/init.h>
	22	#include <linux/err.h>
f8ce2547	23	#include <linux/clk.h>
fced80c7	24	#include <linux/io.h>
731e0cc6	25	#include <linux/opp.h>
46c12216	26	#include <linux/cpu.h>
c1b547bc	27	#include <linux/module.h>
53dfe8a8	28	#include <linux/regulator/consumer.h>
ec6bced6	29
731e0cc6	30	#include <asm/smp_plat.h>
46c12216	31	#include <asm/cpu.h>
ec6bced6	32
731e0cc6	33	#include <plat/clock.h>
731e0cc6	34	#include <plat/common.h>
c1b547bc	35	#include <plat/omap_device.h>
a7ca9d2b	36
731e0cc6	37	#include <mach/hardware.h>
aeec2990	38
42daffd2 AM	39	/* OPP tolerance in percentage */
	40	#define OPP_TOLERANCE 4
	41
731e0cc6	42	static struct cpufreq_frequency_table *freq_table;
1c78217f	43	static atomic_t freq_table_users = ATOMIC_INIT(0);
b8488fbe	44	static struct clk *mpu_clk;
08ca3e3b	45	static char *mpu_clk_name;
a820ffa8	46	static struct device *mpu_dev;
53dfe8a8	47	static struct regulator *mpu_reg;
b8488fbe	48
b0a330dc	49	static int omap_verify_speed(struct cpufreq_policy *policy)
ec6bced6	50	{
bf2a359d	51	if (!freq_table)
ec6bced6	52	return -EINVAL;
bf2a359d	53	return cpufreq_frequency_table_verify(policy, freq_table);
ec6bced6 TL	54	}
ec6bced6 TL	55
b0a330dc	56	static unsigned int omap_getspeed(unsigned int cpu)
ec6bced6	57	{
ec6bced6 TL	58	unsigned long rate;
ec6bced6 TL	59
46c12216	60	if (cpu >= NR_CPUS)
ec6bced6 TL	61	return 0;
ec6bced6 TL	62
ec6bced6	63	rate = clk_get_rate(mpu_clk) / 1000;
ec6bced6 TL	64	return rate;
	65	}
	66
	67	static int omap_target(struct cpufreq_policy *policy,
	68	unsigned int target_freq,
	69	unsigned int relation)
	70	{
bf2a359d	71	unsigned int i;
53dfe8a8	72	int r, ret = 0;
731e0cc6	73	struct cpufreq_freqs freqs;
53dfe8a8	74	struct opp *opp;
42daffd2	75	unsigned long freq, volt = 0, volt_old = 0, tol = 0;
ec6bced6	76
bf2a359d NM	77	if (!freq_table) {
	78	dev_err(mpu_dev, "%s: cpu%d: no freq table!\n", __func__,
	79	policy->cpu);
	80	return -EINVAL;
	81	}
	82
	83	ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
	84	relation, &i);
	85	if (ret) {
	86	dev_dbg(mpu_dev, "%s: cpu%d: no freq match for %d(ret=%d)\n",
	87	__func__, policy->cpu, target_freq, ret);
	88	return ret;
	89	}
	90	freqs.new = freq_table[i].frequency;
	91	if (!freqs.new) {
	92	dev_err(mpu_dev, "%s: cpu%d: no match for freq %d\n", __func__,
	93	policy->cpu, target_freq);
	94	return -EINVAL;
	95	}
aeec2990	96
46c12216	97	freqs.old = omap_getspeed(policy->cpu);
46c12216	98	freqs.cpu = policy->cpu;
ec6bced6	99
022ac03b	100	if (freqs.old == freqs.new && policy->cur == freqs.new)
aeec2990 KH	101	return ret;
aeec2990 KH	102
46c12216 RK	103	/* notifiers */
	104	for_each_cpu(i, policy->cpus) {
	105	freqs.cpu = i;
	106	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
	107	}
731e0cc6	108
53dfe8a8	109	freq = freqs.new * 1000;
8df0a663 KH	110	ret = clk_round_rate(mpu_clk, freq);
	111	if (IS_ERR_VALUE(ret)) {
	112	dev_warn(mpu_dev,
	113	"CPUfreq: Cannot find matching frequency for %lu\n",
	114	freq);
	115	return ret;
	116	}
	117	freq = ret;
53dfe8a8 KH	118
	119	if (mpu_reg) {
	120	opp = opp_find_freq_ceil(mpu_dev, &freq);
	121	if (IS_ERR(opp)) {
	122	dev_err(mpu_dev, "%s: unable to find MPU OPP for %d\n",
	123	__func__, freqs.new);
	124	return -EINVAL;
	125	}
	126	volt = opp_get_voltage(opp);
42daffd2	127	tol = volt * OPP_TOLERANCE / 100;
53dfe8a8 KH	128	volt_old = regulator_get_voltage(mpu_reg);
	129	}
	130
	131	dev_dbg(mpu_dev, "cpufreq-omap: %u MHz, %ld mV --> %u MHz, %ld mV\n",
	132	freqs.old / 1000, volt_old ? volt_old / 1000 : -1,
	133	freqs.new / 1000, volt ? volt / 1000 : -1);
	134
	135	/* scaling up? scale voltage before frequency */
	136	if (mpu_reg && (freqs.new > freqs.old)) {
42daffd2	137	r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol);
53dfe8a8 KH	138	if (r < 0) {
	139	dev_warn(mpu_dev, "%s: unable to scale voltage up.\n",
	140	__func__);
	141	freqs.new = freqs.old;
	142	goto done;
	143	}
	144	}
731e0cc6	145
aeec2990	146	ret = clk_set_rate(mpu_clk, freqs.new * 1000);
46c12216	147
53dfe8a8 KH	148	/* scaling down? scale voltage after frequency */
53dfe8a8 KH	149	if (mpu_reg && (freqs.new < freqs.old)) {
42daffd2	150	r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol);
53dfe8a8 KH	151	if (r < 0) {
	152	dev_warn(mpu_dev, "%s: unable to scale voltage down.\n",
	153	__func__);
	154	ret = clk_set_rate(mpu_clk, freqs.old * 1000);
	155	freqs.new = freqs.old;
	156	goto done;
	157	}
	158	}
	159
	160	freqs.new = omap_getspeed(policy->cpu);
46c12216	161
53dfe8a8	162	done:
46c12216 RK	163	/* notifiers */
	164	for_each_cpu(i, policy->cpus) {
	165	freqs.cpu = i;
	166	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
	167	}
ec6bced6 TL	168
	169	return ret;
	170	}
	171
1c78217f NM	172	static inline void freq_table_free(void)
	173	{
	174	if (atomic_dec_and_test(&freq_table_users))
	175	opp_free_cpufreq_table(mpu_dev, &freq_table);
	176	}
	177
790ab7e9	178	static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
ec6bced6	179	{
aeec2990	180	int result = 0;
731e0cc6	181
08ca3e3b	182	mpu_clk = clk_get(NULL, mpu_clk_name);
ec6bced6 TL	183	if (IS_ERR(mpu_clk))
	184	return PTR_ERR(mpu_clk);
	185
11e04fdd NM	186	if (policy->cpu >= NR_CPUS) {
	187	result = -EINVAL;
	188	goto fail_ck;
	189	}
aeec2990	190
46c12216	191	policy->cur = policy->min = policy->max = omap_getspeed(policy->cpu);
1c78217f	192
1b865214	193	if (!freq_table)
1c78217f	194	result = opp_init_cpufreq_table(mpu_dev, &freq_table);
bf2a359d NM	195
	196	if (result) {
	197	dev_err(mpu_dev, "%s: cpu%d: failed creating freq table[%d]\n",
	198	__func__, policy->cpu, result);
11e04fdd	199	goto fail_ck;
aeec2990 KH	200	}
aeec2990 KH	201
1b865214 RN	202	atomic_inc_return(&freq_table_users);
1b865214 RN	203
bf2a359d	204	result = cpufreq_frequency_table_cpuinfo(policy, freq_table);
1c78217f NM	205	if (result)
	206	goto fail_table;
	207
	208	cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
bf2a359d	209
731e0cc6 SS	210	policy->min = policy->cpuinfo.min_freq;
731e0cc6 SS	211	policy->max = policy->cpuinfo.max_freq;
46c12216 RK	212	policy->cur = omap_getspeed(policy->cpu);
	213
	214	/*
	215	* On OMAP SMP configuartion, both processors share the voltage
	216	* and clock. So both CPUs needs to be scaled together and hence
	217	* needs software co-ordination. Use cpufreq affected_cpus
	218	* interface to handle this scenario. Additional is_smp() check
	219	* is to keep SMP_ON_UP build working.
	220	*/
	221	if (is_smp()) {
	222	policy->shared_type = CPUFREQ_SHARED_TYPE_ANY;
ed8ce00c	223	cpumask_setall(policy->cpus);
46c12216	224	}
731e0cc6	225
aeec2990	226	/* FIXME: what's the actual transition time? */
b029839c	227	policy->cpuinfo.transition_latency = 300 * 1000;
ec6bced6 TL	228
ec6bced6 TL	229	return 0;
11e04fdd	230
1c78217f NM	231	fail_table:
1c78217f NM	232	freq_table_free();
11e04fdd NM	233	fail_ck:
	234	clk_put(mpu_clk);
	235	return result;
ec6bced6 TL	236	}
ec6bced6 TL	237
b8488fbe HD	238	static int omap_cpu_exit(struct cpufreq_policy *policy)
b8488fbe HD	239	{
1c78217f	240	freq_table_free();
b8488fbe HD	241	clk_put(mpu_clk);
	242	return 0;
	243	}
	244
aeec2990 KH	245	static struct freq_attr *omap_cpufreq_attr[] = {
	246	&cpufreq_freq_attr_scaling_available_freqs,
	247	NULL,
	248	};
	249
ec6bced6 TL	250	static struct cpufreq_driver omap_driver = {
	251	.flags = CPUFREQ_STICKY,
	252	.verify = omap_verify_speed,
	253	.target = omap_target,
	254	.get = omap_getspeed,
	255	.init = omap_cpu_init,
b8488fbe	256	.exit = omap_cpu_exit,
ec6bced6	257	.name = "omap",
aeec2990	258	.attr = omap_cpufreq_attr,
ec6bced6 TL	259	};
	260
	261	static int __init omap_cpufreq_init(void)
	262	{
08ca3e3b NM	263	if (cpu_is_omap24xx())
	264	mpu_clk_name = "virt_prcm_set";
	265	else if (cpu_is_omap34xx())
	266	mpu_clk_name = "dpll1_ck";
	267	else if (cpu_is_omap44xx())
	268	mpu_clk_name = "dpll_mpu_ck";
	269
	270	if (!mpu_clk_name) {
	271	pr_err("%s: unsupported Silicon?\n", __func__);
	272	return -EINVAL;
	273	}
a820ffa8	274
c1b547bc	275	mpu_dev = omap_device_get_by_hwmod_name("mpu");
1bae9958	276	if (IS_ERR(mpu_dev)) {
a820ffa8	277	pr_warning("%s: unable to get the mpu device\n", __func__);
1bae9958	278	return PTR_ERR(mpu_dev);
a820ffa8 NM	279	}
a820ffa8 NM	280
53dfe8a8 KH	281	mpu_reg = regulator_get(mpu_dev, "vcc");
	282	if (IS_ERR(mpu_reg)) {
	283	pr_warning("%s: unable to get MPU regulator\n", __func__);
	284	mpu_reg = NULL;
	285	} else {
	286	/*
	287	* Ensure physical regulator is present.
	288	* (e.g. could be dummy regulator.)
	289	*/
	290	if (regulator_get_voltage(mpu_reg) < 0) {
	291	pr_warn("%s: physical regulator not present for MPU\n",
	292	__func__);
	293	regulator_put(mpu_reg);
	294	mpu_reg = NULL;
	295	}
	296	}
	297
ec6bced6 TL	298	return cpufreq_register_driver(&omap_driver);
	299	}
	300
731e0cc6 SS	301	static void __exit omap_cpufreq_exit(void)
	302	{
	303	cpufreq_unregister_driver(&omap_driver);
	304	}
aeec2990	305
731e0cc6 SS	306	MODULE_DESCRIPTION("cpufreq driver for OMAP SoCs");
	307	MODULE_LICENSE("GPL");
	308	module_init(omap_cpufreq_init);
	309	module_exit(omap_cpufreq_exit);