Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
[deliverable/linux.git] / drivers / cpufreq / powernv-cpufreq.c
CommitLineData
b3d627a5
VS
1/*
2 * POWERNV cpufreq driver for the IBM POWER processors
3 *
4 * (C) Copyright IBM 2014
5 *
6 * Author: Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20#define pr_fmt(fmt) "powernv-cpufreq: " fmt
21
22#include <linux/kernel.h>
23#include <linux/sysfs.h>
24#include <linux/cpumask.h>
25#include <linux/module.h>
26#include <linux/cpufreq.h>
27#include <linux/smp.h>
28#include <linux/of.h>
cf30af76 29#include <linux/reboot.h>
053819e0 30#include <linux/slab.h>
6d167a44 31#include <linux/cpu.h>
c89f2682 32#include <trace/events/power.h>
b3d627a5
VS
33
34#include <asm/cputhreads.h>
6174bac8 35#include <asm/firmware.h>
b3d627a5 36#include <asm/reg.h>
f3cae355 37#include <asm/smp.h> /* Required for cpu_sibling_mask() in UP configs */
cb166fa9 38#include <asm/opal.h>
eaa2c3ae 39#include <linux/timer.h>
b3d627a5
VS
40
41#define POWERNV_MAX_PSTATES 256
09a972d1
SB
42#define PMSR_PSAFE_ENABLE (1UL << 30)
43#define PMSR_SPR_EM_DISABLE (1UL << 31)
44#define PMSR_MAX(x) ((x >> 32) & 0xFF)
b3d627a5 45
eaa2c3ae
AA
46#define MAX_RAMP_DOWN_TIME 5120
47/*
48 * On an idle system we want the global pstate to ramp-down from max value to
49 * min over a span of ~5 secs. Also we want it to initially ramp-down slowly and
50 * then ramp-down rapidly later on.
51 *
52 * This gives a percentage rampdown for time elapsed in milliseconds.
53 * ramp_down_percentage = ((ms * ms) >> 18)
54 * ~= 3.8 * (sec * sec)
55 *
56 * At 0 ms ramp_down_percent = 0
57 * At 5120 ms ramp_down_percent = 100
58 */
59#define ramp_down_percent(time) ((time * time) >> 18)
60
61/* Interval after which the timer is queued to bring down global pstate */
62#define GPSTATE_TIMER_INTERVAL 2000
63
64/**
65 * struct global_pstate_info - Per policy data structure to maintain history of
66 * global pstates
09ca4c9b
AA
67 * @highest_lpstate_idx: The local pstate index from which we are
68 * ramping down
eaa2c3ae 69 * @elapsed_time: Time in ms spent in ramping down from
09ca4c9b 70 * highest_lpstate_idx
eaa2c3ae
AA
71 * @last_sampled_time: Time from boot in ms when global pstates were
72 * last set
09ca4c9b
AA
73 * @last_lpstate_idx, Last set value of local pstate and global
74 * last_gpstate_idx pstate in terms of cpufreq table index
eaa2c3ae
AA
75 * @timer: Is used for ramping down if cpu goes idle for
76 * a long time with global pstate held high
77 * @gpstate_lock: A spinlock to maintain synchronization between
78 * routines called by the timer handler and
79 * governer's target_index calls
80 */
81struct global_pstate_info {
09ca4c9b 82 int highest_lpstate_idx;
eaa2c3ae
AA
83 unsigned int elapsed_time;
84 unsigned int last_sampled_time;
09ca4c9b
AA
85 int last_lpstate_idx;
86 int last_gpstate_idx;
eaa2c3ae
AA
87 spinlock_t gpstate_lock;
88 struct timer_list timer;
89};
90
b3d627a5 91static struct cpufreq_frequency_table powernv_freqs[POWERNV_MAX_PSTATES+1];
cb166fa9 92static bool rebooting, throttled, occ_reset;
b3d627a5 93
c89f2682
SB
94static const char * const throttle_reason[] = {
95 "No throttling",
96 "Power Cap",
97 "Processor Over Temperature",
98 "Power Supply Failure",
99 "Over Current",
100 "OCC Reset"
101};
102
1b028984
SB
103enum throttle_reason_type {
104 NO_THROTTLE = 0,
105 POWERCAP,
106 CPU_OVERTEMP,
107 POWER_SUPPLY_FAILURE,
108 OVERCURRENT,
109 OCC_RESET_THROTTLE,
110 OCC_MAX_REASON
111};
112
053819e0
SB
113static struct chip {
114 unsigned int id;
115 bool throttled;
c89f2682
SB
116 bool restore;
117 u8 throttle_reason;
735366fc
SB
118 cpumask_t mask;
119 struct work_struct throttle;
1b028984
SB
120 int throttle_turbo;
121 int throttle_sub_turbo;
122 int reason[OCC_MAX_REASON];
053819e0
SB
123} *chips;
124
125static int nr_chips;
3e5963bc 126static DEFINE_PER_CPU(struct chip *, chip_info);
053819e0 127
b3d627a5 128/*
09ca4c9b
AA
129 * Note:
130 * The set of pstates consists of contiguous integers.
131 * powernv_pstate_info stores the index of the frequency table for
132 * max, min and nominal frequencies. It also stores number of
133 * available frequencies.
b3d627a5 134 *
09ca4c9b
AA
135 * powernv_pstate_info.nominal indicates the index to the highest
136 * non-turbo frequency.
b3d627a5
VS
137 */
138static struct powernv_pstate_info {
09ca4c9b
AA
139 unsigned int min;
140 unsigned int max;
141 unsigned int nominal;
142 unsigned int nr_pstates;
b3d627a5
VS
143} powernv_pstate_info;
144
09ca4c9b
AA
145/* Use following macros for conversions between pstate_id and index */
146static inline int idx_to_pstate(unsigned int i)
147{
148 return powernv_freqs[i].driver_data;
149}
150
151static inline unsigned int pstate_to_idx(int pstate)
152{
153 /*
154 * abs() is deliberately used so that is works with
155 * both monotonically increasing and decreasing
156 * pstate values
157 */
158 return abs(pstate - idx_to_pstate(powernv_pstate_info.max));
159}
160
eaa2c3ae
AA
161static inline void reset_gpstates(struct cpufreq_policy *policy)
162{
163 struct global_pstate_info *gpstates = policy->driver_data;
164
09ca4c9b 165 gpstates->highest_lpstate_idx = 0;
eaa2c3ae
AA
166 gpstates->elapsed_time = 0;
167 gpstates->last_sampled_time = 0;
09ca4c9b
AA
168 gpstates->last_lpstate_idx = 0;
169 gpstates->last_gpstate_idx = 0;
eaa2c3ae
AA
170}
171
b3d627a5
VS
172/*
173 * Initialize the freq table based on data obtained
174 * from the firmware passed via device-tree
175 */
176static int init_powernv_pstates(void)
177{
178 struct device_node *power_mgt;
09ca4c9b 179 int i, nr_pstates = 0;
b3d627a5
VS
180 const __be32 *pstate_ids, *pstate_freqs;
181 u32 len_ids, len_freqs;
09ca4c9b 182 u32 pstate_min, pstate_max, pstate_nominal;
b3d627a5
VS
183
184 power_mgt = of_find_node_by_path("/ibm,opal/power-mgt");
185 if (!power_mgt) {
186 pr_warn("power-mgt node not found\n");
187 return -ENODEV;
188 }
189
190 if (of_property_read_u32(power_mgt, "ibm,pstate-min", &pstate_min)) {
191 pr_warn("ibm,pstate-min node not found\n");
192 return -ENODEV;
193 }
194
195 if (of_property_read_u32(power_mgt, "ibm,pstate-max", &pstate_max)) {
196 pr_warn("ibm,pstate-max node not found\n");
197 return -ENODEV;
198 }
199
200 if (of_property_read_u32(power_mgt, "ibm,pstate-nominal",
201 &pstate_nominal)) {
202 pr_warn("ibm,pstate-nominal not found\n");
203 return -ENODEV;
204 }
205 pr_info("cpufreq pstate min %d nominal %d max %d\n", pstate_min,
206 pstate_nominal, pstate_max);
207
208 pstate_ids = of_get_property(power_mgt, "ibm,pstate-ids", &len_ids);
209 if (!pstate_ids) {
210 pr_warn("ibm,pstate-ids not found\n");
211 return -ENODEV;
212 }
213
214 pstate_freqs = of_get_property(power_mgt, "ibm,pstate-frequencies-mhz",
215 &len_freqs);
216 if (!pstate_freqs) {
217 pr_warn("ibm,pstate-frequencies-mhz not found\n");
218 return -ENODEV;
219 }
220
6174bac8
VS
221 if (len_ids != len_freqs) {
222 pr_warn("Entries in ibm,pstate-ids and "
223 "ibm,pstate-frequencies-mhz does not match\n");
224 }
225
b3d627a5
VS
226 nr_pstates = min(len_ids, len_freqs) / sizeof(u32);
227 if (!nr_pstates) {
228 pr_warn("No PStates found\n");
229 return -ENODEV;
230 }
231
09ca4c9b 232 powernv_pstate_info.nr_pstates = nr_pstates;
b3d627a5
VS
233 pr_debug("NR PStates %d\n", nr_pstates);
234 for (i = 0; i < nr_pstates; i++) {
235 u32 id = be32_to_cpu(pstate_ids[i]);
236 u32 freq = be32_to_cpu(pstate_freqs[i]);
237
238 pr_debug("PState id %d freq %d MHz\n", id, freq);
239 powernv_freqs[i].frequency = freq * 1000; /* kHz */
0692c691 240 powernv_freqs[i].driver_data = id;
09ca4c9b
AA
241
242 if (id == pstate_max)
243 powernv_pstate_info.max = i;
244 else if (id == pstate_nominal)
245 powernv_pstate_info.nominal = i;
246 else if (id == pstate_min)
247 powernv_pstate_info.min = i;
b3d627a5 248 }
09ca4c9b 249
b3d627a5
VS
250 /* End of list marker entry */
251 powernv_freqs[i].frequency = CPUFREQ_TABLE_END;
b3d627a5
VS
252 return 0;
253}
254
255/* Returns the CPU frequency corresponding to the pstate_id. */
256static unsigned int pstate_id_to_freq(int pstate_id)
257{
258 int i;
259
09ca4c9b 260 i = pstate_to_idx(pstate_id);
6174bac8
VS
261 if (i >= powernv_pstate_info.nr_pstates || i < 0) {
262 pr_warn("PState id %d outside of PState table, "
263 "reporting nominal id %d instead\n",
09ca4c9b
AA
264 pstate_id, idx_to_pstate(powernv_pstate_info.nominal));
265 i = powernv_pstate_info.nominal;
6174bac8 266 }
b3d627a5
VS
267
268 return powernv_freqs[i].frequency;
269}
270
271/*
272 * cpuinfo_nominal_freq_show - Show the nominal CPU frequency as indicated by
273 * the firmware
274 */
275static ssize_t cpuinfo_nominal_freq_show(struct cpufreq_policy *policy,
276 char *buf)
277{
278 return sprintf(buf, "%u\n",
09ca4c9b 279 powernv_freqs[powernv_pstate_info.nominal].frequency);
b3d627a5
VS
280}
281
282struct freq_attr cpufreq_freq_attr_cpuinfo_nominal_freq =
283 __ATTR_RO(cpuinfo_nominal_freq);
284
285static struct freq_attr *powernv_cpu_freq_attr[] = {
286 &cpufreq_freq_attr_scaling_available_freqs,
287 &cpufreq_freq_attr_cpuinfo_nominal_freq,
288 NULL,
289};
290
1b028984
SB
291#define throttle_attr(name, member) \
292static ssize_t name##_show(struct cpufreq_policy *policy, char *buf) \
293{ \
294 struct chip *chip = per_cpu(chip_info, policy->cpu); \
295 \
296 return sprintf(buf, "%u\n", chip->member); \
297} \
298 \
299static struct freq_attr throttle_attr_##name = __ATTR_RO(name) \
300
301throttle_attr(unthrottle, reason[NO_THROTTLE]);
302throttle_attr(powercap, reason[POWERCAP]);
303throttle_attr(overtemp, reason[CPU_OVERTEMP]);
304throttle_attr(supply_fault, reason[POWER_SUPPLY_FAILURE]);
305throttle_attr(overcurrent, reason[OVERCURRENT]);
306throttle_attr(occ_reset, reason[OCC_RESET_THROTTLE]);
307throttle_attr(turbo_stat, throttle_turbo);
308throttle_attr(sub_turbo_stat, throttle_sub_turbo);
309
310static struct attribute *throttle_attrs[] = {
311 &throttle_attr_unthrottle.attr,
312 &throttle_attr_powercap.attr,
313 &throttle_attr_overtemp.attr,
314 &throttle_attr_supply_fault.attr,
315 &throttle_attr_overcurrent.attr,
316 &throttle_attr_occ_reset.attr,
317 &throttle_attr_turbo_stat.attr,
318 &throttle_attr_sub_turbo_stat.attr,
319 NULL,
320};
321
322static const struct attribute_group throttle_attr_grp = {
323 .name = "throttle_stats",
324 .attrs = throttle_attrs,
325};
326
b3d627a5
VS
327/* Helper routines */
328
329/* Access helpers to power mgt SPR */
330
331static inline unsigned long get_pmspr(unsigned long sprn)
332{
333 switch (sprn) {
334 case SPRN_PMCR:
335 return mfspr(SPRN_PMCR);
336
337 case SPRN_PMICR:
338 return mfspr(SPRN_PMICR);
339
340 case SPRN_PMSR:
341 return mfspr(SPRN_PMSR);
342 }
343 BUG();
344}
345
346static inline void set_pmspr(unsigned long sprn, unsigned long val)
347{
348 switch (sprn) {
349 case SPRN_PMCR:
350 mtspr(SPRN_PMCR, val);
351 return;
352
353 case SPRN_PMICR:
354 mtspr(SPRN_PMICR, val);
355 return;
356 }
357 BUG();
358}
359
360/*
361 * Use objects of this type to query/update
362 * pstates on a remote CPU via smp_call_function.
363 */
364struct powernv_smp_call_data {
365 unsigned int freq;
366 int pstate_id;
eaa2c3ae 367 int gpstate_id;
b3d627a5
VS
368};
369
370/*
371 * powernv_read_cpu_freq: Reads the current frequency on this CPU.
372 *
373 * Called via smp_call_function.
374 *
375 * Note: The caller of the smp_call_function should pass an argument of
376 * the type 'struct powernv_smp_call_data *' along with this function.
377 *
378 * The current frequency on this CPU will be returned via
379 * ((struct powernv_smp_call_data *)arg)->freq;
380 */
381static void powernv_read_cpu_freq(void *arg)
382{
383 unsigned long pmspr_val;
384 s8 local_pstate_id;
385 struct powernv_smp_call_data *freq_data = arg;
386
387 pmspr_val = get_pmspr(SPRN_PMSR);
388
389 /*
390 * The local pstate id corresponds bits 48..55 in the PMSR.
391 * Note: Watch out for the sign!
392 */
393 local_pstate_id = (pmspr_val >> 48) & 0xFF;
394 freq_data->pstate_id = local_pstate_id;
395 freq_data->freq = pstate_id_to_freq(freq_data->pstate_id);
396
397 pr_debug("cpu %d pmsr %016lX pstate_id %d frequency %d kHz\n",
398 raw_smp_processor_id(), pmspr_val, freq_data->pstate_id,
399 freq_data->freq);
400}
401
402/*
403 * powernv_cpufreq_get: Returns the CPU frequency as reported by the
404 * firmware for CPU 'cpu'. This value is reported through the sysfs
405 * file cpuinfo_cur_freq.
406 */
60d1ea4e 407static unsigned int powernv_cpufreq_get(unsigned int cpu)
b3d627a5
VS
408{
409 struct powernv_smp_call_data freq_data;
410
411 smp_call_function_any(cpu_sibling_mask(cpu), powernv_read_cpu_freq,
412 &freq_data, 1);
413
414 return freq_data.freq;
415}
416
417/*
418 * set_pstate: Sets the pstate on this CPU.
419 *
420 * This is called via an smp_call_function.
421 *
422 * The caller must ensure that freq_data is of the type
423 * (struct powernv_smp_call_data *) and the pstate_id which needs to be set
424 * on this CPU should be present in freq_data->pstate_id.
425 */
eaa2c3ae 426static void set_pstate(void *data)
b3d627a5
VS
427{
428 unsigned long val;
eaa2c3ae
AA
429 struct powernv_smp_call_data *freq_data = data;
430 unsigned long pstate_ul = freq_data->pstate_id;
431 unsigned long gpstate_ul = freq_data->gpstate_id;
b3d627a5
VS
432
433 val = get_pmspr(SPRN_PMCR);
434 val = val & 0x0000FFFFFFFFFFFFULL;
435
436 pstate_ul = pstate_ul & 0xFF;
eaa2c3ae 437 gpstate_ul = gpstate_ul & 0xFF;
b3d627a5
VS
438
439 /* Set both global(bits 56..63) and local(bits 48..55) PStates */
eaa2c3ae 440 val = val | (gpstate_ul << 56) | (pstate_ul << 48);
b3d627a5
VS
441
442 pr_debug("Setting cpu %d pmcr to %016lX\n",
443 raw_smp_processor_id(), val);
444 set_pmspr(SPRN_PMCR, val);
445}
446
cf30af76
SB
447/*
448 * get_nominal_index: Returns the index corresponding to the nominal
449 * pstate in the cpufreq table
450 */
451static inline unsigned int get_nominal_index(void)
452{
09ca4c9b 453 return powernv_pstate_info.nominal;
cf30af76
SB
454}
455
735366fc 456static void powernv_cpufreq_throttle_check(void *data)
09a972d1 457{
3e5963bc 458 struct chip *chip;
735366fc 459 unsigned int cpu = smp_processor_id();
09a972d1 460 unsigned long pmsr;
3e5963bc 461 int pmsr_pmax;
09ca4c9b 462 unsigned int pmsr_pmax_idx;
09a972d1
SB
463
464 pmsr = get_pmspr(SPRN_PMSR);
3e5963bc 465 chip = this_cpu_read(chip_info);
053819e0 466
09a972d1
SB
467 /* Check for Pmax Capping */
468 pmsr_pmax = (s8)PMSR_MAX(pmsr);
09ca4c9b
AA
469 pmsr_pmax_idx = pstate_to_idx(pmsr_pmax);
470 if (pmsr_pmax_idx != powernv_pstate_info.max) {
3e5963bc 471 if (chip->throttled)
053819e0 472 goto next;
3e5963bc 473 chip->throttled = true;
09ca4c9b
AA
474 if (pmsr_pmax_idx > powernv_pstate_info.nominal) {
475 pr_warn_once("CPU %d on Chip %u has Pmax(%d) reduced below nominal frequency(%d)\n",
3e5963bc 476 cpu, chip->id, pmsr_pmax,
09ca4c9b 477 idx_to_pstate(powernv_pstate_info.nominal));
1b028984
SB
478 chip->throttle_sub_turbo++;
479 } else {
480 chip->throttle_turbo++;
481 }
3e5963bc
MN
482 trace_powernv_throttle(chip->id,
483 throttle_reason[chip->throttle_reason],
c89f2682 484 pmsr_pmax);
3e5963bc
MN
485 } else if (chip->throttled) {
486 chip->throttled = false;
487 trace_powernv_throttle(chip->id,
488 throttle_reason[chip->throttle_reason],
c89f2682 489 pmsr_pmax);
09a972d1
SB
490 }
491
3dd3ebe5 492 /* Check if Psafe_mode_active is set in PMSR. */
053819e0 493next:
3dd3ebe5 494 if (pmsr & PMSR_PSAFE_ENABLE) {
09a972d1
SB
495 throttled = true;
496 pr_info("Pstate set to safe frequency\n");
497 }
498
499 /* Check if SPR_EM_DISABLE is set in PMSR */
500 if (pmsr & PMSR_SPR_EM_DISABLE) {
501 throttled = true;
502 pr_info("Frequency Control disabled from OS\n");
503 }
504
505 if (throttled) {
506 pr_info("PMSR = %16lx\n", pmsr);
c89f2682 507 pr_warn("CPU Frequency could be throttled\n");
09a972d1
SB
508 }
509}
510
eaa2c3ae
AA
511/**
512 * calc_global_pstate - Calculate global pstate
09ca4c9b
AA
513 * @elapsed_time: Elapsed time in milliseconds
514 * @local_pstate_idx: New local pstate
515 * @highest_lpstate_idx: pstate from which its ramping down
eaa2c3ae
AA
516 *
517 * Finds the appropriate global pstate based on the pstate from which its
518 * ramping down and the time elapsed in ramping down. It follows a quadratic
519 * equation which ensures that it reaches ramping down to pmin in 5sec.
520 */
521static inline int calc_global_pstate(unsigned int elapsed_time,
09ca4c9b
AA
522 int highest_lpstate_idx,
523 int local_pstate_idx)
eaa2c3ae 524{
09ca4c9b 525 int index_diff;
eaa2c3ae
AA
526
527 /*
528 * Using ramp_down_percent we get the percentage of rampdown
529 * that we are expecting to be dropping. Difference between
09ca4c9b 530 * highest_lpstate_idx and powernv_pstate_info.min will give a absolute
eaa2c3ae
AA
531 * number of how many pstates we will drop eventually by the end of
532 * 5 seconds, then just scale it get the number pstates to be dropped.
533 */
09ca4c9b
AA
534 index_diff = ((int)ramp_down_percent(elapsed_time) *
535 (powernv_pstate_info.min - highest_lpstate_idx)) / 100;
eaa2c3ae
AA
536
537 /* Ensure that global pstate is >= to local pstate */
09ca4c9b
AA
538 if (highest_lpstate_idx + index_diff >= local_pstate_idx)
539 return local_pstate_idx;
eaa2c3ae 540 else
09ca4c9b 541 return highest_lpstate_idx + index_diff;
eaa2c3ae
AA
542}
543
544static inline void queue_gpstate_timer(struct global_pstate_info *gpstates)
545{
546 unsigned int timer_interval;
547
548 /*
549 * Setting up timer to fire after GPSTATE_TIMER_INTERVAL ms, But
550 * if it exceeds MAX_RAMP_DOWN_TIME ms for ramp down time.
551 * Set timer such that it fires exactly at MAX_RAMP_DOWN_TIME
552 * seconds of ramp down time.
553 */
554 if ((gpstates->elapsed_time + GPSTATE_TIMER_INTERVAL)
555 > MAX_RAMP_DOWN_TIME)
556 timer_interval = MAX_RAMP_DOWN_TIME - gpstates->elapsed_time;
557 else
558 timer_interval = GPSTATE_TIMER_INTERVAL;
559
7bc54b65 560 mod_timer(&gpstates->timer, jiffies + msecs_to_jiffies(timer_interval));
eaa2c3ae
AA
561}
562
563/**
564 * gpstate_timer_handler
565 *
566 * @data: pointer to cpufreq_policy on which timer was queued
567 *
568 * This handler brings down the global pstate closer to the local pstate
569 * according quadratic equation. Queues a new timer if it is still not equal
570 * to local pstate
571 */
572void gpstate_timer_handler(unsigned long data)
573{
574 struct cpufreq_policy *policy = (struct cpufreq_policy *)data;
575 struct global_pstate_info *gpstates = policy->driver_data;
09ca4c9b 576 int gpstate_idx;
eaa2c3ae
AA
577 unsigned int time_diff = jiffies_to_msecs(jiffies)
578 - gpstates->last_sampled_time;
579 struct powernv_smp_call_data freq_data;
580
581 if (!spin_trylock(&gpstates->gpstate_lock))
582 return;
583
584 gpstates->last_sampled_time += time_diff;
585 gpstates->elapsed_time += time_diff;
09ca4c9b 586 freq_data.pstate_id = idx_to_pstate(gpstates->last_lpstate_idx);
eaa2c3ae 587
09ca4c9b 588 if ((gpstates->last_gpstate_idx == gpstates->last_lpstate_idx) ||
eaa2c3ae 589 (gpstates->elapsed_time > MAX_RAMP_DOWN_TIME)) {
09ca4c9b 590 gpstate_idx = pstate_to_idx(freq_data.pstate_id);
eaa2c3ae 591 reset_gpstates(policy);
09ca4c9b 592 gpstates->highest_lpstate_idx = gpstate_idx;
eaa2c3ae 593 } else {
09ca4c9b
AA
594 gpstate_idx = calc_global_pstate(gpstates->elapsed_time,
595 gpstates->highest_lpstate_idx,
596 freq_data.pstate_id);
eaa2c3ae
AA
597 }
598
599 /*
600 * If local pstate is equal to global pstate, rampdown is over
601 * So timer is not required to be queued.
602 */
09ca4c9b 603 if (gpstate_idx != gpstates->last_lpstate_idx)
eaa2c3ae
AA
604 queue_gpstate_timer(gpstates);
605
09ca4c9b
AA
606 freq_data.gpstate_id = idx_to_pstate(gpstate_idx);
607 gpstates->last_gpstate_idx = pstate_to_idx(freq_data.gpstate_id);
608 gpstates->last_lpstate_idx = pstate_to_idx(freq_data.pstate_id);
eaa2c3ae 609
1fd3ff28
AA
610 spin_unlock(&gpstates->gpstate_lock);
611
eaa2c3ae
AA
612 /* Timer may get migrated to a different cpu on cpu hot unplug */
613 smp_call_function_any(policy->cpus, set_pstate, &freq_data, 1);
eaa2c3ae
AA
614}
615
b3d627a5
VS
616/*
617 * powernv_cpufreq_target_index: Sets the frequency corresponding to
618 * the cpufreq table entry indexed by new_index on the cpus in the
619 * mask policy->cpus
620 */
621static int powernv_cpufreq_target_index(struct cpufreq_policy *policy,
622 unsigned int new_index)
623{
624 struct powernv_smp_call_data freq_data;
09ca4c9b 625 unsigned int cur_msec, gpstate_idx;
eaa2c3ae 626 struct global_pstate_info *gpstates = policy->driver_data;
b3d627a5 627
cf30af76
SB
628 if (unlikely(rebooting) && new_index != get_nominal_index())
629 return 0;
630
09a972d1 631 if (!throttled)
735366fc 632 powernv_cpufreq_throttle_check(NULL);
09a972d1 633
eaa2c3ae
AA
634 cur_msec = jiffies_to_msecs(get_jiffies_64());
635
1fd3ff28 636 spin_lock(&gpstates->gpstate_lock);
09ca4c9b 637 freq_data.pstate_id = idx_to_pstate(new_index);
b3d627a5 638
eaa2c3ae 639 if (!gpstates->last_sampled_time) {
09ca4c9b
AA
640 gpstate_idx = new_index;
641 gpstates->highest_lpstate_idx = new_index;
eaa2c3ae
AA
642 goto gpstates_done;
643 }
644
09ca4c9b 645 if (gpstates->last_gpstate_idx < new_index) {
eaa2c3ae
AA
646 gpstates->elapsed_time += cur_msec -
647 gpstates->last_sampled_time;
648
649 /*
650 * If its has been ramping down for more than MAX_RAMP_DOWN_TIME
651 * we should be resetting all global pstate related data. Set it
652 * equal to local pstate to start fresh.
653 */
654 if (gpstates->elapsed_time > MAX_RAMP_DOWN_TIME) {
655 reset_gpstates(policy);
09ca4c9b
AA
656 gpstates->highest_lpstate_idx = new_index;
657 gpstate_idx = new_index;
eaa2c3ae
AA
658 } else {
659 /* Elaspsed_time is less than 5 seconds, continue to rampdown */
09ca4c9b
AA
660 gpstate_idx = calc_global_pstate(gpstates->elapsed_time,
661 gpstates->highest_lpstate_idx,
662 new_index);
eaa2c3ae
AA
663 }
664 } else {
665 reset_gpstates(policy);
09ca4c9b
AA
666 gpstates->highest_lpstate_idx = new_index;
667 gpstate_idx = new_index;
eaa2c3ae
AA
668 }
669
670 /*
671 * If local pstate is equal to global pstate, rampdown is over
672 * So timer is not required to be queued.
673 */
09ca4c9b 674 if (gpstate_idx != new_index)
eaa2c3ae 675 queue_gpstate_timer(gpstates);
0bc10b93
AA
676 else
677 del_timer_sync(&gpstates->timer);
eaa2c3ae
AA
678
679gpstates_done:
09ca4c9b 680 freq_data.gpstate_id = idx_to_pstate(gpstate_idx);
eaa2c3ae 681 gpstates->last_sampled_time = cur_msec;
09ca4c9b
AA
682 gpstates->last_gpstate_idx = gpstate_idx;
683 gpstates->last_lpstate_idx = new_index;
eaa2c3ae 684
1fd3ff28
AA
685 spin_unlock(&gpstates->gpstate_lock);
686
b3d627a5
VS
687 /*
688 * Use smp_call_function to send IPI and execute the
689 * mtspr on target CPU. We could do that without IPI
690 * if current CPU is within policy->cpus (core)
691 */
692 smp_call_function_any(policy->cpus, set_pstate, &freq_data, 1);
b3d627a5
VS
693 return 0;
694}
695
696static int powernv_cpufreq_cpu_init(struct cpufreq_policy *policy)
697{
eaa2c3ae 698 int base, i, ret;
2920e9ce 699 struct kernfs_node *kn;
eaa2c3ae 700 struct global_pstate_info *gpstates;
b3d627a5
VS
701
702 base = cpu_first_thread_sibling(policy->cpu);
703
704 for (i = 0; i < threads_per_core; i++)
705 cpumask_set_cpu(base + i, policy->cpus);
706
2920e9ce
SB
707 kn = kernfs_find_and_get(policy->kobj.sd, throttle_attr_grp.name);
708 if (!kn) {
1b028984
SB
709 int ret;
710
711 ret = sysfs_create_group(&policy->kobj, &throttle_attr_grp);
712 if (ret) {
713 pr_info("Failed to create throttle stats directory for cpu %d\n",
714 policy->cpu);
715 return ret;
716 }
2920e9ce
SB
717 } else {
718 kernfs_put(kn);
1b028984 719 }
eaa2c3ae
AA
720
721 gpstates = kzalloc(sizeof(*gpstates), GFP_KERNEL);
722 if (!gpstates)
723 return -ENOMEM;
724
725 policy->driver_data = gpstates;
726
727 /* initialize timer */
7bc54b65 728 init_timer_pinned_deferrable(&gpstates->timer);
eaa2c3ae
AA
729 gpstates->timer.data = (unsigned long)policy;
730 gpstates->timer.function = gpstate_timer_handler;
731 gpstates->timer.expires = jiffies +
732 msecs_to_jiffies(GPSTATE_TIMER_INTERVAL);
733 spin_lock_init(&gpstates->gpstate_lock);
734 ret = cpufreq_table_validate_and_show(policy, powernv_freqs);
735
736 if (ret < 0)
737 kfree(policy->driver_data);
738
739 return ret;
740}
741
742static int powernv_cpufreq_cpu_exit(struct cpufreq_policy *policy)
743{
744 /* timer is deleted in cpufreq_cpu_stop() */
745 kfree(policy->driver_data);
746
747 return 0;
b3d627a5
VS
748}
749
cf30af76
SB
750static int powernv_cpufreq_reboot_notifier(struct notifier_block *nb,
751 unsigned long action, void *unused)
752{
753 int cpu;
754 struct cpufreq_policy cpu_policy;
755
756 rebooting = true;
757 for_each_online_cpu(cpu) {
758 cpufreq_get_policy(&cpu_policy, cpu);
759 powernv_cpufreq_target_index(&cpu_policy, get_nominal_index());
760 }
761
762 return NOTIFY_DONE;
763}
764
765static struct notifier_block powernv_cpufreq_reboot_nb = {
766 .notifier_call = powernv_cpufreq_reboot_notifier,
767};
768
735366fc
SB
769void powernv_cpufreq_work_fn(struct work_struct *work)
770{
771 struct chip *chip = container_of(work, struct chip, throttle);
22794280 772 unsigned int cpu;
6d167a44 773 cpumask_t mask;
735366fc 774
6d167a44
SB
775 get_online_cpus();
776 cpumask_and(&mask, &chip->mask, cpu_online_mask);
777 smp_call_function_any(&mask,
735366fc 778 powernv_cpufreq_throttle_check, NULL, 0);
22794280
SB
779
780 if (!chip->restore)
6d167a44 781 goto out;
22794280
SB
782
783 chip->restore = false;
6d167a44
SB
784 for_each_cpu(cpu, &mask) {
785 int index;
22794280
SB
786 struct cpufreq_policy policy;
787
788 cpufreq_get_policy(&policy, cpu);
82577360 789 index = cpufreq_table_find_index_c(&policy, policy.cur);
22794280 790 powernv_cpufreq_target_index(&policy, index);
6d167a44 791 cpumask_andnot(&mask, &mask, policy.cpus);
22794280 792 }
6d167a44
SB
793out:
794 put_online_cpus();
735366fc
SB
795}
796
cb166fa9
SB
797static int powernv_cpufreq_occ_msg(struct notifier_block *nb,
798 unsigned long msg_type, void *_msg)
799{
800 struct opal_msg *msg = _msg;
801 struct opal_occ_msg omsg;
735366fc 802 int i;
cb166fa9
SB
803
804 if (msg_type != OPAL_MSG_OCC)
805 return 0;
806
807 omsg.type = be64_to_cpu(msg->params[0]);
808
809 switch (omsg.type) {
810 case OCC_RESET:
811 occ_reset = true;
309d0631 812 pr_info("OCC (On Chip Controller - enforces hard thermal/power limits) Resetting\n");
cb166fa9
SB
813 /*
814 * powernv_cpufreq_throttle_check() is called in
815 * target() callback which can detect the throttle state
816 * for governors like ondemand.
817 * But static governors will not call target() often thus
818 * report throttling here.
819 */
820 if (!throttled) {
821 throttled = true;
c89f2682 822 pr_warn("CPU frequency is throttled for duration\n");
cb166fa9 823 }
309d0631 824
cb166fa9
SB
825 break;
826 case OCC_LOAD:
309d0631 827 pr_info("OCC Loading, CPU frequency is throttled until OCC is started\n");
cb166fa9
SB
828 break;
829 case OCC_THROTTLE:
830 omsg.chip = be64_to_cpu(msg->params[1]);
831 omsg.throttle_status = be64_to_cpu(msg->params[2]);
832
833 if (occ_reset) {
834 occ_reset = false;
835 throttled = false;
309d0631 836 pr_info("OCC Active, CPU frequency is no longer throttled\n");
735366fc 837
22794280
SB
838 for (i = 0; i < nr_chips; i++) {
839 chips[i].restore = true;
735366fc 840 schedule_work(&chips[i].throttle);
22794280 841 }
735366fc 842
cb166fa9
SB
843 return 0;
844 }
845
c89f2682
SB
846 for (i = 0; i < nr_chips; i++)
847 if (chips[i].id == omsg.chip)
848 break;
849
850 if (omsg.throttle_status >= 0 &&
1b028984 851 omsg.throttle_status <= OCC_MAX_THROTTLE_STATUS) {
c89f2682 852 chips[i].throttle_reason = omsg.throttle_status;
1b028984
SB
853 chips[i].reason[omsg.throttle_status]++;
854 }
735366fc 855
c89f2682
SB
856 if (!omsg.throttle_status)
857 chips[i].restore = true;
858
859 schedule_work(&chips[i].throttle);
cb166fa9
SB
860 }
861 return 0;
862}
863
864static struct notifier_block powernv_cpufreq_opal_nb = {
865 .notifier_call = powernv_cpufreq_occ_msg,
866 .next = NULL,
867 .priority = 0,
868};
869
b120339c
PM
870static void powernv_cpufreq_stop_cpu(struct cpufreq_policy *policy)
871{
872 struct powernv_smp_call_data freq_data;
eaa2c3ae 873 struct global_pstate_info *gpstates = policy->driver_data;
b120339c 874
09ca4c9b
AA
875 freq_data.pstate_id = idx_to_pstate(powernv_pstate_info.min);
876 freq_data.gpstate_id = idx_to_pstate(powernv_pstate_info.min);
b120339c 877 smp_call_function_single(policy->cpu, set_pstate, &freq_data, 1);
eaa2c3ae 878 del_timer_sync(&gpstates->timer);
b120339c
PM
879}
880
b3d627a5
VS
881static struct cpufreq_driver powernv_cpufreq_driver = {
882 .name = "powernv-cpufreq",
883 .flags = CPUFREQ_CONST_LOOPS,
884 .init = powernv_cpufreq_cpu_init,
eaa2c3ae 885 .exit = powernv_cpufreq_cpu_exit,
b3d627a5
VS
886 .verify = cpufreq_generic_frequency_table_verify,
887 .target_index = powernv_cpufreq_target_index,
888 .get = powernv_cpufreq_get,
b120339c 889 .stop_cpu = powernv_cpufreq_stop_cpu,
b3d627a5
VS
890 .attr = powernv_cpu_freq_attr,
891};
892
053819e0
SB
893static int init_chip_info(void)
894{
895 unsigned int chip[256];
896 unsigned int cpu, i;
897 unsigned int prev_chip_id = UINT_MAX;
96c4726f 898
3e5963bc 899 for_each_possible_cpu(cpu) {
053819e0
SB
900 unsigned int id = cpu_to_chip_id(cpu);
901
902 if (prev_chip_id != id) {
903 prev_chip_id = id;
904 chip[nr_chips++] = id;
905 }
906 }
907
c89f2682 908 chips = kcalloc(nr_chips, sizeof(struct chip), GFP_KERNEL);
053819e0 909 if (!chips)
3e5963bc 910 return -ENOMEM;
053819e0
SB
911
912 for (i = 0; i < nr_chips; i++) {
913 chips[i].id = chip[i];
735366fc
SB
914 cpumask_copy(&chips[i].mask, cpumask_of_node(chip[i]));
915 INIT_WORK(&chips[i].throttle, powernv_cpufreq_work_fn);
3e5963bc
MN
916 for_each_cpu(cpu, &chips[i].mask)
917 per_cpu(chip_info, cpu) = &chips[i];
053819e0
SB
918 }
919
920 return 0;
921}
922
c5e29ea7
SB
923static inline void clean_chip_info(void)
924{
925 kfree(chips);
c5e29ea7
SB
926}
927
928static inline void unregister_all_notifiers(void)
929{
930 opal_message_notifier_unregister(OPAL_MSG_OCC,
931 &powernv_cpufreq_opal_nb);
932 unregister_reboot_notifier(&powernv_cpufreq_reboot_nb);
933}
934
b3d627a5
VS
935static int __init powernv_cpufreq_init(void)
936{
937 int rc = 0;
938
6174bac8 939 /* Don't probe on pseries (guest) platforms */
e4d54f71 940 if (!firmware_has_feature(FW_FEATURE_OPAL))
6174bac8
VS
941 return -ENODEV;
942
b3d627a5
VS
943 /* Discover pstates from device tree and init */
944 rc = init_powernv_pstates();
c5e29ea7
SB
945 if (rc)
946 goto out;
b3d627a5 947
053819e0
SB
948 /* Populate chip info */
949 rc = init_chip_info();
950 if (rc)
c5e29ea7 951 goto out;
053819e0 952
cf30af76 953 register_reboot_notifier(&powernv_cpufreq_reboot_nb);
cb166fa9 954 opal_message_notifier_register(OPAL_MSG_OCC, &powernv_cpufreq_opal_nb);
c5e29ea7
SB
955
956 rc = cpufreq_register_driver(&powernv_cpufreq_driver);
957 if (!rc)
958 return 0;
959
960 pr_info("Failed to register the cpufreq driver (%d)\n", rc);
961 unregister_all_notifiers();
962 clean_chip_info();
963out:
964 pr_info("Platform driver disabled. System does not support PState control\n");
965 return rc;
b3d627a5
VS
966}
967module_init(powernv_cpufreq_init);
968
969static void __exit powernv_cpufreq_exit(void)
970{
971 cpufreq_unregister_driver(&powernv_cpufreq_driver);
c5e29ea7
SB
972 unregister_all_notifiers();
973 clean_chip_info();
b3d627a5
VS
974}
975module_exit(powernv_cpufreq_exit);
976
977MODULE_LICENSE("GPL");
978MODULE_AUTHOR("Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com>");
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