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4f788bb2 | 1 | /* |
4f788bb2 EM |
2 | * Copyright (C) 2008 Marvell International Ltd. |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/sched.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/cpufreq.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
23019a73 | 16 | #include <linux/io.h> |
4f788bb2 | 17 | |
adde904b | 18 | #include <mach/generic.h> |
4f788bb2 EM |
19 | #include <mach/pxa3xx-regs.h> |
20 | ||
4f788bb2 EM |
21 | #define HSS_104M (0) |
22 | #define HSS_156M (1) | |
23 | #define HSS_208M (2) | |
24 | #define HSS_312M (3) | |
25 | ||
26 | #define SMCFS_78M (0) | |
27 | #define SMCFS_104M (2) | |
28 | #define SMCFS_208M (5) | |
29 | ||
30 | #define SFLFS_104M (0) | |
31 | #define SFLFS_156M (1) | |
32 | #define SFLFS_208M (2) | |
33 | #define SFLFS_312M (3) | |
34 | ||
35 | #define XSPCLK_156M (0) | |
36 | #define XSPCLK_NONE (3) | |
37 | ||
38 | #define DMCFS_26M (0) | |
39 | #define DMCFS_260M (3) | |
40 | ||
41 | struct pxa3xx_freq_info { | |
42 | unsigned int cpufreq_mhz; | |
43 | unsigned int core_xl : 5; | |
44 | unsigned int core_xn : 3; | |
45 | unsigned int hss : 2; | |
46 | unsigned int dmcfs : 2; | |
47 | unsigned int smcfs : 3; | |
48 | unsigned int sflfs : 2; | |
49 | unsigned int df_clkdiv : 3; | |
50 | ||
51 | int vcc_core; /* in mV */ | |
52 | int vcc_sram; /* in mV */ | |
53 | }; | |
54 | ||
55 | #define OP(cpufreq, _xl, _xn, _hss, _dmc, _smc, _sfl, _dfi, vcore, vsram) \ | |
56 | { \ | |
57 | .cpufreq_mhz = cpufreq, \ | |
58 | .core_xl = _xl, \ | |
59 | .core_xn = _xn, \ | |
60 | .hss = HSS_##_hss##M, \ | |
61 | .dmcfs = DMCFS_##_dmc##M, \ | |
62 | .smcfs = SMCFS_##_smc##M, \ | |
63 | .sflfs = SFLFS_##_sfl##M, \ | |
64 | .df_clkdiv = _dfi, \ | |
65 | .vcc_core = vcore, \ | |
66 | .vcc_sram = vsram, \ | |
67 | } | |
68 | ||
69 | static struct pxa3xx_freq_info pxa300_freqs[] = { | |
70 | /* CPU XL XN HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */ | |
71 | OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */ | |
72 | OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */ | |
73 | OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */ | |
74 | OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */ | |
75 | }; | |
76 | ||
77 | static struct pxa3xx_freq_info pxa320_freqs[] = { | |
78 | /* CPU XL XN HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */ | |
79 | OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */ | |
80 | OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */ | |
81 | OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */ | |
82 | OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */ | |
83 | OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */ | |
84 | }; | |
85 | ||
86 | static unsigned int pxa3xx_freqs_num; | |
87 | static struct pxa3xx_freq_info *pxa3xx_freqs; | |
88 | static struct cpufreq_frequency_table *pxa3xx_freqs_table; | |
89 | ||
90 | static int setup_freqs_table(struct cpufreq_policy *policy, | |
91 | struct pxa3xx_freq_info *freqs, int num) | |
92 | { | |
93 | struct cpufreq_frequency_table *table; | |
15cc921b | 94 | int i; |
4f788bb2 EM |
95 | |
96 | table = kzalloc((num + 1) * sizeof(*table), GFP_KERNEL); | |
97 | if (table == NULL) | |
98 | return -ENOMEM; | |
99 | ||
100 | for (i = 0; i < num; i++) { | |
50701588 | 101 | table[i].driver_data = i; |
4f788bb2 EM |
102 | table[i].frequency = freqs[i].cpufreq_mhz * 1000; |
103 | } | |
50701588 | 104 | table[num].driver_data = i; |
4f788bb2 EM |
105 | table[num].frequency = CPUFREQ_TABLE_END; |
106 | ||
107 | pxa3xx_freqs = freqs; | |
108 | pxa3xx_freqs_num = num; | |
109 | pxa3xx_freqs_table = table; | |
110 | ||
15cc921b | 111 | return cpufreq_table_validate_and_show(policy, table); |
4f788bb2 EM |
112 | } |
113 | ||
114 | static void __update_core_freq(struct pxa3xx_freq_info *info) | |
115 | { | |
116 | uint32_t mask = ACCR_XN_MASK | ACCR_XL_MASK; | |
117 | uint32_t accr = ACCR; | |
118 | uint32_t xclkcfg; | |
119 | ||
120 | accr &= ~(ACCR_XN_MASK | ACCR_XL_MASK | ACCR_XSPCLK_MASK); | |
121 | accr |= ACCR_XN(info->core_xn) | ACCR_XL(info->core_xl); | |
122 | ||
123 | /* No clock until core PLL is re-locked */ | |
124 | accr |= ACCR_XSPCLK(XSPCLK_NONE); | |
125 | ||
126 | xclkcfg = (info->core_xn == 2) ? 0x3 : 0x2; /* turbo bit */ | |
127 | ||
128 | ACCR = accr; | |
129 | __asm__("mcr p14, 0, %0, c6, c0, 0\n" : : "r"(xclkcfg)); | |
130 | ||
131 | while ((ACSR & mask) != (accr & mask)) | |
132 | cpu_relax(); | |
133 | } | |
134 | ||
135 | static void __update_bus_freq(struct pxa3xx_freq_info *info) | |
136 | { | |
137 | uint32_t mask; | |
138 | uint32_t accr = ACCR; | |
139 | ||
140 | mask = ACCR_SMCFS_MASK | ACCR_SFLFS_MASK | ACCR_HSS_MASK | | |
141 | ACCR_DMCFS_MASK; | |
142 | ||
143 | accr &= ~mask; | |
144 | accr |= ACCR_SMCFS(info->smcfs) | ACCR_SFLFS(info->sflfs) | | |
145 | ACCR_HSS(info->hss) | ACCR_DMCFS(info->dmcfs); | |
146 | ||
147 | ACCR = accr; | |
148 | ||
149 | while ((ACSR & mask) != (accr & mask)) | |
150 | cpu_relax(); | |
151 | } | |
152 | ||
4f788bb2 EM |
153 | static unsigned int pxa3xx_cpufreq_get(unsigned int cpu) |
154 | { | |
ecf89b8a | 155 | return pxa3xx_get_clk_frequency_khz(0); |
4f788bb2 EM |
156 | } |
157 | ||
9c0ebcf7 | 158 | static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy, unsigned int index) |
4f788bb2 EM |
159 | { |
160 | struct pxa3xx_freq_info *next; | |
4f788bb2 | 161 | unsigned long flags; |
4f788bb2 EM |
162 | |
163 | if (policy->cpu != 0) | |
164 | return -EINVAL; | |
165 | ||
9c0ebcf7 | 166 | next = &pxa3xx_freqs[index]; |
4f788bb2 | 167 | |
4f788bb2 EM |
168 | local_irq_save(flags); |
169 | __update_core_freq(next); | |
170 | __update_bus_freq(next); | |
171 | local_irq_restore(flags); | |
172 | ||
4f788bb2 EM |
173 | return 0; |
174 | } | |
175 | ||
50e77fcd | 176 | static int pxa3xx_cpufreq_init(struct cpufreq_policy *policy) |
4f788bb2 EM |
177 | { |
178 | int ret = -EINVAL; | |
179 | ||
180 | /* set default policy and cpuinfo */ | |
200ea8e2 VK |
181 | policy->min = policy->cpuinfo.min_freq = 104000; |
182 | policy->max = policy->cpuinfo.max_freq = | |
183 | (cpu_is_pxa320()) ? 806000 : 624000; | |
4f788bb2 | 184 | policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ |
4f788bb2 EM |
185 | |
186 | if (cpu_is_pxa300() || cpu_is_pxa310()) | |
8ee3f8e0 JL |
187 | ret = setup_freqs_table(policy, pxa300_freqs, |
188 | ARRAY_SIZE(pxa300_freqs)); | |
4f788bb2 EM |
189 | |
190 | if (cpu_is_pxa320()) | |
8ee3f8e0 JL |
191 | ret = setup_freqs_table(policy, pxa320_freqs, |
192 | ARRAY_SIZE(pxa320_freqs)); | |
4f788bb2 EM |
193 | |
194 | if (ret) { | |
195 | pr_err("failed to setup frequency table\n"); | |
196 | return ret; | |
197 | } | |
198 | ||
199 | pr_info("CPUFREQ support for PXA3xx initialized\n"); | |
200 | return 0; | |
201 | } | |
202 | ||
203 | static struct cpufreq_driver pxa3xx_cpufreq_driver = { | |
ae6b4271 | 204 | .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
bf36e48d | 205 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 206 | .target_index = pxa3xx_cpufreq_set, |
4f788bb2 EM |
207 | .init = pxa3xx_cpufreq_init, |
208 | .get = pxa3xx_cpufreq_get, | |
209 | .name = "pxa3xx-cpufreq", | |
210 | }; | |
211 | ||
212 | static int __init cpufreq_init(void) | |
213 | { | |
214 | if (cpu_is_pxa3xx()) | |
215 | return cpufreq_register_driver(&pxa3xx_cpufreq_driver); | |
216 | ||
217 | return 0; | |
218 | } | |
219 | module_init(cpufreq_init); | |
220 | ||
221 | static void __exit cpufreq_exit(void) | |
222 | { | |
223 | cpufreq_unregister_driver(&pxa3xx_cpufreq_driver); | |
224 | } | |
225 | module_exit(cpufreq_exit); | |
226 | ||
227 | MODULE_DESCRIPTION("CPU frequency scaling driver for PXA3xx"); | |
228 | MODULE_LICENSE("GPL"); |