[deliverable/linux.git] / drivers / cpufreq / qoriq-cpufreq.c

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * CPU Frequency Scaling driver for Freescale QorIQ SoCs.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt

#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <linux/smp.h>

#if !defined(CONFIG_ARM)
#include <asm/smp.h>	/* for get_hard_smp_processor_id() in UP configs */
#endif

/**
 * struct cpu_data
 * @pclk: the parent clock of cpu
 * @table: frequency table
 */
struct cpu_data {
	struct clk **pclk;
	struct cpufreq_frequency_table *table;
};

/**
 * struct soc_data - SoC specific data
 * @freq_mask: mask the disallowed frequencies
 * @flag: unique flags
 */
struct soc_data {
	u32 freq_mask[4];
	u32 flag;
};

#define FREQ_MASK	1
/* see hardware specification for the allowed frqeuencies */
static const struct soc_data sdata[] = {
	{ /* used by p2041 and p3041 */
		.freq_mask = {0x8, 0x8, 0x2, 0x2},
		.flag = FREQ_MASK,
	},
	{ /* used by p5020 */
		.freq_mask = {0x8, 0x2},
		.flag = FREQ_MASK,
	},
	{ /* used by p4080, p5040 */
		.freq_mask = {0},
		.flag = 0,
	},
};

/*
 * the minimum allowed core frequency, in Hz
 * for chassis v1.0, >= platform frequency
 * for chassis v2.0, >= platform frequency / 2
 */
static u32 min_cpufreq;
static const u32 *fmask;

#if defined(CONFIG_ARM)
static int get_cpu_physical_id(int cpu)
{
	return topology_core_id(cpu);
}
#else
static int get_cpu_physical_id(int cpu)
{
	return get_hard_smp_processor_id(cpu);
}
#endif

static u32 get_bus_freq(void)
{
	struct device_node *soc;
	u32 sysfreq;

	soc = of_find_node_by_type(NULL, "soc");
	if (!soc)
		return 0;

	if (of_property_read_u32(soc, "bus-frequency", &sysfreq))
		sysfreq = 0;

	of_node_put(soc);

	return sysfreq;
}

static struct device_node *cpu_to_clk_node(int cpu)
{
	struct device_node *np, *clk_np;

	if (!cpu_present(cpu))
		return NULL;

	np = of_get_cpu_node(cpu, NULL);
	if (!np)
		return NULL;

	clk_np = of_parse_phandle(np, "clocks", 0);
	if (!clk_np)
		return NULL;

	of_node_put(np);

	return clk_np;
}

/* traverse cpu nodes to get cpu mask of sharing clock wire */
static void set_affected_cpus(struct cpufreq_policy *policy)
{
	struct device_node *np, *clk_np;
	struct cpumask *dstp = policy->cpus;
	int i;

	np = cpu_to_clk_node(policy->cpu);
	if (!np)
		return;

	for_each_present_cpu(i) {
		clk_np = cpu_to_clk_node(i);
		if (!clk_np)
			continue;

		if (clk_np == np)
			cpumask_set_cpu(i, dstp);

		of_node_put(clk_np);
	}
	of_node_put(np);
}

/* reduce the duplicated frequencies in frequency table */
static void freq_table_redup(struct cpufreq_frequency_table *freq_table,
		int count)
{
	int i, j;

	for (i = 1; i < count; i++) {
		for (j = 0; j < i; j++) {
			if (freq_table[j].frequency == CPUFREQ_ENTRY_INVALID ||
					freq_table[j].frequency !=
					freq_table[i].frequency)
				continue;

			freq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
			break;
		}
	}
}

/* sort the frequencies in frequency table in descenting order */
static void freq_table_sort(struct cpufreq_frequency_table *freq_table,
		int count)
{
	int i, j, ind;
	unsigned int freq, max_freq;
	struct cpufreq_frequency_table table;

	for (i = 0; i < count - 1; i++) {
		max_freq = freq_table[i].frequency;
		ind = i;
		for (j = i + 1; j < count; j++) {
			freq = freq_table[j].frequency;
			if (freq == CPUFREQ_ENTRY_INVALID ||
					freq <= max_freq)
				continue;
			ind = j;
			max_freq = freq;
		}

		if (ind != i) {
			/* exchange the frequencies */
			table.driver_data = freq_table[i].driver_data;
			table.frequency = freq_table[i].frequency;
			freq_table[i].driver_data = freq_table[ind].driver_data;
			freq_table[i].frequency = freq_table[ind].frequency;
			freq_table[ind].driver_data = table.driver_data;
			freq_table[ind].frequency = table.frequency;
		}
	}
}

static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
{
	struct device_node *np, *pnode;
	int i, count, ret;
	u32 freq, mask;
	struct clk *clk;
	struct cpufreq_frequency_table *table;
	struct cpu_data *data;
	unsigned int cpu = policy->cpu;
	u64 u64temp;

	np = of_get_cpu_node(cpu, NULL);
	if (!np)
		return -ENODEV;

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		goto err_np;

	policy->clk = of_clk_get(np, 0);
	if (IS_ERR(policy->clk)) {
		pr_err("%s: no clock information\n", __func__);
		goto err_nomem2;
	}

	pnode = of_parse_phandle(np, "clocks", 0);
	if (!pnode) {
		pr_err("%s: could not get clock information\n", __func__);
		goto err_nomem2;
	}

	count = of_property_count_strings(pnode, "clock-names");
	data->pclk = kcalloc(count, sizeof(struct clk *), GFP_KERNEL);
	if (!data->pclk) {
		pr_err("%s: no memory\n", __func__);
		goto err_node;
	}

	table = kcalloc(count + 1, sizeof(*table), GFP_KERNEL);
	if (!table) {
		pr_err("%s: no memory\n", __func__);
		goto err_pclk;
	}

	if (fmask)
		mask = fmask[get_cpu_physical_id(cpu)];
	else
		mask = 0x0;

	for (i = 0; i < count; i++) {
		clk = of_clk_get(pnode, i);
		data->pclk[i] = clk;
		freq = clk_get_rate(clk);
		/*
		 * the clock is valid if its frequency is not masked
		 * and large than minimum allowed frequency.
		 */
		if (freq < min_cpufreq || (mask & (1 << i)))
			table[i].frequency = CPUFREQ_ENTRY_INVALID;
		else
			table[i].frequency = freq / 1000;
		table[i].driver_data = i;
	}
	freq_table_redup(table, count);
	freq_table_sort(table, count);
	table[i].frequency = CPUFREQ_TABLE_END;

	/* set the min and max frequency properly */
	ret = cpufreq_table_validate_and_show(policy, table);
	if (ret) {
		pr_err("invalid frequency table: %d\n", ret);
		goto err_nomem1;
	}

	data->table = table;

	/* update ->cpus if we have cluster, no harm if not */
	set_affected_cpus(policy);
	policy->driver_data = data;

	/* Minimum transition latency is 12 platform clocks */
	u64temp = 12ULL * NSEC_PER_SEC;
	do_div(u64temp, get_bus_freq());
	policy->cpuinfo.transition_latency = u64temp + 1;

	of_node_put(np);
	of_node_put(pnode);

	return 0;

err_nomem1:
	kfree(table);
err_pclk:
	kfree(data->pclk);
err_node:
	of_node_put(pnode);
err_nomem2:
	policy->driver_data = NULL;
	kfree(data);
err_np:
	of_node_put(np);

	return -ENODEV;
}

static int __exit qoriq_cpufreq_cpu_exit(struct cpufreq_policy *policy)
{
	struct cpu_data *data = policy->driver_data;

	kfree(data->pclk);
	kfree(data->table);
	kfree(data);
	policy->driver_data = NULL;

	return 0;
}

static int qoriq_cpufreq_target(struct cpufreq_policy *policy,
		unsigned int index)
{
	struct clk *parent;
	struct cpu_data *data = policy->driver_data;

	parent = data->pclk[data->table[index].driver_data];
	return clk_set_parent(policy->clk, parent);
}

static struct cpufreq_driver qoriq_cpufreq_driver = {
	.name		= "qoriq_cpufreq",
	.flags		= CPUFREQ_CONST_LOOPS,
	.init		= qoriq_cpufreq_cpu_init,
	.exit		= __exit_p(qoriq_cpufreq_cpu_exit),
	.verify		= cpufreq_generic_frequency_table_verify,
	.target_index	= qoriq_cpufreq_target,
	.get		= cpufreq_generic_get,
	.attr		= cpufreq_generic_attr,
};

static const struct of_device_id node_matches[] __initconst = {
	{ .compatible = "fsl,p2041-clockgen", .data = &sdata[0], },
	{ .compatible = "fsl,p3041-clockgen", .data = &sdata[0], },
	{ .compatible = "fsl,p5020-clockgen", .data = &sdata[1], },
	{ .compatible = "fsl,p4080-clockgen", .data = &sdata[2], },
	{ .compatible = "fsl,p5040-clockgen", .data = &sdata[2], },
	{ .compatible = "fsl,qoriq-clockgen-2.0", },
	{}
};

static int __init qoriq_cpufreq_init(void)
{
	int ret;
	struct device_node  *np;
	const struct of_device_id *match;
	const struct soc_data *data;

	np = of_find_matching_node(NULL, node_matches);
	if (!np)
		return -ENODEV;

	match = of_match_node(node_matches, np);
	data = match->data;
	if (data) {
		if (data->flag)
			fmask = data->freq_mask;
		min_cpufreq = get_bus_freq();
	} else {
		min_cpufreq = get_bus_freq() / 2;
	}

	of_node_put(np);

	ret = cpufreq_register_driver(&qoriq_cpufreq_driver);
	if (!ret)
		pr_info("Freescale QorIQ CPU frequency scaling driver\n");

	return ret;
}
module_init(qoriq_cpufreq_init);

static void __exit qoriq_cpufreq_exit(void)
{
	cpufreq_unregister_driver(&qoriq_cpufreq_driver);
}
module_exit(qoriq_cpufreq_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs");
Commit	Line	Data
defa4c73 TY	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
a4f20742	4	* CPU Frequency Scaling driver for Freescale QorIQ SoCs.
defa4c73 TY	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	12
	13	#include <linux/clk.h>
	14	#include <linux/cpufreq.h>
	15	#include <linux/errno.h>
defa4c73 TY	16	#include <linux/init.h>
	17	#include <linux/kernel.h>
	18	#include <linux/module.h>
	19	#include <linux/mutex.h>
	20	#include <linux/of.h>
	21	#include <linux/slab.h>
	22	#include <linux/smp.h>
	23
4492d1a2	24	#if !defined(CONFIG_ARM)
5877b4f4	25	#include <asm/smp.h> /* for get_hard_smp_processor_id() in UP configs */
4492d1a2	26	#endif
5877b4f4	27
defa4c73	28	/**
a4f20742	29	* struct cpu_data
8a95c144	30	* @pclk: the parent clock of cpu
defa4c73 TY	31	* @table: frequency table
	32	*/
	33	struct cpu_data {
8a95c144	34	struct clk **pclk;
defa4c73 TY	35	struct cpufreq_frequency_table *table;
	36	};
	37
	38	/**
	39	* struct soc_data - SoC specific data
	40	* @freq_mask: mask the disallowed frequencies
	41	* @flag: unique flags
	42	*/
	43	struct soc_data {
	44	u32 freq_mask[4];
	45	u32 flag;
	46	};
	47
	48	#define FREQ_MASK 1
	49	/* see hardware specification for the allowed frqeuencies */
	50	static const struct soc_data sdata[] = {
	51	{ /* used by p2041 and p3041 */
	52	.freq_mask = {0x8, 0x8, 0x2, 0x2},
	53	.flag = FREQ_MASK,
	54	},
	55	{ /* used by p5020 */
	56	.freq_mask = {0x8, 0x2},
	57	.flag = FREQ_MASK,
	58	},
	59	{ /* used by p4080, p5040 */
	60	.freq_mask = {0},
	61	.flag = 0,
	62	},
	63	};
	64
	65	/*
	66	* the minimum allowed core frequency, in Hz
	67	* for chassis v1.0, >= platform frequency
	68	* for chassis v2.0, >= platform frequency / 2
	69	*/
	70	static u32 min_cpufreq;
	71	static const u32 *fmask;
	72
a4f20742 TY	73	#if defined(CONFIG_ARM)
	74	static int get_cpu_physical_id(int cpu)
	75	{
	76	return topology_core_id(cpu);
	77	}
	78	#else
	79	static int get_cpu_physical_id(int cpu)
	80	{
	81	return get_hard_smp_processor_id(cpu);
	82	}
	83	#endif
	84
	85	static u32 get_bus_freq(void)
	86	{
	87	struct device_node *soc;
	88	u32 sysfreq;
	89
	90	soc = of_find_node_by_type(NULL, "soc");
	91	if (!soc)
	92	return 0;
	93
	94	if (of_property_read_u32(soc, "bus-frequency", &sysfreq))
	95	sysfreq = 0;
	96
	97	of_node_put(soc);
defa4c73	98
a4f20742 TY	99	return sysfreq;
a4f20742 TY	100	}
defa4c73	101
a4f20742	102	static struct device_node *cpu_to_clk_node(int cpu)
defa4c73	103	{
a4f20742 TY	104	struct device_node np, clk_np;
	105
	106	if (!cpu_present(cpu))
	107	return NULL;
	108
	109	np = of_get_cpu_node(cpu, NULL);
	110	if (!np)
	111	return NULL;
	112
	113	clk_np = of_parse_phandle(np, "clocks", 0);
	114	if (!clk_np)
	115	return NULL;
	116
	117	of_node_put(np);
	118
	119	return clk_np;
	120	}
	121
	122	/* traverse cpu nodes to get cpu mask of sharing clock wire */
	123	static void set_affected_cpus(struct cpufreq_policy *policy)
	124	{
	125	struct device_node np, clk_np;
	126	struct cpumask *dstp = policy->cpus;
	127	int i;
	128
	129	np = cpu_to_clk_node(policy->cpu);
	130	if (!np)
	131	return;
	132
	133	for_each_present_cpu(i) {
	134	clk_np = cpu_to_clk_node(i);
	135	if (!clk_np)
	136	continue;
	137
	138	if (clk_np == np)
	139	cpumask_set_cpu(i, dstp);
	140
	141	of_node_put(clk_np);
	142	}
	143	of_node_put(np);
defa4c73	144	}
defa4c73	145
defa4c73 TY	146	/* reduce the duplicated frequencies in frequency table */
	147	static void freq_table_redup(struct cpufreq_frequency_table *freq_table,
	148	int count)
	149	{
	150	int i, j;
	151
	152	for (i = 1; i < count; i++) {
	153	for (j = 0; j < i; j++) {
	154	if (freq_table[j].frequency == CPUFREQ_ENTRY_INVALID \|\|
	155	freq_table[j].frequency !=
	156	freq_table[i].frequency)
	157	continue;
	158
	159	freq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
	160	break;
	161	}
	162	}
	163	}
	164
	165	/* sort the frequencies in frequency table in descenting order */
	166	static void freq_table_sort(struct cpufreq_frequency_table *freq_table,
	167	int count)
	168	{
	169	int i, j, ind;
	170	unsigned int freq, max_freq;
	171	struct cpufreq_frequency_table table;
a4f20742	172
defa4c73 TY	173	for (i = 0; i < count - 1; i++) {
	174	max_freq = freq_table[i].frequency;
	175	ind = i;
	176	for (j = i + 1; j < count; j++) {
	177	freq = freq_table[j].frequency;
	178	if (freq == CPUFREQ_ENTRY_INVALID \|\|
	179	freq <= max_freq)
	180	continue;
	181	ind = j;
	182	max_freq = freq;
	183	}
	184
	185	if (ind != i) {
	186	/* exchange the frequencies */
	187	table.driver_data = freq_table[i].driver_data;
	188	table.frequency = freq_table[i].frequency;
	189	freq_table[i].driver_data = freq_table[ind].driver_data;
	190	freq_table[i].frequency = freq_table[ind].frequency;
	191	freq_table[ind].driver_data = table.driver_data;
	192	freq_table[ind].frequency = table.frequency;
	193	}
	194	}
	195	}
	196
a4f20742	197	static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
defa4c73	198	{
8a95c144	199	struct device_node np, pnode;
defa4c73 TY	200	int i, count, ret;
	201	u32 freq, mask;
	202	struct clk *clk;
	203	struct cpufreq_frequency_table *table;
	204	struct cpu_data *data;
	205	unsigned int cpu = policy->cpu;
906fe033	206	u64 u64temp;
defa4c73 TY	207
	208	np = of_get_cpu_node(cpu, NULL);
	209	if (!np)
	210	return -ENODEV;
	211
	212	data = kzalloc(sizeof(*data), GFP_KERNEL);
a4f20742	213	if (!data)
defa4c73	214	goto err_np;
defa4c73	215
652ed95d VK	216	policy->clk = of_clk_get(np, 0);
652ed95d VK	217	if (IS_ERR(policy->clk)) {
defa4c73 TY	218	pr_err("%s: no clock information\n", __func__);
	219	goto err_nomem2;
	220	}
	221
8a95c144 TY	222	pnode = of_parse_phandle(np, "clocks", 0);
8a95c144 TY	223	if (!pnode) {
defa4c73 TY	224	pr_err("%s: could not get clock information\n", __func__);
	225	goto err_nomem2;
	226	}
	227
8a95c144 TY	228	count = of_property_count_strings(pnode, "clock-names");
	229	data->pclk = kcalloc(count, sizeof(struct clk *), GFP_KERNEL);
	230	if (!data->pclk) {
	231	pr_err("%s: no memory\n", __func__);
	232	goto err_node;
	233	}
	234
defa4c73 TY	235	table = kcalloc(count + 1, sizeof(*table), GFP_KERNEL);
	236	if (!table) {
	237	pr_err("%s: no memory\n", __func__);
8a95c144	238	goto err_pclk;
defa4c73 TY	239	}
	240
	241	if (fmask)
a4f20742	242	mask = fmask[get_cpu_physical_id(cpu)];
defa4c73 TY	243	else
	244	mask = 0x0;
	245
	246	for (i = 0; i < count; i++) {
8a95c144 TY	247	clk = of_clk_get(pnode, i);
8a95c144 TY	248	data->pclk[i] = clk;
defa4c73 TY	249	freq = clk_get_rate(clk);
	250	/*
	251	* the clock is valid if its frequency is not masked
	252	* and large than minimum allowed frequency.
	253	*/
	254	if (freq < min_cpufreq \|\| (mask & (1 << i)))
	255	table[i].frequency = CPUFREQ_ENTRY_INVALID;
	256	else
	257	table[i].frequency = freq / 1000;
	258	table[i].driver_data = i;
	259	}
	260	freq_table_redup(table, count);
	261	freq_table_sort(table, count);
	262	table[i].frequency = CPUFREQ_TABLE_END;
	263
	264	/* set the min and max frequency properly */
6b4147db	265	ret = cpufreq_table_validate_and_show(policy, table);
defa4c73 TY	266	if (ret) {
	267	pr_err("invalid frequency table: %d\n", ret);
	268	goto err_nomem1;
	269	}
	270
	271	data->table = table;
defa4c73 TY	272
defa4c73 TY	273	/* update ->cpus if we have cluster, no harm if not */
a4f20742 TY	274	set_affected_cpus(policy);
a4f20742 TY	275	policy->driver_data = data;
defa4c73	276
906fe033 ES	277	/* Minimum transition latency is 12 platform clocks */
906fe033 ES	278	u64temp = 12ULL * NSEC_PER_SEC;
a4f20742	279	do_div(u64temp, get_bus_freq());
906fe033	280	policy->cpuinfo.transition_latency = u64temp + 1;
6712d293	281
defa4c73	282	of_node_put(np);
8a95c144	283	of_node_put(pnode);
defa4c73 TY	284
	285	return 0;
	286
	287	err_nomem1:
	288	kfree(table);
8a95c144 TY	289	err_pclk:
8a95c144 TY	290	kfree(data->pclk);
defa4c73	291	err_node:
8a95c144	292	of_node_put(pnode);
defa4c73	293	err_nomem2:
a4f20742	294	policy->driver_data = NULL;
defa4c73 TY	295	kfree(data);
	296	err_np:
	297	of_node_put(np);
	298
	299	return -ENODEV;
	300	}
	301
a4f20742	302	static int __exit qoriq_cpufreq_cpu_exit(struct cpufreq_policy *policy)
defa4c73	303	{
a4f20742	304	struct cpu_data *data = policy->driver_data;
defa4c73	305
8a95c144	306	kfree(data->pclk);
defa4c73 TY	307	kfree(data->table);
defa4c73 TY	308	kfree(data);
a4f20742	309	policy->driver_data = NULL;
defa4c73 TY	310
	311	return 0;
	312	}
	313
a4f20742	314	static int qoriq_cpufreq_target(struct cpufreq_policy *policy,
9c0ebcf7	315	unsigned int index)
defa4c73	316	{
defa4c73	317	struct clk *parent;
a4f20742	318	struct cpu_data *data = policy->driver_data;
defa4c73	319
8a95c144	320	parent = data->pclk[data->table[index].driver_data];
652ed95d	321	return clk_set_parent(policy->clk, parent);
defa4c73 TY	322	}
defa4c73 TY	323
a4f20742 TY	324	static struct cpufreq_driver qoriq_cpufreq_driver = {
a4f20742 TY	325	.name = "qoriq_cpufreq",
defa4c73	326	.flags = CPUFREQ_CONST_LOOPS,
a4f20742 TY	327	.init = qoriq_cpufreq_cpu_init,
a4f20742 TY	328	.exit = __exit_p(qoriq_cpufreq_cpu_exit),
dc2398d7	329	.verify = cpufreq_generic_frequency_table_verify,
a4f20742	330	.target_index = qoriq_cpufreq_target,
652ed95d	331	.get = cpufreq_generic_get,
dc2398d7	332	.attr = cpufreq_generic_attr,
defa4c73 TY	333	};
defa4c73 TY	334
a4f20742	335	static const struct of_device_id node_matches[] __initconst = {
defa4c73 TY	336	{ .compatible = "fsl,p2041-clockgen", .data = &sdata[0], },
	337	{ .compatible = "fsl,p3041-clockgen", .data = &sdata[0], },
	338	{ .compatible = "fsl,p5020-clockgen", .data = &sdata[1], },
	339	{ .compatible = "fsl,p4080-clockgen", .data = &sdata[2], },
	340	{ .compatible = "fsl,p5040-clockgen", .data = &sdata[2], },
	341	{ .compatible = "fsl,qoriq-clockgen-2.0", },
	342	{}
	343	};
	344
a4f20742	345	static int __init qoriq_cpufreq_init(void)
defa4c73 TY	346	{
	347	int ret;
	348	struct device_node *np;
	349	const struct of_device_id *match;
	350	const struct soc_data *data;
defa4c73 TY	351
	352	np = of_find_matching_node(NULL, node_matches);
	353	if (!np)
	354	return -ENODEV;
	355
defa4c73 TY	356	match = of_match_node(node_matches, np);
	357	data = match->data;
	358	if (data) {
	359	if (data->flag)
	360	fmask = data->freq_mask;
a4f20742	361	min_cpufreq = get_bus_freq();
defa4c73	362	} else {
a4f20742	363	min_cpufreq = get_bus_freq() / 2;
defa4c73 TY	364	}
	365
	366	of_node_put(np);
	367
a4f20742	368	ret = cpufreq_register_driver(&qoriq_cpufreq_driver);
defa4c73	369	if (!ret)
a4f20742	370	pr_info("Freescale QorIQ CPU frequency scaling driver\n");
defa4c73 TY	371
defa4c73 TY	372	return ret;
defa4c73	373	}
a4f20742	374	module_init(qoriq_cpufreq_init);
defa4c73	375
a4f20742	376	static void __exit qoriq_cpufreq_exit(void)
defa4c73	377	{
a4f20742	378	cpufreq_unregister_driver(&qoriq_cpufreq_driver);
defa4c73	379	}
a4f20742	380	module_exit(qoriq_cpufreq_exit);
defa4c73 TY	381
	382	MODULE_LICENSE("GPL");
	383	MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
a4f20742	384	MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs");