[deliverable/linux.git] / drivers / cpufreq / qoriq-cpufreq.c

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * CPU Frequency Scaling driver for Freescale QorIQ SoCs.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt

#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <linux/smp.h>

#include <asm/smp.h>	/* for get_hard_smp_processor_id() in UP configs */

/**
 * struct cpu_data
 * @parent: the parent node of cpu clock
 * @table: frequency table
 */
struct cpu_data {
	struct device_node *parent;
	struct cpufreq_frequency_table *table;
};

/**
 * struct soc_data - SoC specific data
 * @freq_mask: mask the disallowed frequencies
 * @flag: unique flags
 */
struct soc_data {
	u32 freq_mask[4];
	u32 flag;
};

#define FREQ_MASK	1
/* see hardware specification for the allowed frqeuencies */
static const struct soc_data sdata[] = {
	{ /* used by p2041 and p3041 */
		.freq_mask = {0x8, 0x8, 0x2, 0x2},
		.flag = FREQ_MASK,
	},
	{ /* used by p5020 */
		.freq_mask = {0x8, 0x2},
		.flag = FREQ_MASK,
	},
	{ /* used by p4080, p5040 */
		.freq_mask = {0},
		.flag = 0,
	},
};

/*
 * the minimum allowed core frequency, in Hz
 * for chassis v1.0, >= platform frequency
 * for chassis v2.0, >= platform frequency / 2
 */
static u32 min_cpufreq;
static const u32 *fmask;

#if defined(CONFIG_ARM)
static int get_cpu_physical_id(int cpu)
{
	return topology_core_id(cpu);
}
#else
static int get_cpu_physical_id(int cpu)
{
	return get_hard_smp_processor_id(cpu);
}
#endif

static u32 get_bus_freq(void)
{
	struct device_node *soc;
	u32 sysfreq;

	soc = of_find_node_by_type(NULL, "soc");
	if (!soc)
		return 0;

	if (of_property_read_u32(soc, "bus-frequency", &sysfreq))
		sysfreq = 0;

	of_node_put(soc);

	return sysfreq;
}

static struct device_node *cpu_to_clk_node(int cpu)
{
	struct device_node *np, *clk_np;

	if (!cpu_present(cpu))
		return NULL;

	np = of_get_cpu_node(cpu, NULL);
	if (!np)
		return NULL;

	clk_np = of_parse_phandle(np, "clocks", 0);
	if (!clk_np)
		return NULL;

	of_node_put(np);

	return clk_np;
}

/* traverse cpu nodes to get cpu mask of sharing clock wire */
static void set_affected_cpus(struct cpufreq_policy *policy)
{
	struct device_node *np, *clk_np;
	struct cpumask *dstp = policy->cpus;
	int i;

	np = cpu_to_clk_node(policy->cpu);
	if (!np)
		return;

	for_each_present_cpu(i) {
		clk_np = cpu_to_clk_node(i);
		if (!clk_np)
			continue;

		if (clk_np == np)
			cpumask_set_cpu(i, dstp);

		of_node_put(clk_np);
	}
	of_node_put(np);
}

/* reduce the duplicated frequencies in frequency table */
static void freq_table_redup(struct cpufreq_frequency_table *freq_table,
		int count)
{
	int i, j;

	for (i = 1; i < count; i++) {
		for (j = 0; j < i; j++) {
			if (freq_table[j].frequency == CPUFREQ_ENTRY_INVALID ||
					freq_table[j].frequency !=
					freq_table[i].frequency)
				continue;

			freq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
			break;
		}
	}
}

/* sort the frequencies in frequency table in descenting order */
static void freq_table_sort(struct cpufreq_frequency_table *freq_table,
		int count)
{
	int i, j, ind;
	unsigned int freq, max_freq;
	struct cpufreq_frequency_table table;

	for (i = 0; i < count - 1; i++) {
		max_freq = freq_table[i].frequency;
		ind = i;
		for (j = i + 1; j < count; j++) {
			freq = freq_table[j].frequency;
			if (freq == CPUFREQ_ENTRY_INVALID ||
					freq <= max_freq)
				continue;
			ind = j;
			max_freq = freq;
		}

		if (ind != i) {
			/* exchange the frequencies */
			table.driver_data = freq_table[i].driver_data;
			table.frequency = freq_table[i].frequency;
			freq_table[i].driver_data = freq_table[ind].driver_data;
			freq_table[i].frequency = freq_table[ind].frequency;
			freq_table[ind].driver_data = table.driver_data;
			freq_table[ind].frequency = table.frequency;
		}
	}
}

static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
{
	struct device_node *np;
	int i, count, ret;
	u32 freq, mask;
	struct clk *clk;
	struct cpufreq_frequency_table *table;
	struct cpu_data *data;
	unsigned int cpu = policy->cpu;
	u64 u64temp;

	np = of_get_cpu_node(cpu, NULL);
	if (!np)
		return -ENODEV;

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		goto err_np;

	policy->clk = of_clk_get(np, 0);
	if (IS_ERR(policy->clk)) {
		pr_err("%s: no clock information\n", __func__);
		goto err_nomem2;
	}

	data->parent = of_parse_phandle(np, "clocks", 0);
	if (!data->parent) {
		pr_err("%s: could not get clock information\n", __func__);
		goto err_nomem2;
	}

	count = of_property_count_strings(data->parent, "clock-names");
	table = kcalloc(count + 1, sizeof(*table), GFP_KERNEL);
	if (!table) {
		pr_err("%s: no memory\n", __func__);
		goto err_node;
	}

	if (fmask)
		mask = fmask[get_cpu_physical_id(cpu)];
	else
		mask = 0x0;

	for (i = 0; i < count; i++) {
		clk = of_clk_get(data->parent, i);
		freq = clk_get_rate(clk);
		/*
		 * the clock is valid if its frequency is not masked
		 * and large than minimum allowed frequency.
		 */
		if (freq < min_cpufreq || (mask & (1 << i)))
			table[i].frequency = CPUFREQ_ENTRY_INVALID;
		else
			table[i].frequency = freq / 1000;
		table[i].driver_data = i;
	}
	freq_table_redup(table, count);
	freq_table_sort(table, count);
	table[i].frequency = CPUFREQ_TABLE_END;

	/* set the min and max frequency properly */
	ret = cpufreq_table_validate_and_show(policy, table);
	if (ret) {
		pr_err("invalid frequency table: %d\n", ret);
		goto err_nomem1;
	}

	data->table = table;

	/* update ->cpus if we have cluster, no harm if not */
	set_affected_cpus(policy);
	policy->driver_data = data;

	/* Minimum transition latency is 12 platform clocks */
	u64temp = 12ULL * NSEC_PER_SEC;
	do_div(u64temp, get_bus_freq());
	policy->cpuinfo.transition_latency = u64temp + 1;

	of_node_put(np);

	return 0;

err_nomem1:
	kfree(table);
err_node:
	of_node_put(data->parent);
err_nomem2:
	policy->driver_data = NULL;
	kfree(data);
err_np:
	of_node_put(np);

	return -ENODEV;
}

static int __exit qoriq_cpufreq_cpu_exit(struct cpufreq_policy *policy)
{
	struct cpu_data *data = policy->driver_data;

	of_node_put(data->parent);
	kfree(data->table);
	kfree(data);
	policy->driver_data = NULL;

	return 0;
}

static int qoriq_cpufreq_target(struct cpufreq_policy *policy,
		unsigned int index)
{
	struct clk *parent;
	struct cpu_data *data = policy->driver_data;

	parent = of_clk_get(data->parent, data->table[index].driver_data);
	return clk_set_parent(policy->clk, parent);
}

static struct cpufreq_driver qoriq_cpufreq_driver = {
	.name		= "qoriq_cpufreq",
	.flags		= CPUFREQ_CONST_LOOPS,
	.init		= qoriq_cpufreq_cpu_init,
	.exit		= __exit_p(qoriq_cpufreq_cpu_exit),
	.verify		= cpufreq_generic_frequency_table_verify,
	.target_index	= qoriq_cpufreq_target,
	.get		= cpufreq_generic_get,
	.attr		= cpufreq_generic_attr,
};

static const struct of_device_id node_matches[] __initconst = {
	{ .compatible = "fsl,p2041-clockgen", .data = &sdata[0], },
	{ .compatible = "fsl,p3041-clockgen", .data = &sdata[0], },
	{ .compatible = "fsl,p5020-clockgen", .data = &sdata[1], },
	{ .compatible = "fsl,p4080-clockgen", .data = &sdata[2], },
	{ .compatible = "fsl,p5040-clockgen", .data = &sdata[2], },
	{ .compatible = "fsl,qoriq-clockgen-2.0", },
	{}
};

static int __init qoriq_cpufreq_init(void)
{
	int ret;
	struct device_node  *np;
	const struct of_device_id *match;
	const struct soc_data *data;

	np = of_find_matching_node(NULL, node_matches);
	if (!np)
		return -ENODEV;

	match = of_match_node(node_matches, np);
	data = match->data;
	if (data) {
		if (data->flag)
			fmask = data->freq_mask;
		min_cpufreq = get_bus_freq();
	} else {
		min_cpufreq = get_bus_freq() / 2;
	}

	of_node_put(np);

	ret = cpufreq_register_driver(&qoriq_cpufreq_driver);
	if (!ret)
		pr_info("Freescale QorIQ CPU frequency scaling driver\n");

	return ret;
}
module_init(qoriq_cpufreq_init);

static void __exit qoriq_cpufreq_exit(void)
{
	cpufreq_unregister_driver(&qoriq_cpufreq_driver);
}
module_exit(qoriq_cpufreq_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs");
Commit	Line	Data
defa4c73 TY	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
a4f20742	4	* CPU Frequency Scaling driver for Freescale QorIQ SoCs.
defa4c73 TY	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	12
	13	#include <linux/clk.h>
	14	#include <linux/cpufreq.h>
	15	#include <linux/errno.h>
defa4c73 TY	16	#include <linux/init.h>
	17	#include <linux/kernel.h>
	18	#include <linux/module.h>
	19	#include <linux/mutex.h>
	20	#include <linux/of.h>
	21	#include <linux/slab.h>
	22	#include <linux/smp.h>
	23
5877b4f4 GU	24	#include <asm/smp.h> /* for get_hard_smp_processor_id() in UP configs */
5877b4f4 GU	25
defa4c73	26	/**
a4f20742	27	* struct cpu_data
defa4c73 TY	28	* @parent: the parent node of cpu clock
	29	* @table: frequency table
	30	*/
	31	struct cpu_data {
defa4c73 TY	32	struct device_node *parent;
	33	struct cpufreq_frequency_table *table;
	34	};
	35
	36	/**
	37	* struct soc_data - SoC specific data
	38	* @freq_mask: mask the disallowed frequencies
	39	* @flag: unique flags
	40	*/
	41	struct soc_data {
	42	u32 freq_mask[4];
	43	u32 flag;
	44	};
	45
	46	#define FREQ_MASK 1
	47	/* see hardware specification for the allowed frqeuencies */
	48	static const struct soc_data sdata[] = {
	49	{ /* used by p2041 and p3041 */
	50	.freq_mask = {0x8, 0x8, 0x2, 0x2},
	51	.flag = FREQ_MASK,
	52	},
	53	{ /* used by p5020 */
	54	.freq_mask = {0x8, 0x2},
	55	.flag = FREQ_MASK,
	56	},
	57	{ /* used by p4080, p5040 */
	58	.freq_mask = {0},
	59	.flag = 0,
	60	},
	61	};
	62
	63	/*
	64	* the minimum allowed core frequency, in Hz
	65	* for chassis v1.0, >= platform frequency
	66	* for chassis v2.0, >= platform frequency / 2
	67	*/
	68	static u32 min_cpufreq;
	69	static const u32 *fmask;
	70
a4f20742 TY	71	#if defined(CONFIG_ARM)
	72	static int get_cpu_physical_id(int cpu)
	73	{
	74	return topology_core_id(cpu);
	75	}
	76	#else
	77	static int get_cpu_physical_id(int cpu)
	78	{
	79	return get_hard_smp_processor_id(cpu);
	80	}
	81	#endif
	82
	83	static u32 get_bus_freq(void)
	84	{
	85	struct device_node *soc;
	86	u32 sysfreq;
	87
	88	soc = of_find_node_by_type(NULL, "soc");
	89	if (!soc)
	90	return 0;
	91
	92	if (of_property_read_u32(soc, "bus-frequency", &sysfreq))
	93	sysfreq = 0;
	94
	95	of_node_put(soc);
defa4c73	96
a4f20742 TY	97	return sysfreq;
a4f20742 TY	98	}
defa4c73	99
a4f20742	100	static struct device_node *cpu_to_clk_node(int cpu)
defa4c73	101	{
a4f20742 TY	102	struct device_node np, clk_np;
	103
	104	if (!cpu_present(cpu))
	105	return NULL;
	106
	107	np = of_get_cpu_node(cpu, NULL);
	108	if (!np)
	109	return NULL;
	110
	111	clk_np = of_parse_phandle(np, "clocks", 0);
	112	if (!clk_np)
	113	return NULL;
	114
	115	of_node_put(np);
	116
	117	return clk_np;
	118	}
	119
	120	/* traverse cpu nodes to get cpu mask of sharing clock wire */
	121	static void set_affected_cpus(struct cpufreq_policy *policy)
	122	{
	123	struct device_node np, clk_np;
	124	struct cpumask *dstp = policy->cpus;
	125	int i;
	126
	127	np = cpu_to_clk_node(policy->cpu);
	128	if (!np)
	129	return;
	130
	131	for_each_present_cpu(i) {
	132	clk_np = cpu_to_clk_node(i);
	133	if (!clk_np)
	134	continue;
	135
	136	if (clk_np == np)
	137	cpumask_set_cpu(i, dstp);
	138
	139	of_node_put(clk_np);
	140	}
	141	of_node_put(np);
defa4c73	142	}
defa4c73	143
defa4c73 TY	144	/* reduce the duplicated frequencies in frequency table */
	145	static void freq_table_redup(struct cpufreq_frequency_table *freq_table,
	146	int count)
	147	{
	148	int i, j;
	149
	150	for (i = 1; i < count; i++) {
	151	for (j = 0; j < i; j++) {
	152	if (freq_table[j].frequency == CPUFREQ_ENTRY_INVALID \|\|
	153	freq_table[j].frequency !=
	154	freq_table[i].frequency)
	155	continue;
	156
	157	freq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
	158	break;
	159	}
	160	}
	161	}
	162
	163	/* sort the frequencies in frequency table in descenting order */
	164	static void freq_table_sort(struct cpufreq_frequency_table *freq_table,
	165	int count)
	166	{
	167	int i, j, ind;
	168	unsigned int freq, max_freq;
	169	struct cpufreq_frequency_table table;
a4f20742	170
defa4c73 TY	171	for (i = 0; i < count - 1; i++) {
	172	max_freq = freq_table[i].frequency;
	173	ind = i;
	174	for (j = i + 1; j < count; j++) {
	175	freq = freq_table[j].frequency;
	176	if (freq == CPUFREQ_ENTRY_INVALID \|\|
	177	freq <= max_freq)
	178	continue;
	179	ind = j;
	180	max_freq = freq;
	181	}
	182
	183	if (ind != i) {
	184	/* exchange the frequencies */
	185	table.driver_data = freq_table[i].driver_data;
	186	table.frequency = freq_table[i].frequency;
	187	freq_table[i].driver_data = freq_table[ind].driver_data;
	188	freq_table[i].frequency = freq_table[ind].frequency;
	189	freq_table[ind].driver_data = table.driver_data;
	190	freq_table[ind].frequency = table.frequency;
	191	}
	192	}
	193	}
	194
a4f20742	195	static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
defa4c73 TY	196	{
	197	struct device_node *np;
	198	int i, count, ret;
	199	u32 freq, mask;
	200	struct clk *clk;
	201	struct cpufreq_frequency_table *table;
	202	struct cpu_data *data;
	203	unsigned int cpu = policy->cpu;
906fe033	204	u64 u64temp;
defa4c73 TY	205
	206	np = of_get_cpu_node(cpu, NULL);
	207	if (!np)
	208	return -ENODEV;
	209
	210	data = kzalloc(sizeof(*data), GFP_KERNEL);
a4f20742	211	if (!data)
defa4c73	212	goto err_np;
defa4c73	213
652ed95d VK	214	policy->clk = of_clk_get(np, 0);
652ed95d VK	215	if (IS_ERR(policy->clk)) {
defa4c73 TY	216	pr_err("%s: no clock information\n", __func__);
	217	goto err_nomem2;
	218	}
	219
	220	data->parent = of_parse_phandle(np, "clocks", 0);
	221	if (!data->parent) {
	222	pr_err("%s: could not get clock information\n", __func__);
	223	goto err_nomem2;
	224	}
	225
	226	count = of_property_count_strings(data->parent, "clock-names");
	227	table = kcalloc(count + 1, sizeof(*table), GFP_KERNEL);
	228	if (!table) {
	229	pr_err("%s: no memory\n", __func__);
	230	goto err_node;
	231	}
	232
	233	if (fmask)
a4f20742	234	mask = fmask[get_cpu_physical_id(cpu)];
defa4c73 TY	235	else
	236	mask = 0x0;
	237
	238	for (i = 0; i < count; i++) {
	239	clk = of_clk_get(data->parent, i);
	240	freq = clk_get_rate(clk);
	241	/*
	242	* the clock is valid if its frequency is not masked
	243	* and large than minimum allowed frequency.
	244	*/
	245	if (freq < min_cpufreq \|\| (mask & (1 << i)))
	246	table[i].frequency = CPUFREQ_ENTRY_INVALID;
	247	else
	248	table[i].frequency = freq / 1000;
	249	table[i].driver_data = i;
	250	}
	251	freq_table_redup(table, count);
	252	freq_table_sort(table, count);
	253	table[i].frequency = CPUFREQ_TABLE_END;
	254
	255	/* set the min and max frequency properly */
6b4147db	256	ret = cpufreq_table_validate_and_show(policy, table);
defa4c73 TY	257	if (ret) {
	258	pr_err("invalid frequency table: %d\n", ret);
	259	goto err_nomem1;
	260	}
	261
	262	data->table = table;
defa4c73 TY	263
defa4c73 TY	264	/* update ->cpus if we have cluster, no harm if not */
a4f20742 TY	265	set_affected_cpus(policy);
a4f20742 TY	266	policy->driver_data = data;
defa4c73	267
906fe033 ES	268	/* Minimum transition latency is 12 platform clocks */
906fe033 ES	269	u64temp = 12ULL * NSEC_PER_SEC;
a4f20742	270	do_div(u64temp, get_bus_freq());
906fe033	271	policy->cpuinfo.transition_latency = u64temp + 1;
6712d293	272
defa4c73 TY	273	of_node_put(np);
	274
	275	return 0;
	276
	277	err_nomem1:
	278	kfree(table);
	279	err_node:
	280	of_node_put(data->parent);
	281	err_nomem2:
a4f20742	282	policy->driver_data = NULL;
defa4c73 TY	283	kfree(data);
	284	err_np:
	285	of_node_put(np);
	286
	287	return -ENODEV;
	288	}
	289
a4f20742	290	static int __exit qoriq_cpufreq_cpu_exit(struct cpufreq_policy *policy)
defa4c73	291	{
a4f20742	292	struct cpu_data *data = policy->driver_data;
defa4c73	293
defa4c73 TY	294	of_node_put(data->parent);
	295	kfree(data->table);
	296	kfree(data);
a4f20742	297	policy->driver_data = NULL;
defa4c73 TY	298
	299	return 0;
	300	}
	301
a4f20742	302	static int qoriq_cpufreq_target(struct cpufreq_policy *policy,
9c0ebcf7	303	unsigned int index)
defa4c73	304	{
defa4c73	305	struct clk *parent;
a4f20742	306	struct cpu_data *data = policy->driver_data;
defa4c73	307
9c0ebcf7	308	parent = of_clk_get(data->parent, data->table[index].driver_data);
652ed95d	309	return clk_set_parent(policy->clk, parent);
defa4c73 TY	310	}
defa4c73 TY	311
a4f20742 TY	312	static struct cpufreq_driver qoriq_cpufreq_driver = {
a4f20742 TY	313	.name = "qoriq_cpufreq",
defa4c73	314	.flags = CPUFREQ_CONST_LOOPS,
a4f20742 TY	315	.init = qoriq_cpufreq_cpu_init,
a4f20742 TY	316	.exit = __exit_p(qoriq_cpufreq_cpu_exit),
dc2398d7	317	.verify = cpufreq_generic_frequency_table_verify,
a4f20742	318	.target_index = qoriq_cpufreq_target,
652ed95d	319	.get = cpufreq_generic_get,
dc2398d7	320	.attr = cpufreq_generic_attr,
defa4c73 TY	321	};
defa4c73 TY	322
a4f20742	323	static const struct of_device_id node_matches[] __initconst = {
defa4c73 TY	324	{ .compatible = "fsl,p2041-clockgen", .data = &sdata[0], },
	325	{ .compatible = "fsl,p3041-clockgen", .data = &sdata[0], },
	326	{ .compatible = "fsl,p5020-clockgen", .data = &sdata[1], },
	327	{ .compatible = "fsl,p4080-clockgen", .data = &sdata[2], },
	328	{ .compatible = "fsl,p5040-clockgen", .data = &sdata[2], },
	329	{ .compatible = "fsl,qoriq-clockgen-2.0", },
	330	{}
	331	};
	332
a4f20742	333	static int __init qoriq_cpufreq_init(void)
defa4c73 TY	334	{
	335	int ret;
	336	struct device_node *np;
	337	const struct of_device_id *match;
	338	const struct soc_data *data;
defa4c73 TY	339
	340	np = of_find_matching_node(NULL, node_matches);
	341	if (!np)
	342	return -ENODEV;
	343
defa4c73 TY	344	match = of_match_node(node_matches, np);
	345	data = match->data;
	346	if (data) {
	347	if (data->flag)
	348	fmask = data->freq_mask;
a4f20742	349	min_cpufreq = get_bus_freq();
defa4c73	350	} else {
a4f20742	351	min_cpufreq = get_bus_freq() / 2;
defa4c73 TY	352	}
	353
	354	of_node_put(np);
	355
a4f20742	356	ret = cpufreq_register_driver(&qoriq_cpufreq_driver);
defa4c73	357	if (!ret)
a4f20742	358	pr_info("Freescale QorIQ CPU frequency scaling driver\n");
defa4c73 TY	359
defa4c73 TY	360	return ret;
defa4c73	361	}
a4f20742	362	module_init(qoriq_cpufreq_init);
defa4c73	363
a4f20742	364	static void __exit qoriq_cpufreq_exit(void)
defa4c73	365	{
a4f20742	366	cpufreq_unregister_driver(&qoriq_cpufreq_driver);
defa4c73	367	}
a4f20742	368	module_exit(qoriq_cpufreq_exit);
defa4c73 TY	369
	370	MODULE_LICENSE("GPL");
	371	MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
a4f20742	372	MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs");