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34ee5507 HS |
1 | /* |
2 | * S3C2416/2450 CPUfreq Support | |
3 | * | |
4 | * Copyright 2011 Heiko Stuebner <heiko@sntech.de> | |
5 | * | |
6 | * based on s3c64xx_cpufreq.c | |
7 | * | |
8 | * Copyright 2009 Wolfson Microelectronics plc | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/types.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/cpufreq.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/regulator/consumer.h> | |
22 | #include <linux/reboot.h> | |
23 | #include <linux/module.h> | |
24 | ||
25 | static DEFINE_MUTEX(cpufreq_lock); | |
26 | ||
27 | struct s3c2416_data { | |
28 | struct clk *armdiv; | |
29 | struct clk *armclk; | |
30 | struct clk *hclk; | |
31 | ||
32 | unsigned long regulator_latency; | |
33 | #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE | |
34 | struct regulator *vddarm; | |
35 | #endif | |
36 | ||
37 | struct cpufreq_frequency_table *freq_table; | |
38 | ||
39 | bool is_dvs; | |
40 | bool disable_dvs; | |
41 | }; | |
42 | ||
43 | static struct s3c2416_data s3c2416_cpufreq; | |
44 | ||
45 | struct s3c2416_dvfs { | |
46 | unsigned int vddarm_min; | |
47 | unsigned int vddarm_max; | |
48 | }; | |
49 | ||
50 | /* pseudo-frequency for dvs mode */ | |
51 | #define FREQ_DVS 132333 | |
52 | ||
53 | /* frequency to sleep and reboot in | |
54 | * it's essential to leave dvs, as some boards do not reconfigure the | |
55 | * regulator on reboot | |
56 | */ | |
57 | #define FREQ_SLEEP 133333 | |
58 | ||
59 | /* Sources for the ARMCLK */ | |
60 | #define SOURCE_HCLK 0 | |
61 | #define SOURCE_ARMDIV 1 | |
62 | ||
63 | #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE | |
64 | /* S3C2416 only supports changing the voltage in the dvs-mode. | |
65 | * Voltages down to 1.0V seem to work, so we take what the regulator | |
66 | * can get us. | |
67 | */ | |
68 | static struct s3c2416_dvfs s3c2416_dvfs_table[] = { | |
69 | [SOURCE_HCLK] = { 950000, 1250000 }, | |
70 | [SOURCE_ARMDIV] = { 1250000, 1350000 }, | |
71 | }; | |
72 | #endif | |
73 | ||
74 | static struct cpufreq_frequency_table s3c2416_freq_table[] = { | |
75 | { SOURCE_HCLK, FREQ_DVS }, | |
76 | { SOURCE_ARMDIV, 133333 }, | |
77 | { SOURCE_ARMDIV, 266666 }, | |
78 | { SOURCE_ARMDIV, 400000 }, | |
79 | { 0, CPUFREQ_TABLE_END }, | |
80 | }; | |
81 | ||
82 | static struct cpufreq_frequency_table s3c2450_freq_table[] = { | |
83 | { SOURCE_HCLK, FREQ_DVS }, | |
84 | { SOURCE_ARMDIV, 133500 }, | |
85 | { SOURCE_ARMDIV, 267000 }, | |
86 | { SOURCE_ARMDIV, 534000 }, | |
87 | { 0, CPUFREQ_TABLE_END }, | |
88 | }; | |
89 | ||
34ee5507 HS |
90 | static unsigned int s3c2416_cpufreq_get_speed(unsigned int cpu) |
91 | { | |
92 | struct s3c2416_data *s3c_freq = &s3c2416_cpufreq; | |
93 | ||
94 | if (cpu != 0) | |
95 | return 0; | |
96 | ||
97 | /* return our pseudo-frequency when in dvs mode */ | |
98 | if (s3c_freq->is_dvs) | |
99 | return FREQ_DVS; | |
100 | ||
101 | return clk_get_rate(s3c_freq->armclk) / 1000; | |
102 | } | |
103 | ||
104 | static int s3c2416_cpufreq_set_armdiv(struct s3c2416_data *s3c_freq, | |
105 | unsigned int freq) | |
106 | { | |
107 | int ret; | |
108 | ||
109 | if (clk_get_rate(s3c_freq->armdiv) / 1000 != freq) { | |
110 | ret = clk_set_rate(s3c_freq->armdiv, freq * 1000); | |
111 | if (ret < 0) { | |
112 | pr_err("cpufreq: Failed to set armdiv rate %dkHz: %d\n", | |
113 | freq, ret); | |
114 | return ret; | |
115 | } | |
116 | } | |
117 | ||
118 | return 0; | |
119 | } | |
120 | ||
121 | static int s3c2416_cpufreq_enter_dvs(struct s3c2416_data *s3c_freq, int idx) | |
122 | { | |
123 | #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE | |
124 | struct s3c2416_dvfs *dvfs; | |
125 | #endif | |
126 | int ret; | |
127 | ||
128 | if (s3c_freq->is_dvs) { | |
129 | pr_debug("cpufreq: already in dvs mode, nothing to do\n"); | |
130 | return 0; | |
131 | } | |
132 | ||
133 | pr_debug("cpufreq: switching armclk to hclk (%lukHz)\n", | |
134 | clk_get_rate(s3c_freq->hclk) / 1000); | |
135 | ret = clk_set_parent(s3c_freq->armclk, s3c_freq->hclk); | |
136 | if (ret < 0) { | |
137 | pr_err("cpufreq: Failed to switch armclk to hclk: %d\n", ret); | |
138 | return ret; | |
139 | } | |
140 | ||
141 | #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE | |
142 | /* changing the core voltage is only allowed when in dvs mode */ | |
143 | if (s3c_freq->vddarm) { | |
144 | dvfs = &s3c2416_dvfs_table[idx]; | |
145 | ||
c03c3013 | 146 | pr_debug("cpufreq: setting regulator to %d-%d\n", |
34ee5507 HS |
147 | dvfs->vddarm_min, dvfs->vddarm_max); |
148 | ret = regulator_set_voltage(s3c_freq->vddarm, | |
149 | dvfs->vddarm_min, | |
150 | dvfs->vddarm_max); | |
151 | ||
152 | /* when lowering the voltage failed, there is nothing to do */ | |
153 | if (ret != 0) | |
154 | pr_err("cpufreq: Failed to set VDDARM: %d\n", ret); | |
155 | } | |
156 | #endif | |
157 | ||
158 | s3c_freq->is_dvs = 1; | |
159 | ||
160 | return 0; | |
161 | } | |
162 | ||
163 | static int s3c2416_cpufreq_leave_dvs(struct s3c2416_data *s3c_freq, int idx) | |
164 | { | |
165 | #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE | |
166 | struct s3c2416_dvfs *dvfs; | |
167 | #endif | |
168 | int ret; | |
169 | ||
170 | if (!s3c_freq->is_dvs) { | |
171 | pr_debug("cpufreq: not in dvs mode, so can't leave\n"); | |
172 | return 0; | |
173 | } | |
174 | ||
175 | #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE | |
176 | if (s3c_freq->vddarm) { | |
177 | dvfs = &s3c2416_dvfs_table[idx]; | |
178 | ||
c03c3013 | 179 | pr_debug("cpufreq: setting regulator to %d-%d\n", |
34ee5507 HS |
180 | dvfs->vddarm_min, dvfs->vddarm_max); |
181 | ret = regulator_set_voltage(s3c_freq->vddarm, | |
182 | dvfs->vddarm_min, | |
183 | dvfs->vddarm_max); | |
184 | if (ret != 0) { | |
185 | pr_err("cpufreq: Failed to set VDDARM: %d\n", ret); | |
186 | return ret; | |
187 | } | |
188 | } | |
189 | #endif | |
190 | ||
191 | /* force armdiv to hclk frequency for transition from dvs*/ | |
192 | if (clk_get_rate(s3c_freq->armdiv) > clk_get_rate(s3c_freq->hclk)) { | |
193 | pr_debug("cpufreq: force armdiv to hclk frequency (%lukHz)\n", | |
194 | clk_get_rate(s3c_freq->hclk) / 1000); | |
195 | ret = s3c2416_cpufreq_set_armdiv(s3c_freq, | |
196 | clk_get_rate(s3c_freq->hclk) / 1000); | |
197 | if (ret < 0) { | |
278cee05 | 198 | pr_err("cpufreq: Failed to set the armdiv to %lukHz: %d\n", |
34ee5507 HS |
199 | clk_get_rate(s3c_freq->hclk) / 1000, ret); |
200 | return ret; | |
201 | } | |
202 | } | |
203 | ||
204 | pr_debug("cpufreq: switching armclk parent to armdiv (%lukHz)\n", | |
205 | clk_get_rate(s3c_freq->armdiv) / 1000); | |
206 | ||
207 | ret = clk_set_parent(s3c_freq->armclk, s3c_freq->armdiv); | |
208 | if (ret < 0) { | |
209 | pr_err("cpufreq: Failed to switch armclk clock parent to armdiv: %d\n", | |
210 | ret); | |
211 | return ret; | |
212 | } | |
213 | ||
214 | s3c_freq->is_dvs = 0; | |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
219 | static int s3c2416_cpufreq_set_target(struct cpufreq_policy *policy, | |
9c0ebcf7 | 220 | unsigned int index) |
34ee5507 HS |
221 | { |
222 | struct s3c2416_data *s3c_freq = &s3c2416_cpufreq; | |
223 | struct cpufreq_freqs freqs; | |
224 | int idx, ret, to_dvs = 0; | |
34ee5507 HS |
225 | |
226 | mutex_lock(&cpufreq_lock); | |
227 | ||
9c0ebcf7 | 228 | idx = s3c_freq->freq_table[index].driver_data; |
34ee5507 HS |
229 | |
230 | if (idx == SOURCE_HCLK) | |
231 | to_dvs = 1; | |
232 | ||
233 | /* switching to dvs when it's not allowed */ | |
234 | if (to_dvs && s3c_freq->disable_dvs) { | |
235 | pr_debug("cpufreq: entering dvs mode not allowed\n"); | |
236 | ret = -EINVAL; | |
237 | goto out; | |
238 | } | |
239 | ||
34ee5507 HS |
240 | freqs.flags = 0; |
241 | freqs.old = s3c_freq->is_dvs ? FREQ_DVS | |
242 | : clk_get_rate(s3c_freq->armclk) / 1000; | |
243 | ||
244 | /* When leavin dvs mode, always switch the armdiv to the hclk rate | |
245 | * The S3C2416 has stability issues when switching directly to | |
246 | * higher frequencies. | |
247 | */ | |
248 | freqs.new = (s3c_freq->is_dvs && !to_dvs) | |
249 | ? clk_get_rate(s3c_freq->hclk) / 1000 | |
9c0ebcf7 | 250 | : s3c_freq->freq_table[index].frequency; |
34ee5507 HS |
251 | |
252 | pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new); | |
253 | ||
254 | if (!to_dvs && freqs.old == freqs.new) | |
255 | goto out; | |
256 | ||
b43a7ffb | 257 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); |
34ee5507 HS |
258 | |
259 | if (to_dvs) { | |
260 | pr_debug("cpufreq: enter dvs\n"); | |
261 | ret = s3c2416_cpufreq_enter_dvs(s3c_freq, idx); | |
262 | } else if (s3c_freq->is_dvs) { | |
263 | pr_debug("cpufreq: leave dvs\n"); | |
264 | ret = s3c2416_cpufreq_leave_dvs(s3c_freq, idx); | |
265 | } else { | |
266 | pr_debug("cpufreq: change armdiv to %dkHz\n", freqs.new); | |
267 | ret = s3c2416_cpufreq_set_armdiv(s3c_freq, freqs.new); | |
268 | } | |
269 | ||
b43a7ffb | 270 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE); |
34ee5507 HS |
271 | |
272 | out: | |
273 | mutex_unlock(&cpufreq_lock); | |
274 | ||
275 | return ret; | |
276 | } | |
277 | ||
278 | #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE | |
279 | static void __init s3c2416_cpufreq_cfg_regulator(struct s3c2416_data *s3c_freq) | |
280 | { | |
281 | int count, v, i, found; | |
282 | struct cpufreq_frequency_table *freq; | |
283 | struct s3c2416_dvfs *dvfs; | |
284 | ||
285 | count = regulator_count_voltages(s3c_freq->vddarm); | |
286 | if (count < 0) { | |
287 | pr_err("cpufreq: Unable to check supported voltages\n"); | |
288 | return; | |
289 | } | |
290 | ||
291 | freq = s3c_freq->freq_table; | |
292 | while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) { | |
293 | if (freq->frequency == CPUFREQ_ENTRY_INVALID) | |
294 | continue; | |
295 | ||
166b9add | 296 | dvfs = &s3c2416_dvfs_table[freq->driver_data]; |
34ee5507 HS |
297 | found = 0; |
298 | ||
299 | /* Check only the min-voltage, more is always ok on S3C2416 */ | |
300 | for (i = 0; i < count; i++) { | |
301 | v = regulator_list_voltage(s3c_freq->vddarm, i); | |
302 | if (v >= dvfs->vddarm_min) | |
303 | found = 1; | |
304 | } | |
305 | ||
306 | if (!found) { | |
307 | pr_debug("cpufreq: %dkHz unsupported by regulator\n", | |
308 | freq->frequency); | |
309 | freq->frequency = CPUFREQ_ENTRY_INVALID; | |
310 | } | |
311 | ||
312 | freq++; | |
313 | } | |
314 | ||
315 | /* Guessed */ | |
316 | s3c_freq->regulator_latency = 1 * 1000 * 1000; | |
317 | } | |
318 | #endif | |
319 | ||
320 | static int s3c2416_cpufreq_reboot_notifier_evt(struct notifier_block *this, | |
321 | unsigned long event, void *ptr) | |
322 | { | |
323 | struct s3c2416_data *s3c_freq = &s3c2416_cpufreq; | |
324 | int ret; | |
325 | ||
326 | mutex_lock(&cpufreq_lock); | |
327 | ||
328 | /* disable further changes */ | |
329 | s3c_freq->disable_dvs = 1; | |
330 | ||
331 | mutex_unlock(&cpufreq_lock); | |
332 | ||
333 | /* some boards don't reconfigure the regulator on reboot, which | |
334 | * could lead to undervolting the cpu when the clock is reset. | |
335 | * Therefore we always leave the DVS mode on reboot. | |
336 | */ | |
337 | if (s3c_freq->is_dvs) { | |
338 | pr_debug("cpufreq: leave dvs on reboot\n"); | |
339 | ret = cpufreq_driver_target(cpufreq_cpu_get(0), FREQ_SLEEP, 0); | |
340 | if (ret < 0) | |
341 | return NOTIFY_BAD; | |
342 | } | |
343 | ||
344 | return NOTIFY_DONE; | |
345 | } | |
346 | ||
347 | static struct notifier_block s3c2416_cpufreq_reboot_notifier = { | |
348 | .notifier_call = s3c2416_cpufreq_reboot_notifier_evt, | |
349 | }; | |
350 | ||
351 | static int __init s3c2416_cpufreq_driver_init(struct cpufreq_policy *policy) | |
352 | { | |
353 | struct s3c2416_data *s3c_freq = &s3c2416_cpufreq; | |
354 | struct cpufreq_frequency_table *freq; | |
355 | struct clk *msysclk; | |
356 | unsigned long rate; | |
357 | int ret; | |
358 | ||
359 | if (policy->cpu != 0) | |
360 | return -EINVAL; | |
361 | ||
362 | msysclk = clk_get(NULL, "msysclk"); | |
363 | if (IS_ERR(msysclk)) { | |
364 | ret = PTR_ERR(msysclk); | |
365 | pr_err("cpufreq: Unable to obtain msysclk: %d\n", ret); | |
366 | return ret; | |
367 | } | |
368 | ||
369 | /* | |
370 | * S3C2416 and S3C2450 share the same processor-ID and also provide no | |
371 | * other means to distinguish them other than through the rate of | |
372 | * msysclk. On S3C2416 msysclk runs at 800MHz and on S3C2450 at 533MHz. | |
373 | */ | |
374 | rate = clk_get_rate(msysclk); | |
375 | if (rate == 800 * 1000 * 1000) { | |
376 | pr_info("cpufreq: msysclk running at %lukHz, using S3C2416 frequency table\n", | |
377 | rate / 1000); | |
378 | s3c_freq->freq_table = s3c2416_freq_table; | |
379 | policy->cpuinfo.max_freq = 400000; | |
380 | } else if (rate / 1000 == 534000) { | |
381 | pr_info("cpufreq: msysclk running at %lukHz, using S3C2450 frequency table\n", | |
382 | rate / 1000); | |
383 | s3c_freq->freq_table = s3c2450_freq_table; | |
384 | policy->cpuinfo.max_freq = 534000; | |
385 | } | |
386 | ||
387 | /* not needed anymore */ | |
388 | clk_put(msysclk); | |
389 | ||
390 | if (s3c_freq->freq_table == NULL) { | |
391 | pr_err("cpufreq: No frequency information for this CPU, msysclk at %lukHz\n", | |
392 | rate / 1000); | |
393 | return -ENODEV; | |
394 | } | |
395 | ||
396 | s3c_freq->is_dvs = 0; | |
397 | ||
398 | s3c_freq->armdiv = clk_get(NULL, "armdiv"); | |
399 | if (IS_ERR(s3c_freq->armdiv)) { | |
400 | ret = PTR_ERR(s3c_freq->armdiv); | |
401 | pr_err("cpufreq: Unable to obtain ARMDIV: %d\n", ret); | |
402 | return ret; | |
403 | } | |
404 | ||
405 | s3c_freq->hclk = clk_get(NULL, "hclk"); | |
406 | if (IS_ERR(s3c_freq->hclk)) { | |
407 | ret = PTR_ERR(s3c_freq->hclk); | |
408 | pr_err("cpufreq: Unable to obtain HCLK: %d\n", ret); | |
409 | goto err_hclk; | |
410 | } | |
411 | ||
412 | /* chech hclk rate, we only support the common 133MHz for now | |
413 | * hclk could also run at 66MHz, but this not often used | |
414 | */ | |
415 | rate = clk_get_rate(s3c_freq->hclk); | |
416 | if (rate < 133 * 1000 * 1000) { | |
417 | pr_err("cpufreq: HCLK not at 133MHz\n"); | |
418 | clk_put(s3c_freq->hclk); | |
419 | ret = -EINVAL; | |
420 | goto err_armclk; | |
421 | } | |
422 | ||
423 | s3c_freq->armclk = clk_get(NULL, "armclk"); | |
424 | if (IS_ERR(s3c_freq->armclk)) { | |
425 | ret = PTR_ERR(s3c_freq->armclk); | |
426 | pr_err("cpufreq: Unable to obtain ARMCLK: %d\n", ret); | |
427 | goto err_armclk; | |
428 | } | |
429 | ||
430 | #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE | |
431 | s3c_freq->vddarm = regulator_get(NULL, "vddarm"); | |
432 | if (IS_ERR(s3c_freq->vddarm)) { | |
433 | ret = PTR_ERR(s3c_freq->vddarm); | |
434 | pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret); | |
435 | goto err_vddarm; | |
436 | } | |
437 | ||
438 | s3c2416_cpufreq_cfg_regulator(s3c_freq); | |
439 | #else | |
440 | s3c_freq->regulator_latency = 0; | |
441 | #endif | |
442 | ||
443 | freq = s3c_freq->freq_table; | |
444 | while (freq->frequency != CPUFREQ_TABLE_END) { | |
445 | /* special handling for dvs mode */ | |
166b9add | 446 | if (freq->driver_data == 0) { |
34ee5507 HS |
447 | if (!s3c_freq->hclk) { |
448 | pr_debug("cpufreq: %dkHz unsupported as it would need unavailable dvs mode\n", | |
449 | freq->frequency); | |
450 | freq->frequency = CPUFREQ_ENTRY_INVALID; | |
451 | } else { | |
452 | freq++; | |
453 | continue; | |
454 | } | |
455 | } | |
456 | ||
457 | /* Check for frequencies we can generate */ | |
458 | rate = clk_round_rate(s3c_freq->armdiv, | |
459 | freq->frequency * 1000); | |
460 | rate /= 1000; | |
461 | if (rate != freq->frequency) { | |
462 | pr_debug("cpufreq: %dkHz unsupported by clock (clk_round_rate return %lu)\n", | |
463 | freq->frequency, rate); | |
464 | freq->frequency = CPUFREQ_ENTRY_INVALID; | |
465 | } | |
466 | ||
467 | freq++; | |
468 | } | |
469 | ||
34ee5507 HS |
470 | /* Datasheet says PLL stabalisation time must be at least 300us, |
471 | * so but add some fudge. (reference in LOCKCON0 register description) | |
472 | */ | |
a307a1e6 VK |
473 | ret = cpufreq_generic_init(policy, s3c_freq->freq_table, |
474 | (500 * 1000) + s3c_freq->regulator_latency); | |
34ee5507 HS |
475 | if (ret) |
476 | goto err_freq_table; | |
477 | ||
34ee5507 HS |
478 | register_reboot_notifier(&s3c2416_cpufreq_reboot_notifier); |
479 | ||
480 | return 0; | |
481 | ||
482 | err_freq_table: | |
483 | #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE | |
484 | regulator_put(s3c_freq->vddarm); | |
485 | err_vddarm: | |
486 | #endif | |
487 | clk_put(s3c_freq->armclk); | |
488 | err_armclk: | |
489 | clk_put(s3c_freq->hclk); | |
490 | err_hclk: | |
491 | clk_put(s3c_freq->armdiv); | |
492 | ||
493 | return ret; | |
494 | } | |
495 | ||
34ee5507 | 496 | static struct cpufreq_driver s3c2416_cpufreq_driver = { |
34ee5507 | 497 | .flags = 0, |
e96a4105 | 498 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 499 | .target_index = s3c2416_cpufreq_set_target, |
34ee5507 HS |
500 | .get = s3c2416_cpufreq_get_speed, |
501 | .init = s3c2416_cpufreq_driver_init, | |
502 | .name = "s3c2416", | |
e96a4105 | 503 | .attr = cpufreq_generic_attr, |
34ee5507 HS |
504 | }; |
505 | ||
506 | static int __init s3c2416_cpufreq_init(void) | |
507 | { | |
508 | return cpufreq_register_driver(&s3c2416_cpufreq_driver); | |
509 | } | |
510 | module_init(s3c2416_cpufreq_init); |