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09ec1d7e | 1 | /* |
e02f8664 | 2 | * Copyright (c) 2006-2008 Simtec Electronics |
2e4ea6e8 BD |
3 | * http://armlinux.simtec.co.uk/ |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C24XX CPU Frequency scaling | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/ioport.h> | |
17 | #include <linux/cpufreq.h> | |
18 | #include <linux/cpu.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/io.h> | |
edbaa603 | 22 | #include <linux/device.h> |
2e4ea6e8 | 23 | #include <linux/sysfs.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
2e4ea6e8 BD |
25 | |
26 | #include <asm/mach/arch.h> | |
27 | #include <asm/mach/map.h> | |
28 | ||
29 | #include <plat/cpu.h> | |
2e4ea6e8 BD |
30 | #include <plat/cpu-freq-core.h> |
31 | ||
32 | #include <mach/regs-clock.h> | |
33 | ||
34 | /* note, cpufreq support deals in kHz, no Hz */ | |
35 | ||
36 | static struct cpufreq_driver s3c24xx_driver; | |
37 | static struct s3c_cpufreq_config cpu_cur; | |
38 | static struct s3c_iotimings s3c24xx_iotiming; | |
39 | static struct cpufreq_frequency_table *pll_reg; | |
40 | static unsigned int last_target = ~0; | |
41 | static unsigned int ftab_size; | |
42 | static struct cpufreq_frequency_table *ftab; | |
43 | ||
44 | static struct clk *_clk_mpll; | |
45 | static struct clk *_clk_xtal; | |
46 | static struct clk *clk_fclk; | |
47 | static struct clk *clk_hclk; | |
48 | static struct clk *clk_pclk; | |
49 | static struct clk *clk_arm; | |
50 | ||
4a6c4108 | 51 | #ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS |
e6d197a6 BD |
52 | struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void) |
53 | { | |
54 | return &cpu_cur; | |
55 | } | |
56 | ||
57 | struct s3c_iotimings *s3c_cpufreq_getiotimings(void) | |
58 | { | |
59 | return &s3c24xx_iotiming; | |
60 | } | |
4a6c4108 | 61 | #endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS */ |
e6d197a6 | 62 | |
2e4ea6e8 BD |
63 | static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg) |
64 | { | |
65 | unsigned long fclk, pclk, hclk, armclk; | |
66 | ||
67 | cfg->freq.fclk = fclk = clk_get_rate(clk_fclk); | |
68 | cfg->freq.hclk = hclk = clk_get_rate(clk_hclk); | |
69 | cfg->freq.pclk = pclk = clk_get_rate(clk_pclk); | |
70 | cfg->freq.armclk = armclk = clk_get_rate(clk_arm); | |
71 | ||
50701588 | 72 | cfg->pll.driver_data = __raw_readl(S3C2410_MPLLCON); |
2e4ea6e8 BD |
73 | cfg->pll.frequency = fclk; |
74 | ||
75 | cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); | |
76 | ||
77 | cfg->divs.h_divisor = fclk / hclk; | |
78 | cfg->divs.p_divisor = fclk / pclk; | |
79 | } | |
80 | ||
81 | static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg) | |
82 | { | |
83 | unsigned long pll = cfg->pll.frequency; | |
84 | ||
85 | cfg->freq.fclk = pll; | |
86 | cfg->freq.hclk = pll / cfg->divs.h_divisor; | |
87 | cfg->freq.pclk = pll / cfg->divs.p_divisor; | |
88 | ||
89 | /* convert hclk into 10ths of nanoseconds for io calcs */ | |
90 | cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); | |
91 | } | |
92 | ||
93 | static inline int closer(unsigned int target, unsigned int n, unsigned int c) | |
94 | { | |
95 | int diff_cur = abs(target - c); | |
96 | int diff_new = abs(target - n); | |
97 | ||
98 | return (diff_new < diff_cur); | |
99 | } | |
100 | ||
101 | static void s3c_cpufreq_show(const char *pfx, | |
102 | struct s3c_cpufreq_config *cfg) | |
103 | { | |
104 | s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n", | |
105 | pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk, | |
106 | cfg->freq.hclk, cfg->divs.h_divisor, | |
107 | cfg->freq.pclk, cfg->divs.p_divisor); | |
108 | } | |
109 | ||
110 | /* functions to wrapper the driver info calls to do the cpu specific work */ | |
111 | ||
112 | static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg) | |
113 | { | |
114 | if (cfg->info->set_iotiming) | |
115 | (cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming); | |
116 | } | |
117 | ||
118 | static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg) | |
119 | { | |
120 | if (cfg->info->calc_iotiming) | |
121 | return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming); | |
122 | ||
123 | return 0; | |
124 | } | |
125 | ||
126 | static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) | |
127 | { | |
128 | (cfg->info->set_refresh)(cfg); | |
129 | } | |
130 | ||
131 | static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) | |
132 | { | |
133 | (cfg->info->set_divs)(cfg); | |
134 | } | |
135 | ||
136 | static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) | |
137 | { | |
138 | return (cfg->info->calc_divs)(cfg); | |
139 | } | |
140 | ||
141 | static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg) | |
142 | { | |
d8b53257 | 143 | cfg->mpll = _clk_mpll; |
2e4ea6e8 BD |
144 | (cfg->info->set_fvco)(cfg); |
145 | } | |
146 | ||
2e4ea6e8 BD |
147 | static inline void s3c_cpufreq_updateclk(struct clk *clk, |
148 | unsigned int freq) | |
149 | { | |
150 | clk_set_rate(clk, freq); | |
151 | } | |
152 | ||
153 | static int s3c_cpufreq_settarget(struct cpufreq_policy *policy, | |
154 | unsigned int target_freq, | |
155 | struct cpufreq_frequency_table *pll) | |
156 | { | |
157 | struct s3c_cpufreq_freqs freqs; | |
158 | struct s3c_cpufreq_config cpu_new; | |
159 | unsigned long flags; | |
160 | ||
161 | cpu_new = cpu_cur; /* copy new from current */ | |
162 | ||
163 | s3c_cpufreq_show("cur", &cpu_cur); | |
164 | ||
165 | /* TODO - check for DMA currently outstanding */ | |
166 | ||
167 | cpu_new.pll = pll ? *pll : cpu_cur.pll; | |
168 | ||
169 | if (pll) | |
170 | freqs.pll_changing = 1; | |
171 | ||
172 | /* update our frequencies */ | |
173 | ||
174 | cpu_new.freq.armclk = target_freq; | |
175 | cpu_new.freq.fclk = cpu_new.pll.frequency; | |
176 | ||
177 | if (s3c_cpufreq_calcdivs(&cpu_new) < 0) { | |
178 | printk(KERN_ERR "no divisors for %d\n", target_freq); | |
179 | goto err_notpossible; | |
180 | } | |
181 | ||
182 | s3c_freq_dbg("%s: got divs\n", __func__); | |
183 | ||
184 | s3c_cpufreq_calc(&cpu_new); | |
185 | ||
186 | s3c_freq_dbg("%s: calculated frequencies for new\n", __func__); | |
187 | ||
188 | if (cpu_new.freq.hclk != cpu_cur.freq.hclk) { | |
189 | if (s3c_cpufreq_calcio(&cpu_new) < 0) { | |
190 | printk(KERN_ERR "%s: no IO timings\n", __func__); | |
191 | goto err_notpossible; | |
192 | } | |
193 | } | |
194 | ||
195 | s3c_cpufreq_show("new", &cpu_new); | |
196 | ||
197 | /* setup our cpufreq parameters */ | |
198 | ||
199 | freqs.old = cpu_cur.freq; | |
200 | freqs.new = cpu_new.freq; | |
201 | ||
2e4ea6e8 BD |
202 | freqs.freqs.old = cpu_cur.freq.armclk / 1000; |
203 | freqs.freqs.new = cpu_new.freq.armclk / 1000; | |
204 | ||
205 | /* update f/h/p clock settings before we issue the change | |
206 | * notification, so that drivers do not need to do anything | |
207 | * special if they want to recalculate on CPUFREQ_PRECHANGE. */ | |
208 | ||
209 | s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency); | |
210 | s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk); | |
211 | s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk); | |
212 | s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk); | |
213 | ||
214 | /* start the frequency change */ | |
8fec051e | 215 | cpufreq_freq_transition_begin(policy, &freqs.freqs); |
2e4ea6e8 BD |
216 | |
217 | /* If hclk is staying the same, then we do not need to | |
218 | * re-write the IO or the refresh timings whilst we are changing | |
219 | * speed. */ | |
220 | ||
221 | local_irq_save(flags); | |
222 | ||
223 | /* is our memory clock slowing down? */ | |
224 | if (cpu_new.freq.hclk < cpu_cur.freq.hclk) { | |
225 | s3c_cpufreq_setrefresh(&cpu_new); | |
226 | s3c_cpufreq_setio(&cpu_new); | |
227 | } | |
228 | ||
229 | if (cpu_new.freq.fclk == cpu_cur.freq.fclk) { | |
230 | /* not changing PLL, just set the divisors */ | |
231 | ||
232 | s3c_cpufreq_setdivs(&cpu_new); | |
233 | } else { | |
234 | if (cpu_new.freq.fclk < cpu_cur.freq.fclk) { | |
235 | /* slow the cpu down, then set divisors */ | |
236 | ||
237 | s3c_cpufreq_setfvco(&cpu_new); | |
238 | s3c_cpufreq_setdivs(&cpu_new); | |
239 | } else { | |
240 | /* set the divisors, then speed up */ | |
241 | ||
242 | s3c_cpufreq_setdivs(&cpu_new); | |
243 | s3c_cpufreq_setfvco(&cpu_new); | |
244 | } | |
245 | } | |
246 | ||
247 | /* did our memory clock speed up */ | |
248 | if (cpu_new.freq.hclk > cpu_cur.freq.hclk) { | |
249 | s3c_cpufreq_setrefresh(&cpu_new); | |
250 | s3c_cpufreq_setio(&cpu_new); | |
251 | } | |
252 | ||
253 | /* update our current settings */ | |
254 | cpu_cur = cpu_new; | |
255 | ||
256 | local_irq_restore(flags); | |
257 | ||
258 | /* notify everyone we've done this */ | |
8fec051e | 259 | cpufreq_freq_transition_end(policy, &freqs.freqs, 0); |
2e4ea6e8 BD |
260 | |
261 | s3c_freq_dbg("%s: finished\n", __func__); | |
262 | return 0; | |
263 | ||
264 | err_notpossible: | |
265 | printk(KERN_ERR "no compatible settings for %d\n", target_freq); | |
266 | return -EINVAL; | |
267 | } | |
268 | ||
269 | /* s3c_cpufreq_target | |
270 | * | |
271 | * called by the cpufreq core to adjust the frequency that the CPU | |
272 | * is currently running at. | |
273 | */ | |
274 | ||
275 | static int s3c_cpufreq_target(struct cpufreq_policy *policy, | |
276 | unsigned int target_freq, | |
277 | unsigned int relation) | |
278 | { | |
279 | struct cpufreq_frequency_table *pll; | |
280 | unsigned int index; | |
281 | ||
282 | /* avoid repeated calls which cause a needless amout of duplicated | |
283 | * logging output (and CPU time as the calculation process is | |
284 | * done) */ | |
285 | if (target_freq == last_target) | |
286 | return 0; | |
287 | ||
288 | last_target = target_freq; | |
289 | ||
290 | s3c_freq_dbg("%s: policy %p, target %u, relation %u\n", | |
291 | __func__, policy, target_freq, relation); | |
292 | ||
293 | if (ftab) { | |
294 | if (cpufreq_frequency_table_target(policy, ftab, | |
295 | target_freq, relation, | |
296 | &index)) { | |
297 | s3c_freq_dbg("%s: table failed\n", __func__); | |
298 | return -EINVAL; | |
299 | } | |
300 | ||
301 | s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__, | |
302 | target_freq, index, ftab[index].frequency); | |
303 | target_freq = ftab[index].frequency; | |
304 | } | |
305 | ||
306 | target_freq *= 1000; /* convert target to Hz */ | |
307 | ||
308 | /* find the settings for our new frequency */ | |
309 | ||
310 | if (!pll_reg || cpu_cur.lock_pll) { | |
311 | /* either we've not got any PLL values, or we've locked | |
312 | * to the current one. */ | |
313 | pll = NULL; | |
314 | } else { | |
315 | struct cpufreq_policy tmp_policy; | |
316 | int ret; | |
317 | ||
318 | /* we keep the cpu pll table in Hz, to ensure we get an | |
319 | * accurate value for the PLL output. */ | |
320 | ||
321 | tmp_policy.min = policy->min * 1000; | |
322 | tmp_policy.max = policy->max * 1000; | |
323 | tmp_policy.cpu = policy->cpu; | |
324 | ||
325 | /* cpufreq_frequency_table_target uses a pointer to 'index' | |
326 | * which is the number of the table entry, not the value of | |
327 | * the table entry's index field. */ | |
328 | ||
329 | ret = cpufreq_frequency_table_target(&tmp_policy, pll_reg, | |
330 | target_freq, relation, | |
331 | &index); | |
332 | ||
333 | if (ret < 0) { | |
334 | printk(KERN_ERR "%s: no PLL available\n", __func__); | |
335 | goto err_notpossible; | |
336 | } | |
337 | ||
338 | pll = pll_reg + index; | |
339 | ||
340 | s3c_freq_dbg("%s: target %u => %u\n", | |
341 | __func__, target_freq, pll->frequency); | |
342 | ||
343 | target_freq = pll->frequency; | |
344 | } | |
345 | ||
346 | return s3c_cpufreq_settarget(policy, target_freq, pll); | |
347 | ||
348 | err_notpossible: | |
349 | printk(KERN_ERR "no compatible settings for %d\n", target_freq); | |
350 | return -EINVAL; | |
351 | } | |
352 | ||
2e4ea6e8 BD |
353 | struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name) |
354 | { | |
355 | struct clk *clk; | |
356 | ||
357 | clk = clk_get(dev, name); | |
358 | if (IS_ERR(clk)) | |
359 | printk(KERN_ERR "cpufreq: failed to get clock '%s'\n", name); | |
360 | ||
361 | return clk; | |
362 | } | |
363 | ||
364 | static int s3c_cpufreq_init(struct cpufreq_policy *policy) | |
365 | { | |
652ed95d | 366 | policy->clk = clk_arm; |
a307a1e6 | 367 | return cpufreq_generic_init(policy, ftab, cpu_cur.info->latency); |
2e4ea6e8 BD |
368 | } |
369 | ||
21b4c415 | 370 | static int __init s3c_cpufreq_initclks(void) |
2e4ea6e8 BD |
371 | { |
372 | _clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll"); | |
373 | _clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal"); | |
374 | clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk"); | |
375 | clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk"); | |
376 | clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk"); | |
377 | clk_arm = s3c_cpufreq_clk_get(NULL, "armclk"); | |
378 | ||
379 | if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) || | |
380 | IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) { | |
381 | printk(KERN_ERR "%s: could not get clock(s)\n", __func__); | |
382 | return -ENOENT; | |
383 | } | |
384 | ||
385 | printk(KERN_INFO "%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n", __func__, | |
386 | clk_get_rate(clk_fclk) / 1000, | |
387 | clk_get_rate(clk_hclk) / 1000, | |
388 | clk_get_rate(clk_pclk) / 1000, | |
389 | clk_get_rate(clk_arm) / 1000); | |
390 | ||
391 | return 0; | |
392 | } | |
393 | ||
2e4ea6e8 BD |
394 | #ifdef CONFIG_PM |
395 | static struct cpufreq_frequency_table suspend_pll; | |
396 | static unsigned int suspend_freq; | |
397 | ||
7ca64e2d | 398 | static int s3c_cpufreq_suspend(struct cpufreq_policy *policy) |
2e4ea6e8 BD |
399 | { |
400 | suspend_pll.frequency = clk_get_rate(_clk_mpll); | |
50701588 | 401 | suspend_pll.driver_data = __raw_readl(S3C2410_MPLLCON); |
652ed95d | 402 | suspend_freq = clk_get_rate(clk_arm); |
2e4ea6e8 BD |
403 | |
404 | return 0; | |
405 | } | |
406 | ||
407 | static int s3c_cpufreq_resume(struct cpufreq_policy *policy) | |
408 | { | |
409 | int ret; | |
410 | ||
411 | s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy); | |
412 | ||
413 | last_target = ~0; /* invalidate last_target setting */ | |
414 | ||
2e4ea6e8 BD |
415 | /* whilst we will be called later on, we try and re-set the |
416 | * cpu frequencies as soon as possible so that we do not end | |
25985edc | 417 | * up resuming devices and then immediately having to re-set |
2e4ea6e8 BD |
418 | * a number of settings once these devices have restarted. |
419 | * | |
420 | * as a note, it is expected devices are not used until they | |
421 | * have been un-suspended and at that time they should have | |
422 | * used the updated clock settings. | |
423 | */ | |
424 | ||
425 | ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll); | |
426 | if (ret) { | |
427 | printk(KERN_ERR "%s: failed to reset pll/freq\n", __func__); | |
428 | return ret; | |
429 | } | |
430 | ||
431 | return 0; | |
432 | } | |
433 | #else | |
434 | #define s3c_cpufreq_resume NULL | |
435 | #define s3c_cpufreq_suspend NULL | |
436 | #endif | |
437 | ||
438 | static struct cpufreq_driver s3c24xx_driver = { | |
ae6b4271 | 439 | .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
2e4ea6e8 | 440 | .target = s3c_cpufreq_target, |
652ed95d | 441 | .get = cpufreq_generic_get, |
2e4ea6e8 BD |
442 | .init = s3c_cpufreq_init, |
443 | .suspend = s3c_cpufreq_suspend, | |
444 | .resume = s3c_cpufreq_resume, | |
445 | .name = "s3c24xx", | |
446 | }; | |
447 | ||
448 | ||
61882b63 | 449 | int s3c_cpufreq_register(struct s3c_cpufreq_info *info) |
2e4ea6e8 BD |
450 | { |
451 | if (!info || !info->name) { | |
452 | printk(KERN_ERR "%s: failed to pass valid information\n", | |
453 | __func__); | |
454 | return -EINVAL; | |
455 | } | |
456 | ||
457 | printk(KERN_INFO "S3C24XX CPU Frequency driver, %s cpu support\n", | |
458 | info->name); | |
459 | ||
460 | /* check our driver info has valid data */ | |
461 | ||
462 | BUG_ON(info->set_refresh == NULL); | |
463 | BUG_ON(info->set_divs == NULL); | |
464 | BUG_ON(info->calc_divs == NULL); | |
465 | ||
466 | /* info->set_fvco is optional, depending on whether there | |
467 | * is a need to set the clock code. */ | |
468 | ||
469 | cpu_cur.info = info; | |
470 | ||
471 | /* Note, driver registering should probably update locktime */ | |
472 | ||
473 | return 0; | |
474 | } | |
475 | ||
476 | int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board) | |
477 | { | |
478 | struct s3c_cpufreq_board *ours; | |
479 | ||
480 | if (!board) { | |
481 | printk(KERN_INFO "%s: no board data\n", __func__); | |
482 | return -EINVAL; | |
483 | } | |
484 | ||
485 | /* Copy the board information so that each board can make this | |
486 | * initdata. */ | |
487 | ||
d5b73cd8 | 488 | ours = kzalloc(sizeof(*ours), GFP_KERNEL); |
2e4ea6e8 BD |
489 | if (ours == NULL) { |
490 | printk(KERN_ERR "%s: no memory\n", __func__); | |
491 | return -ENOMEM; | |
492 | } | |
493 | ||
494 | *ours = *board; | |
495 | cpu_cur.board = ours; | |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
87ae97f1 | 500 | static int __init s3c_cpufreq_auto_io(void) |
2e4ea6e8 BD |
501 | { |
502 | int ret; | |
503 | ||
504 | if (!cpu_cur.info->get_iotiming) { | |
505 | printk(KERN_ERR "%s: get_iotiming undefined\n", __func__); | |
506 | return -ENOENT; | |
507 | } | |
508 | ||
509 | printk(KERN_INFO "%s: working out IO settings\n", __func__); | |
510 | ||
511 | ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming); | |
512 | if (ret) | |
513 | printk(KERN_ERR "%s: failed to get timings\n", __func__); | |
514 | ||
515 | return ret; | |
516 | } | |
517 | ||
518 | /* if one or is zero, then return the other, otherwise return the min */ | |
519 | #define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b)) | |
520 | ||
521 | /** | |
522 | * s3c_cpufreq_freq_min - find the minimum settings for the given freq. | |
523 | * @dst: The destination structure | |
524 | * @a: One argument. | |
525 | * @b: The other argument. | |
526 | * | |
527 | * Create a minimum of each frequency entry in the 'struct s3c_freq', | |
528 | * unless the entry is zero when it is ignored and the non-zero argument | |
529 | * used. | |
530 | */ | |
531 | static void s3c_cpufreq_freq_min(struct s3c_freq *dst, | |
532 | struct s3c_freq *a, struct s3c_freq *b) | |
533 | { | |
534 | dst->fclk = do_min(a->fclk, b->fclk); | |
535 | dst->hclk = do_min(a->hclk, b->hclk); | |
536 | dst->pclk = do_min(a->pclk, b->pclk); | |
537 | dst->armclk = do_min(a->armclk, b->armclk); | |
538 | } | |
539 | ||
540 | static inline u32 calc_locktime(u32 freq, u32 time_us) | |
541 | { | |
542 | u32 result; | |
543 | ||
544 | result = freq * time_us; | |
545 | result = DIV_ROUND_UP(result, 1000 * 1000); | |
546 | ||
547 | return result; | |
548 | } | |
549 | ||
550 | static void s3c_cpufreq_update_loctkime(void) | |
551 | { | |
552 | unsigned int bits = cpu_cur.info->locktime_bits; | |
553 | u32 rate = (u32)clk_get_rate(_clk_xtal); | |
554 | u32 val; | |
555 | ||
556 | if (bits == 0) { | |
557 | WARN_ON(1); | |
558 | return; | |
559 | } | |
560 | ||
561 | val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits; | |
562 | val |= calc_locktime(rate, cpu_cur.info->locktime_m); | |
563 | ||
564 | printk(KERN_INFO "%s: new locktime is 0x%08x\n", __func__, val); | |
565 | __raw_writel(val, S3C2410_LOCKTIME); | |
566 | } | |
567 | ||
568 | static int s3c_cpufreq_build_freq(void) | |
569 | { | |
570 | int size, ret; | |
571 | ||
572 | if (!cpu_cur.info->calc_freqtable) | |
573 | return -EINVAL; | |
574 | ||
575 | kfree(ftab); | |
576 | ftab = NULL; | |
577 | ||
578 | size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0); | |
579 | size++; | |
580 | ||
71508a1f | 581 | ftab = kzalloc(sizeof(*ftab) * size, GFP_KERNEL); |
2e4ea6e8 BD |
582 | if (!ftab) { |
583 | printk(KERN_ERR "%s: no memory for tables\n", __func__); | |
584 | return -ENOMEM; | |
585 | } | |
586 | ||
587 | ftab_size = size; | |
588 | ||
589 | ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size); | |
590 | s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END); | |
591 | ||
592 | return 0; | |
593 | } | |
594 | ||
595 | static int __init s3c_cpufreq_initcall(void) | |
596 | { | |
597 | int ret = 0; | |
598 | ||
599 | if (cpu_cur.info && cpu_cur.board) { | |
600 | ret = s3c_cpufreq_initclks(); | |
601 | if (ret) | |
602 | goto out; | |
603 | ||
604 | /* get current settings */ | |
605 | s3c_cpufreq_getcur(&cpu_cur); | |
606 | s3c_cpufreq_show("cur", &cpu_cur); | |
607 | ||
608 | if (cpu_cur.board->auto_io) { | |
609 | ret = s3c_cpufreq_auto_io(); | |
610 | if (ret) { | |
611 | printk(KERN_ERR "%s: failed to get io timing\n", | |
612 | __func__); | |
613 | goto out; | |
614 | } | |
615 | } | |
616 | ||
617 | if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) { | |
618 | printk(KERN_ERR "%s: no IO support registered\n", | |
619 | __func__); | |
620 | ret = -EINVAL; | |
621 | goto out; | |
622 | } | |
623 | ||
624 | if (!cpu_cur.info->need_pll) | |
625 | cpu_cur.lock_pll = 1; | |
626 | ||
627 | s3c_cpufreq_update_loctkime(); | |
628 | ||
629 | s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max, | |
630 | &cpu_cur.info->max); | |
631 | ||
632 | if (cpu_cur.info->calc_freqtable) | |
633 | s3c_cpufreq_build_freq(); | |
634 | ||
635 | ret = cpufreq_register_driver(&s3c24xx_driver); | |
636 | } | |
637 | ||
638 | out: | |
639 | return ret; | |
640 | } | |
641 | ||
642 | late_initcall(s3c_cpufreq_initcall); | |
643 | ||
644 | /** | |
645 | * s3c_plltab_register - register CPU PLL table. | |
646 | * @plls: The list of PLL entries. | |
647 | * @plls_no: The size of the PLL entries @plls. | |
648 | * | |
649 | * Register the given set of PLLs with the system. | |
650 | */ | |
651 | int __init s3c_plltab_register(struct cpufreq_frequency_table *plls, | |
652 | unsigned int plls_no) | |
653 | { | |
654 | struct cpufreq_frequency_table *vals; | |
655 | unsigned int size; | |
656 | ||
d5b73cd8 | 657 | size = sizeof(*vals) * (plls_no + 1); |
2e4ea6e8 | 658 | |
71508a1f | 659 | vals = kzalloc(size, GFP_KERNEL); |
2e4ea6e8 BD |
660 | if (vals) { |
661 | memcpy(vals, plls, size); | |
662 | pll_reg = vals; | |
663 | ||
664 | /* write a terminating entry, we don't store it in the | |
665 | * table that is stored in the kernel */ | |
666 | vals += plls_no; | |
667 | vals->frequency = CPUFREQ_TABLE_END; | |
668 | ||
669 | printk(KERN_INFO "cpufreq: %d PLL entries\n", plls_no); | |
670 | } else | |
671 | printk(KERN_ERR "cpufreq: no memory for PLL tables\n"); | |
672 | ||
673 | return vals ? 0 : -ENOMEM; | |
674 | } |