Commit | Line | Data |
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09ec1d7e | 1 | /* |
e02f8664 | 2 | * Copyright (c) 2006-2008 Simtec Electronics |
2e4ea6e8 BD |
3 | * http://armlinux.simtec.co.uk/ |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C24XX CPU Frequency scaling | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
1c5864e2 JP |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
14 | ||
2e4ea6e8 BD |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/ioport.h> | |
19 | #include <linux/cpufreq.h> | |
20 | #include <linux/cpu.h> | |
21 | #include <linux/clk.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/io.h> | |
edbaa603 | 24 | #include <linux/device.h> |
2e4ea6e8 | 25 | #include <linux/sysfs.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
2e4ea6e8 BD |
27 | |
28 | #include <asm/mach/arch.h> | |
29 | #include <asm/mach/map.h> | |
30 | ||
31 | #include <plat/cpu.h> | |
2e4ea6e8 BD |
32 | #include <plat/cpu-freq-core.h> |
33 | ||
34 | #include <mach/regs-clock.h> | |
35 | ||
36 | /* note, cpufreq support deals in kHz, no Hz */ | |
37 | ||
38 | static struct cpufreq_driver s3c24xx_driver; | |
39 | static struct s3c_cpufreq_config cpu_cur; | |
40 | static struct s3c_iotimings s3c24xx_iotiming; | |
41 | static struct cpufreq_frequency_table *pll_reg; | |
42 | static unsigned int last_target = ~0; | |
43 | static unsigned int ftab_size; | |
44 | static struct cpufreq_frequency_table *ftab; | |
45 | ||
46 | static struct clk *_clk_mpll; | |
47 | static struct clk *_clk_xtal; | |
48 | static struct clk *clk_fclk; | |
49 | static struct clk *clk_hclk; | |
50 | static struct clk *clk_pclk; | |
51 | static struct clk *clk_arm; | |
52 | ||
4a6c4108 | 53 | #ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS |
e6d197a6 BD |
54 | struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void) |
55 | { | |
56 | return &cpu_cur; | |
57 | } | |
58 | ||
59 | struct s3c_iotimings *s3c_cpufreq_getiotimings(void) | |
60 | { | |
61 | return &s3c24xx_iotiming; | |
62 | } | |
4a6c4108 | 63 | #endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS */ |
e6d197a6 | 64 | |
2e4ea6e8 BD |
65 | static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg) |
66 | { | |
67 | unsigned long fclk, pclk, hclk, armclk; | |
68 | ||
69 | cfg->freq.fclk = fclk = clk_get_rate(clk_fclk); | |
70 | cfg->freq.hclk = hclk = clk_get_rate(clk_hclk); | |
71 | cfg->freq.pclk = pclk = clk_get_rate(clk_pclk); | |
72 | cfg->freq.armclk = armclk = clk_get_rate(clk_arm); | |
73 | ||
50701588 | 74 | cfg->pll.driver_data = __raw_readl(S3C2410_MPLLCON); |
2e4ea6e8 BD |
75 | cfg->pll.frequency = fclk; |
76 | ||
77 | cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); | |
78 | ||
79 | cfg->divs.h_divisor = fclk / hclk; | |
80 | cfg->divs.p_divisor = fclk / pclk; | |
81 | } | |
82 | ||
83 | static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg) | |
84 | { | |
85 | unsigned long pll = cfg->pll.frequency; | |
86 | ||
87 | cfg->freq.fclk = pll; | |
88 | cfg->freq.hclk = pll / cfg->divs.h_divisor; | |
89 | cfg->freq.pclk = pll / cfg->divs.p_divisor; | |
90 | ||
91 | /* convert hclk into 10ths of nanoseconds for io calcs */ | |
92 | cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); | |
93 | } | |
94 | ||
95 | static inline int closer(unsigned int target, unsigned int n, unsigned int c) | |
96 | { | |
97 | int diff_cur = abs(target - c); | |
98 | int diff_new = abs(target - n); | |
99 | ||
100 | return (diff_new < diff_cur); | |
101 | } | |
102 | ||
103 | static void s3c_cpufreq_show(const char *pfx, | |
104 | struct s3c_cpufreq_config *cfg) | |
105 | { | |
106 | s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n", | |
107 | pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk, | |
108 | cfg->freq.hclk, cfg->divs.h_divisor, | |
109 | cfg->freq.pclk, cfg->divs.p_divisor); | |
110 | } | |
111 | ||
112 | /* functions to wrapper the driver info calls to do the cpu specific work */ | |
113 | ||
114 | static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg) | |
115 | { | |
116 | if (cfg->info->set_iotiming) | |
117 | (cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming); | |
118 | } | |
119 | ||
120 | static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg) | |
121 | { | |
122 | if (cfg->info->calc_iotiming) | |
123 | return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming); | |
124 | ||
125 | return 0; | |
126 | } | |
127 | ||
128 | static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg) | |
129 | { | |
130 | (cfg->info->set_refresh)(cfg); | |
131 | } | |
132 | ||
133 | static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg) | |
134 | { | |
135 | (cfg->info->set_divs)(cfg); | |
136 | } | |
137 | ||
138 | static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg) | |
139 | { | |
140 | return (cfg->info->calc_divs)(cfg); | |
141 | } | |
142 | ||
143 | static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg) | |
144 | { | |
d8b53257 | 145 | cfg->mpll = _clk_mpll; |
2e4ea6e8 BD |
146 | (cfg->info->set_fvco)(cfg); |
147 | } | |
148 | ||
2e4ea6e8 BD |
149 | static inline void s3c_cpufreq_updateclk(struct clk *clk, |
150 | unsigned int freq) | |
151 | { | |
152 | clk_set_rate(clk, freq); | |
153 | } | |
154 | ||
155 | static int s3c_cpufreq_settarget(struct cpufreq_policy *policy, | |
156 | unsigned int target_freq, | |
157 | struct cpufreq_frequency_table *pll) | |
158 | { | |
159 | struct s3c_cpufreq_freqs freqs; | |
160 | struct s3c_cpufreq_config cpu_new; | |
161 | unsigned long flags; | |
162 | ||
163 | cpu_new = cpu_cur; /* copy new from current */ | |
164 | ||
165 | s3c_cpufreq_show("cur", &cpu_cur); | |
166 | ||
167 | /* TODO - check for DMA currently outstanding */ | |
168 | ||
169 | cpu_new.pll = pll ? *pll : cpu_cur.pll; | |
170 | ||
171 | if (pll) | |
172 | freqs.pll_changing = 1; | |
173 | ||
174 | /* update our frequencies */ | |
175 | ||
176 | cpu_new.freq.armclk = target_freq; | |
177 | cpu_new.freq.fclk = cpu_new.pll.frequency; | |
178 | ||
179 | if (s3c_cpufreq_calcdivs(&cpu_new) < 0) { | |
b49c22a6 | 180 | pr_err("no divisors for %d\n", target_freq); |
2e4ea6e8 BD |
181 | goto err_notpossible; |
182 | } | |
183 | ||
184 | s3c_freq_dbg("%s: got divs\n", __func__); | |
185 | ||
186 | s3c_cpufreq_calc(&cpu_new); | |
187 | ||
188 | s3c_freq_dbg("%s: calculated frequencies for new\n", __func__); | |
189 | ||
190 | if (cpu_new.freq.hclk != cpu_cur.freq.hclk) { | |
191 | if (s3c_cpufreq_calcio(&cpu_new) < 0) { | |
b49c22a6 | 192 | pr_err("%s: no IO timings\n", __func__); |
2e4ea6e8 BD |
193 | goto err_notpossible; |
194 | } | |
195 | } | |
196 | ||
197 | s3c_cpufreq_show("new", &cpu_new); | |
198 | ||
199 | /* setup our cpufreq parameters */ | |
200 | ||
201 | freqs.old = cpu_cur.freq; | |
202 | freqs.new = cpu_new.freq; | |
203 | ||
2e4ea6e8 BD |
204 | freqs.freqs.old = cpu_cur.freq.armclk / 1000; |
205 | freqs.freqs.new = cpu_new.freq.armclk / 1000; | |
206 | ||
207 | /* update f/h/p clock settings before we issue the change | |
208 | * notification, so that drivers do not need to do anything | |
209 | * special if they want to recalculate on CPUFREQ_PRECHANGE. */ | |
210 | ||
211 | s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency); | |
212 | s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk); | |
213 | s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk); | |
214 | s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk); | |
215 | ||
216 | /* start the frequency change */ | |
8fec051e | 217 | cpufreq_freq_transition_begin(policy, &freqs.freqs); |
2e4ea6e8 BD |
218 | |
219 | /* If hclk is staying the same, then we do not need to | |
220 | * re-write the IO or the refresh timings whilst we are changing | |
221 | * speed. */ | |
222 | ||
223 | local_irq_save(flags); | |
224 | ||
225 | /* is our memory clock slowing down? */ | |
226 | if (cpu_new.freq.hclk < cpu_cur.freq.hclk) { | |
227 | s3c_cpufreq_setrefresh(&cpu_new); | |
228 | s3c_cpufreq_setio(&cpu_new); | |
229 | } | |
230 | ||
231 | if (cpu_new.freq.fclk == cpu_cur.freq.fclk) { | |
232 | /* not changing PLL, just set the divisors */ | |
233 | ||
234 | s3c_cpufreq_setdivs(&cpu_new); | |
235 | } else { | |
236 | if (cpu_new.freq.fclk < cpu_cur.freq.fclk) { | |
237 | /* slow the cpu down, then set divisors */ | |
238 | ||
239 | s3c_cpufreq_setfvco(&cpu_new); | |
240 | s3c_cpufreq_setdivs(&cpu_new); | |
241 | } else { | |
242 | /* set the divisors, then speed up */ | |
243 | ||
244 | s3c_cpufreq_setdivs(&cpu_new); | |
245 | s3c_cpufreq_setfvco(&cpu_new); | |
246 | } | |
247 | } | |
248 | ||
249 | /* did our memory clock speed up */ | |
250 | if (cpu_new.freq.hclk > cpu_cur.freq.hclk) { | |
251 | s3c_cpufreq_setrefresh(&cpu_new); | |
252 | s3c_cpufreq_setio(&cpu_new); | |
253 | } | |
254 | ||
255 | /* update our current settings */ | |
256 | cpu_cur = cpu_new; | |
257 | ||
258 | local_irq_restore(flags); | |
259 | ||
260 | /* notify everyone we've done this */ | |
8fec051e | 261 | cpufreq_freq_transition_end(policy, &freqs.freqs, 0); |
2e4ea6e8 BD |
262 | |
263 | s3c_freq_dbg("%s: finished\n", __func__); | |
264 | return 0; | |
265 | ||
266 | err_notpossible: | |
b49c22a6 | 267 | pr_err("no compatible settings for %d\n", target_freq); |
2e4ea6e8 BD |
268 | return -EINVAL; |
269 | } | |
270 | ||
271 | /* s3c_cpufreq_target | |
272 | * | |
273 | * called by the cpufreq core to adjust the frequency that the CPU | |
274 | * is currently running at. | |
275 | */ | |
276 | ||
277 | static int s3c_cpufreq_target(struct cpufreq_policy *policy, | |
278 | unsigned int target_freq, | |
279 | unsigned int relation) | |
280 | { | |
281 | struct cpufreq_frequency_table *pll; | |
282 | unsigned int index; | |
283 | ||
284 | /* avoid repeated calls which cause a needless amout of duplicated | |
285 | * logging output (and CPU time as the calculation process is | |
286 | * done) */ | |
287 | if (target_freq == last_target) | |
288 | return 0; | |
289 | ||
290 | last_target = target_freq; | |
291 | ||
292 | s3c_freq_dbg("%s: policy %p, target %u, relation %u\n", | |
293 | __func__, policy, target_freq, relation); | |
294 | ||
295 | if (ftab) { | |
296 | if (cpufreq_frequency_table_target(policy, ftab, | |
297 | target_freq, relation, | |
298 | &index)) { | |
299 | s3c_freq_dbg("%s: table failed\n", __func__); | |
300 | return -EINVAL; | |
301 | } | |
302 | ||
303 | s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__, | |
304 | target_freq, index, ftab[index].frequency); | |
305 | target_freq = ftab[index].frequency; | |
306 | } | |
307 | ||
308 | target_freq *= 1000; /* convert target to Hz */ | |
309 | ||
310 | /* find the settings for our new frequency */ | |
311 | ||
312 | if (!pll_reg || cpu_cur.lock_pll) { | |
313 | /* either we've not got any PLL values, or we've locked | |
314 | * to the current one. */ | |
315 | pll = NULL; | |
316 | } else { | |
317 | struct cpufreq_policy tmp_policy; | |
318 | int ret; | |
319 | ||
320 | /* we keep the cpu pll table in Hz, to ensure we get an | |
321 | * accurate value for the PLL output. */ | |
322 | ||
323 | tmp_policy.min = policy->min * 1000; | |
324 | tmp_policy.max = policy->max * 1000; | |
325 | tmp_policy.cpu = policy->cpu; | |
326 | ||
327 | /* cpufreq_frequency_table_target uses a pointer to 'index' | |
328 | * which is the number of the table entry, not the value of | |
329 | * the table entry's index field. */ | |
330 | ||
331 | ret = cpufreq_frequency_table_target(&tmp_policy, pll_reg, | |
332 | target_freq, relation, | |
333 | &index); | |
334 | ||
335 | if (ret < 0) { | |
b49c22a6 | 336 | pr_err("%s: no PLL available\n", __func__); |
2e4ea6e8 BD |
337 | goto err_notpossible; |
338 | } | |
339 | ||
340 | pll = pll_reg + index; | |
341 | ||
342 | s3c_freq_dbg("%s: target %u => %u\n", | |
343 | __func__, target_freq, pll->frequency); | |
344 | ||
345 | target_freq = pll->frequency; | |
346 | } | |
347 | ||
348 | return s3c_cpufreq_settarget(policy, target_freq, pll); | |
349 | ||
350 | err_notpossible: | |
b49c22a6 | 351 | pr_err("no compatible settings for %d\n", target_freq); |
2e4ea6e8 BD |
352 | return -EINVAL; |
353 | } | |
354 | ||
2e4ea6e8 BD |
355 | struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name) |
356 | { | |
357 | struct clk *clk; | |
358 | ||
359 | clk = clk_get(dev, name); | |
360 | if (IS_ERR(clk)) | |
1c5864e2 | 361 | pr_err("failed to get clock '%s'\n", name); |
2e4ea6e8 BD |
362 | |
363 | return clk; | |
364 | } | |
365 | ||
366 | static int s3c_cpufreq_init(struct cpufreq_policy *policy) | |
367 | { | |
652ed95d | 368 | policy->clk = clk_arm; |
a307a1e6 | 369 | return cpufreq_generic_init(policy, ftab, cpu_cur.info->latency); |
2e4ea6e8 BD |
370 | } |
371 | ||
21b4c415 | 372 | static int __init s3c_cpufreq_initclks(void) |
2e4ea6e8 BD |
373 | { |
374 | _clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll"); | |
375 | _clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal"); | |
376 | clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk"); | |
377 | clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk"); | |
378 | clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk"); | |
379 | clk_arm = s3c_cpufreq_clk_get(NULL, "armclk"); | |
380 | ||
381 | if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) || | |
382 | IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) { | |
b49c22a6 | 383 | pr_err("%s: could not get clock(s)\n", __func__); |
2e4ea6e8 BD |
384 | return -ENOENT; |
385 | } | |
386 | ||
b49c22a6 JP |
387 | pr_info("%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n", |
388 | __func__, | |
389 | clk_get_rate(clk_fclk) / 1000, | |
390 | clk_get_rate(clk_hclk) / 1000, | |
391 | clk_get_rate(clk_pclk) / 1000, | |
392 | clk_get_rate(clk_arm) / 1000); | |
2e4ea6e8 BD |
393 | |
394 | return 0; | |
395 | } | |
396 | ||
2e4ea6e8 BD |
397 | #ifdef CONFIG_PM |
398 | static struct cpufreq_frequency_table suspend_pll; | |
399 | static unsigned int suspend_freq; | |
400 | ||
7ca64e2d | 401 | static int s3c_cpufreq_suspend(struct cpufreq_policy *policy) |
2e4ea6e8 BD |
402 | { |
403 | suspend_pll.frequency = clk_get_rate(_clk_mpll); | |
50701588 | 404 | suspend_pll.driver_data = __raw_readl(S3C2410_MPLLCON); |
652ed95d | 405 | suspend_freq = clk_get_rate(clk_arm); |
2e4ea6e8 BD |
406 | |
407 | return 0; | |
408 | } | |
409 | ||
410 | static int s3c_cpufreq_resume(struct cpufreq_policy *policy) | |
411 | { | |
412 | int ret; | |
413 | ||
414 | s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy); | |
415 | ||
416 | last_target = ~0; /* invalidate last_target setting */ | |
417 | ||
2e4ea6e8 BD |
418 | /* whilst we will be called later on, we try and re-set the |
419 | * cpu frequencies as soon as possible so that we do not end | |
25985edc | 420 | * up resuming devices and then immediately having to re-set |
2e4ea6e8 BD |
421 | * a number of settings once these devices have restarted. |
422 | * | |
423 | * as a note, it is expected devices are not used until they | |
424 | * have been un-suspended and at that time they should have | |
425 | * used the updated clock settings. | |
426 | */ | |
427 | ||
428 | ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll); | |
429 | if (ret) { | |
b49c22a6 | 430 | pr_err("%s: failed to reset pll/freq\n", __func__); |
2e4ea6e8 BD |
431 | return ret; |
432 | } | |
433 | ||
434 | return 0; | |
435 | } | |
436 | #else | |
437 | #define s3c_cpufreq_resume NULL | |
438 | #define s3c_cpufreq_suspend NULL | |
439 | #endif | |
440 | ||
441 | static struct cpufreq_driver s3c24xx_driver = { | |
ae6b4271 | 442 | .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
2e4ea6e8 | 443 | .target = s3c_cpufreq_target, |
652ed95d | 444 | .get = cpufreq_generic_get, |
2e4ea6e8 BD |
445 | .init = s3c_cpufreq_init, |
446 | .suspend = s3c_cpufreq_suspend, | |
447 | .resume = s3c_cpufreq_resume, | |
448 | .name = "s3c24xx", | |
449 | }; | |
450 | ||
451 | ||
61882b63 | 452 | int s3c_cpufreq_register(struct s3c_cpufreq_info *info) |
2e4ea6e8 BD |
453 | { |
454 | if (!info || !info->name) { | |
b49c22a6 | 455 | pr_err("%s: failed to pass valid information\n", __func__); |
2e4ea6e8 BD |
456 | return -EINVAL; |
457 | } | |
458 | ||
b49c22a6 JP |
459 | pr_info("S3C24XX CPU Frequency driver, %s cpu support\n", |
460 | info->name); | |
2e4ea6e8 BD |
461 | |
462 | /* check our driver info has valid data */ | |
463 | ||
464 | BUG_ON(info->set_refresh == NULL); | |
465 | BUG_ON(info->set_divs == NULL); | |
466 | BUG_ON(info->calc_divs == NULL); | |
467 | ||
468 | /* info->set_fvco is optional, depending on whether there | |
469 | * is a need to set the clock code. */ | |
470 | ||
471 | cpu_cur.info = info; | |
472 | ||
473 | /* Note, driver registering should probably update locktime */ | |
474 | ||
475 | return 0; | |
476 | } | |
477 | ||
478 | int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board) | |
479 | { | |
480 | struct s3c_cpufreq_board *ours; | |
481 | ||
482 | if (!board) { | |
b49c22a6 | 483 | pr_info("%s: no board data\n", __func__); |
2e4ea6e8 BD |
484 | return -EINVAL; |
485 | } | |
486 | ||
487 | /* Copy the board information so that each board can make this | |
488 | * initdata. */ | |
489 | ||
d5b73cd8 | 490 | ours = kzalloc(sizeof(*ours), GFP_KERNEL); |
2e4ea6e8 | 491 | if (ours == NULL) { |
b49c22a6 | 492 | pr_err("%s: no memory\n", __func__); |
2e4ea6e8 BD |
493 | return -ENOMEM; |
494 | } | |
495 | ||
496 | *ours = *board; | |
497 | cpu_cur.board = ours; | |
498 | ||
499 | return 0; | |
500 | } | |
501 | ||
87ae97f1 | 502 | static int __init s3c_cpufreq_auto_io(void) |
2e4ea6e8 BD |
503 | { |
504 | int ret; | |
505 | ||
506 | if (!cpu_cur.info->get_iotiming) { | |
b49c22a6 | 507 | pr_err("%s: get_iotiming undefined\n", __func__); |
2e4ea6e8 BD |
508 | return -ENOENT; |
509 | } | |
510 | ||
b49c22a6 | 511 | pr_info("%s: working out IO settings\n", __func__); |
2e4ea6e8 BD |
512 | |
513 | ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming); | |
514 | if (ret) | |
b49c22a6 | 515 | pr_err("%s: failed to get timings\n", __func__); |
2e4ea6e8 BD |
516 | |
517 | return ret; | |
518 | } | |
519 | ||
520 | /* if one or is zero, then return the other, otherwise return the min */ | |
521 | #define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b)) | |
522 | ||
523 | /** | |
524 | * s3c_cpufreq_freq_min - find the minimum settings for the given freq. | |
525 | * @dst: The destination structure | |
526 | * @a: One argument. | |
527 | * @b: The other argument. | |
528 | * | |
529 | * Create a minimum of each frequency entry in the 'struct s3c_freq', | |
530 | * unless the entry is zero when it is ignored and the non-zero argument | |
531 | * used. | |
532 | */ | |
533 | static void s3c_cpufreq_freq_min(struct s3c_freq *dst, | |
534 | struct s3c_freq *a, struct s3c_freq *b) | |
535 | { | |
536 | dst->fclk = do_min(a->fclk, b->fclk); | |
537 | dst->hclk = do_min(a->hclk, b->hclk); | |
538 | dst->pclk = do_min(a->pclk, b->pclk); | |
539 | dst->armclk = do_min(a->armclk, b->armclk); | |
540 | } | |
541 | ||
542 | static inline u32 calc_locktime(u32 freq, u32 time_us) | |
543 | { | |
544 | u32 result; | |
545 | ||
546 | result = freq * time_us; | |
547 | result = DIV_ROUND_UP(result, 1000 * 1000); | |
548 | ||
549 | return result; | |
550 | } | |
551 | ||
552 | static void s3c_cpufreq_update_loctkime(void) | |
553 | { | |
554 | unsigned int bits = cpu_cur.info->locktime_bits; | |
555 | u32 rate = (u32)clk_get_rate(_clk_xtal); | |
556 | u32 val; | |
557 | ||
558 | if (bits == 0) { | |
559 | WARN_ON(1); | |
560 | return; | |
561 | } | |
562 | ||
563 | val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits; | |
564 | val |= calc_locktime(rate, cpu_cur.info->locktime_m); | |
565 | ||
b49c22a6 | 566 | pr_info("%s: new locktime is 0x%08x\n", __func__, val); |
2e4ea6e8 BD |
567 | __raw_writel(val, S3C2410_LOCKTIME); |
568 | } | |
569 | ||
570 | static int s3c_cpufreq_build_freq(void) | |
571 | { | |
572 | int size, ret; | |
573 | ||
574 | if (!cpu_cur.info->calc_freqtable) | |
575 | return -EINVAL; | |
576 | ||
577 | kfree(ftab); | |
578 | ftab = NULL; | |
579 | ||
580 | size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0); | |
581 | size++; | |
582 | ||
71508a1f | 583 | ftab = kzalloc(sizeof(*ftab) * size, GFP_KERNEL); |
2e4ea6e8 | 584 | if (!ftab) { |
b49c22a6 | 585 | pr_err("%s: no memory for tables\n", __func__); |
2e4ea6e8 BD |
586 | return -ENOMEM; |
587 | } | |
588 | ||
589 | ftab_size = size; | |
590 | ||
591 | ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size); | |
592 | s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END); | |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
597 | static int __init s3c_cpufreq_initcall(void) | |
598 | { | |
599 | int ret = 0; | |
600 | ||
601 | if (cpu_cur.info && cpu_cur.board) { | |
602 | ret = s3c_cpufreq_initclks(); | |
603 | if (ret) | |
604 | goto out; | |
605 | ||
606 | /* get current settings */ | |
607 | s3c_cpufreq_getcur(&cpu_cur); | |
608 | s3c_cpufreq_show("cur", &cpu_cur); | |
609 | ||
610 | if (cpu_cur.board->auto_io) { | |
611 | ret = s3c_cpufreq_auto_io(); | |
612 | if (ret) { | |
b49c22a6 | 613 | pr_err("%s: failed to get io timing\n", |
2e4ea6e8 BD |
614 | __func__); |
615 | goto out; | |
616 | } | |
617 | } | |
618 | ||
619 | if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) { | |
b49c22a6 | 620 | pr_err("%s: no IO support registered\n", __func__); |
2e4ea6e8 BD |
621 | ret = -EINVAL; |
622 | goto out; | |
623 | } | |
624 | ||
625 | if (!cpu_cur.info->need_pll) | |
626 | cpu_cur.lock_pll = 1; | |
627 | ||
628 | s3c_cpufreq_update_loctkime(); | |
629 | ||
630 | s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max, | |
631 | &cpu_cur.info->max); | |
632 | ||
633 | if (cpu_cur.info->calc_freqtable) | |
634 | s3c_cpufreq_build_freq(); | |
635 | ||
636 | ret = cpufreq_register_driver(&s3c24xx_driver); | |
637 | } | |
638 | ||
639 | out: | |
640 | return ret; | |
641 | } | |
642 | ||
643 | late_initcall(s3c_cpufreq_initcall); | |
644 | ||
645 | /** | |
646 | * s3c_plltab_register - register CPU PLL table. | |
647 | * @plls: The list of PLL entries. | |
648 | * @plls_no: The size of the PLL entries @plls. | |
649 | * | |
650 | * Register the given set of PLLs with the system. | |
651 | */ | |
62f49ee2 | 652 | int s3c_plltab_register(struct cpufreq_frequency_table *plls, |
2e4ea6e8 BD |
653 | unsigned int plls_no) |
654 | { | |
655 | struct cpufreq_frequency_table *vals; | |
656 | unsigned int size; | |
657 | ||
d5b73cd8 | 658 | size = sizeof(*vals) * (plls_no + 1); |
2e4ea6e8 | 659 | |
71508a1f | 660 | vals = kzalloc(size, GFP_KERNEL); |
2e4ea6e8 BD |
661 | if (vals) { |
662 | memcpy(vals, plls, size); | |
663 | pll_reg = vals; | |
664 | ||
665 | /* write a terminating entry, we don't store it in the | |
666 | * table that is stored in the kernel */ | |
667 | vals += plls_no; | |
668 | vals->frequency = CPUFREQ_TABLE_END; | |
669 | ||
1c5864e2 | 670 | pr_info("%d PLL entries\n", plls_no); |
2e4ea6e8 | 671 | } else |
1c5864e2 | 672 | pr_err("no memory for PLL tables\n"); |
2e4ea6e8 BD |
673 | |
674 | return vals ? 0 : -ENOMEM; | |
675 | } |