Commit | Line | Data |
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be2de99b | 1 | /* |
b3748ddd MB |
2 | * Copyright 2009 Wolfson Microelectronics plc |
3 | * | |
4 | * S3C64xx CPUfreq Support | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
a6a43412 MB |
11 | #define pr_fmt(fmt) "cpufreq: " fmt |
12 | ||
b3748ddd MB |
13 | #include <linux/kernel.h> |
14 | #include <linux/types.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/cpufreq.h> | |
17 | #include <linux/clk.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/regulator/consumer.h> | |
a6ee8779 | 20 | #include <linux/module.h> |
b3748ddd | 21 | |
b3748ddd | 22 | static struct regulator *vddarm; |
43f1069e | 23 | static unsigned long regulator_latency; |
b3748ddd MB |
24 | |
25 | #ifdef CONFIG_CPU_S3C6410 | |
26 | struct s3c64xx_dvfs { | |
27 | unsigned int vddarm_min; | |
28 | unsigned int vddarm_max; | |
29 | }; | |
30 | ||
31 | static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = { | |
e9c08f0d MB |
32 | [0] = { 1000000, 1150000 }, |
33 | [1] = { 1050000, 1150000 }, | |
34 | [2] = { 1100000, 1150000 }, | |
35 | [3] = { 1200000, 1350000 }, | |
c6e2d685 | 36 | [4] = { 1300000, 1350000 }, |
b3748ddd MB |
37 | }; |
38 | ||
39 | static struct cpufreq_frequency_table s3c64xx_freq_table[] = { | |
40 | { 0, 66000 }, | |
ef993ef8 | 41 | { 0, 100000 }, |
b3748ddd | 42 | { 0, 133000 }, |
ef993ef8 | 43 | { 1, 200000 }, |
b3748ddd MB |
44 | { 1, 222000 }, |
45 | { 1, 266000 }, | |
46 | { 2, 333000 }, | |
47 | { 2, 400000 }, | |
e9c08f0d MB |
48 | { 2, 532000 }, |
49 | { 2, 533000 }, | |
50 | { 3, 667000 }, | |
c6e2d685 | 51 | { 4, 800000 }, |
b3748ddd MB |
52 | { 0, CPUFREQ_TABLE_END }, |
53 | }; | |
54 | #endif | |
55 | ||
b3748ddd | 56 | static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy, |
9c0ebcf7 | 57 | unsigned int index) |
b3748ddd | 58 | { |
b3748ddd | 59 | struct s3c64xx_dvfs *dvfs; |
d4019f0a VK |
60 | unsigned int old_freq, new_freq; |
61 | int ret; | |
b3748ddd | 62 | |
652ed95d | 63 | old_freq = clk_get_rate(policy->clk) / 1000; |
d4019f0a | 64 | new_freq = s3c64xx_freq_table[index].frequency; |
9c0ebcf7 | 65 | dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[index].driver_data]; |
b3748ddd | 66 | |
b3748ddd | 67 | #ifdef CONFIG_REGULATOR |
d4019f0a | 68 | if (vddarm && new_freq > old_freq) { |
b3748ddd MB |
69 | ret = regulator_set_voltage(vddarm, |
70 | dvfs->vddarm_min, | |
71 | dvfs->vddarm_max); | |
72 | if (ret != 0) { | |
a6a43412 | 73 | pr_err("Failed to set VDDARM for %dkHz: %d\n", |
d4019f0a VK |
74 | new_freq, ret); |
75 | return ret; | |
b3748ddd MB |
76 | } |
77 | } | |
78 | #endif | |
79 | ||
652ed95d | 80 | ret = clk_set_rate(policy->clk, new_freq * 1000); |
b3748ddd | 81 | if (ret < 0) { |
a6a43412 | 82 | pr_err("Failed to set rate %dkHz: %d\n", |
d4019f0a VK |
83 | new_freq, ret); |
84 | return ret; | |
b3748ddd MB |
85 | } |
86 | ||
87 | #ifdef CONFIG_REGULATOR | |
d4019f0a | 88 | if (vddarm && new_freq < old_freq) { |
b3748ddd MB |
89 | ret = regulator_set_voltage(vddarm, |
90 | dvfs->vddarm_min, | |
91 | dvfs->vddarm_max); | |
92 | if (ret != 0) { | |
a6a43412 | 93 | pr_err("Failed to set VDDARM for %dkHz: %d\n", |
d4019f0a | 94 | new_freq, ret); |
652ed95d | 95 | if (clk_set_rate(policy->clk, old_freq * 1000) < 0) |
d4019f0a VK |
96 | pr_err("Failed to restore original clock rate\n"); |
97 | ||
98 | return ret; | |
b3748ddd MB |
99 | } |
100 | } | |
101 | #endif | |
102 | ||
a6a43412 | 103 | pr_debug("Set actual frequency %lukHz\n", |
652ed95d | 104 | clk_get_rate(policy->clk) / 1000); |
b3748ddd MB |
105 | |
106 | return 0; | |
b3748ddd MB |
107 | } |
108 | ||
109 | #ifdef CONFIG_REGULATOR | |
43f1069e | 110 | static void __init s3c64xx_cpufreq_config_regulator(void) |
b3748ddd MB |
111 | { |
112 | int count, v, i, found; | |
113 | struct cpufreq_frequency_table *freq; | |
114 | struct s3c64xx_dvfs *dvfs; | |
115 | ||
116 | count = regulator_count_voltages(vddarm); | |
117 | if (count < 0) { | |
a6a43412 | 118 | pr_err("Unable to check supported voltages\n"); |
b3748ddd MB |
119 | } |
120 | ||
121 | freq = s3c64xx_freq_table; | |
43f1069e | 122 | while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) { |
b3748ddd MB |
123 | if (freq->frequency == CPUFREQ_ENTRY_INVALID) |
124 | continue; | |
125 | ||
0e824432 | 126 | dvfs = &s3c64xx_dvfs_table[freq->driver_data]; |
b3748ddd MB |
127 | found = 0; |
128 | ||
129 | for (i = 0; i < count; i++) { | |
130 | v = regulator_list_voltage(vddarm, i); | |
131 | if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max) | |
132 | found = 1; | |
133 | } | |
134 | ||
135 | if (!found) { | |
a6a43412 | 136 | pr_debug("%dkHz unsupported by regulator\n", |
b3748ddd MB |
137 | freq->frequency); |
138 | freq->frequency = CPUFREQ_ENTRY_INVALID; | |
139 | } | |
140 | ||
141 | freq++; | |
142 | } | |
43f1069e MB |
143 | |
144 | /* Guess based on having to do an I2C/SPI write; in future we | |
145 | * will be able to query the regulator performance here. */ | |
146 | regulator_latency = 1 * 1000 * 1000; | |
b3748ddd MB |
147 | } |
148 | #endif | |
149 | ||
6d0de157 | 150 | static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy) |
b3748ddd MB |
151 | { |
152 | int ret; | |
153 | struct cpufreq_frequency_table *freq; | |
154 | ||
155 | if (policy->cpu != 0) | |
156 | return -EINVAL; | |
157 | ||
158 | if (s3c64xx_freq_table == NULL) { | |
a6a43412 | 159 | pr_err("No frequency information for this CPU\n"); |
b3748ddd MB |
160 | return -ENODEV; |
161 | } | |
162 | ||
652ed95d VK |
163 | policy->clk = clk_get(NULL, "armclk"); |
164 | if (IS_ERR(policy->clk)) { | |
a6a43412 | 165 | pr_err("Unable to obtain ARMCLK: %ld\n", |
652ed95d VK |
166 | PTR_ERR(policy->clk)); |
167 | return PTR_ERR(policy->clk); | |
b3748ddd MB |
168 | } |
169 | ||
170 | #ifdef CONFIG_REGULATOR | |
171 | vddarm = regulator_get(NULL, "vddarm"); | |
172 | if (IS_ERR(vddarm)) { | |
173 | ret = PTR_ERR(vddarm); | |
a6a43412 MB |
174 | pr_err("Failed to obtain VDDARM: %d\n", ret); |
175 | pr_err("Only frequency scaling available\n"); | |
b3748ddd MB |
176 | vddarm = NULL; |
177 | } else { | |
43f1069e | 178 | s3c64xx_cpufreq_config_regulator(); |
b3748ddd MB |
179 | } |
180 | #endif | |
181 | ||
182 | freq = s3c64xx_freq_table; | |
183 | while (freq->frequency != CPUFREQ_TABLE_END) { | |
184 | unsigned long r; | |
185 | ||
186 | /* Check for frequencies we can generate */ | |
652ed95d | 187 | r = clk_round_rate(policy->clk, freq->frequency * 1000); |
b3748ddd | 188 | r /= 1000; |
383af9c2 | 189 | if (r != freq->frequency) { |
a6a43412 | 190 | pr_debug("%dkHz unsupported by clock\n", |
383af9c2 | 191 | freq->frequency); |
b3748ddd | 192 | freq->frequency = CPUFREQ_ENTRY_INVALID; |
383af9c2 | 193 | } |
b3748ddd MB |
194 | |
195 | /* If we have no regulator then assume startup | |
196 | * frequency is the maximum we can support. */ | |
652ed95d | 197 | if (!vddarm && freq->frequency > clk_get_rate(policy->clk) / 1000) |
b3748ddd MB |
198 | freq->frequency = CPUFREQ_ENTRY_INVALID; |
199 | ||
200 | freq++; | |
201 | } | |
202 | ||
43f1069e MB |
203 | /* Datasheet says PLL stabalisation time (if we were to use |
204 | * the PLLs, which we don't currently) is ~300us worst case, | |
205 | * but add some fudge. | |
206 | */ | |
a307a1e6 VK |
207 | ret = cpufreq_generic_init(policy, s3c64xx_freq_table, |
208 | (500 * 1000) + regulator_latency); | |
b3748ddd | 209 | if (ret != 0) { |
a6a43412 | 210 | pr_err("Failed to configure frequency table: %d\n", |
b3748ddd MB |
211 | ret); |
212 | regulator_put(vddarm); | |
652ed95d | 213 | clk_put(policy->clk); |
b3748ddd MB |
214 | } |
215 | ||
216 | return ret; | |
217 | } | |
218 | ||
219 | static struct cpufreq_driver s3c64xx_cpufreq_driver = { | |
ae6b4271 | 220 | .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
e96a4105 | 221 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 222 | .target_index = s3c64xx_cpufreq_set_target, |
652ed95d | 223 | .get = cpufreq_generic_get, |
b3748ddd MB |
224 | .init = s3c64xx_cpufreq_driver_init, |
225 | .name = "s3c", | |
226 | }; | |
227 | ||
228 | static int __init s3c64xx_cpufreq_init(void) | |
229 | { | |
230 | return cpufreq_register_driver(&s3c64xx_cpufreq_driver); | |
231 | } | |
232 | module_init(s3c64xx_cpufreq_init); |