[deliverable/linux.git] / drivers / cpufreq / s5pv210-cpufreq.c

/*
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * CPU frequency scaling for S5PC110/S5PV210
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/cpufreq.h>
#include <linux/reboot.h>
#include <linux/regulator/consumer.h>

#include <mach/map.h>
#include <mach/regs-clock.h>

static struct clk *dmc0_clk;
static struct clk *dmc1_clk;
static DEFINE_MUTEX(set_freq_lock);

/* APLL M,P,S values for 1G/800Mhz */
#define APLL_VAL_1000	((1 << 31) | (125 << 16) | (3 << 8) | 1)
#define APLL_VAL_800	((1 << 31) | (100 << 16) | (3 << 8) | 1)

/* Use 800MHz when entering sleep mode */
#define SLEEP_FREQ	(800 * 1000)

/* Tracks if cpu freqency can be updated anymore */
static bool no_cpufreq_access;

/*
 * DRAM configurations to calculate refresh counter for changing
 * frequency of memory.
 */
struct dram_conf {
	unsigned long freq;	/* HZ */
	unsigned long refresh;	/* DRAM refresh counter * 1000 */
};

/* DRAM configuration (DMC0 and DMC1) */
static struct dram_conf s5pv210_dram_conf[2];

enum perf_level {
	L0, L1, L2, L3, L4,
};

enum s5pv210_mem_type {
	LPDDR	= 0x1,
	LPDDR2	= 0x2,
	DDR2	= 0x4,
};

enum s5pv210_dmc_port {
	DMC0 = 0,
	DMC1,
};

static struct cpufreq_frequency_table s5pv210_freq_table[] = {
	{0, L0, 1000*1000},
	{0, L1, 800*1000},
	{0, L2, 400*1000},
	{0, L3, 200*1000},
	{0, L4, 100*1000},
	{0, 0, CPUFREQ_TABLE_END},
};

static struct regulator *arm_regulator;
static struct regulator *int_regulator;

struct s5pv210_dvs_conf {
	int arm_volt;	/* uV */
	int int_volt;	/* uV */
};

static const int arm_volt_max = 1350000;
static const int int_volt_max = 1250000;

static struct s5pv210_dvs_conf dvs_conf[] = {
	[L0] = {
		.arm_volt	= 1250000,
		.int_volt	= 1100000,
	},
	[L1] = {
		.arm_volt	= 1200000,
		.int_volt	= 1100000,
	},
	[L2] = {
		.arm_volt	= 1050000,
		.int_volt	= 1100000,
	},
	[L3] = {
		.arm_volt	= 950000,
		.int_volt	= 1100000,
	},
	[L4] = {
		.arm_volt	= 950000,
		.int_volt	= 1000000,
	},
};

static u32 clkdiv_val[5][11] = {
	/*
	 * Clock divider value for following
	 * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
	 *   HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
	 *   ONEDRAM, MFC, G3D }
	 */

	/* L0 : [1000/200/100][166/83][133/66][200/200] */
	{0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},

	/* L1 : [800/200/100][166/83][133/66][200/200] */
	{0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},

	/* L2 : [400/200/100][166/83][133/66][200/200] */
	{1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},

	/* L3 : [200/200/100][166/83][133/66][200/200] */
	{3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},

	/* L4 : [100/100/100][83/83][66/66][100/100] */
	{7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
};

/*
 * This function set DRAM refresh counter
 * accoriding to operating frequency of DRAM
 * ch: DMC port number 0 or 1
 * freq: Operating frequency of DRAM(KHz)
 */
static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
{
	unsigned long tmp, tmp1;
	void __iomem *reg = NULL;

	if (ch == DMC0) {
		reg = (S5P_VA_DMC0 + 0x30);
	} else if (ch == DMC1) {
		reg = (S5P_VA_DMC1 + 0x30);
	} else {
		printk(KERN_ERR "Cannot find DMC port\n");
		return;
	}

	/* Find current DRAM frequency */
	tmp = s5pv210_dram_conf[ch].freq;

	do_div(tmp, freq);

	tmp1 = s5pv210_dram_conf[ch].refresh;

	do_div(tmp1, tmp);

	__raw_writel(tmp1, reg);
}

static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
{
	unsigned long reg;
	unsigned int priv_index;
	unsigned int pll_changing = 0;
	unsigned int bus_speed_changing = 0;
	unsigned int old_freq, new_freq;
	int arm_volt, int_volt;
	int ret = 0;

	mutex_lock(&set_freq_lock);

	if (no_cpufreq_access) {
		pr_err("Denied access to %s as it is disabled temporarily\n",
		       __func__);
		ret = -EINVAL;
		goto exit;
	}

	old_freq = policy->cur;
	new_freq = s5pv210_freq_table[index].frequency;

	/* Finding current running level index */
	if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
					   old_freq, CPUFREQ_RELATION_H,
					   &priv_index)) {
		ret = -EINVAL;
		goto exit;
	}

	arm_volt = dvs_conf[index].arm_volt;
	int_volt = dvs_conf[index].int_volt;

	if (new_freq > old_freq) {
		ret = regulator_set_voltage(arm_regulator,
				arm_volt, arm_volt_max);
		if (ret)
			goto exit;

		ret = regulator_set_voltage(int_regulator,
				int_volt, int_volt_max);
		if (ret)
			goto exit;
	}

	/* Check if there need to change PLL */
	if ((index == L0) || (priv_index == L0))
		pll_changing = 1;

	/* Check if there need to change System bus clock */
	if ((index == L4) || (priv_index == L4))
		bus_speed_changing = 1;

	if (bus_speed_changing) {
		/*
		 * Reconfigure DRAM refresh counter value for minimum
		 * temporary clock while changing divider.
		 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
		 */
		if (pll_changing)
			s5pv210_set_refresh(DMC1, 83000);
		else
			s5pv210_set_refresh(DMC1, 100000);

		s5pv210_set_refresh(DMC0, 83000);
	}

	/*
	 * APLL should be changed in this level
	 * APLL -> MPLL(for stable transition) -> APLL
	 * Some clock source's clock API are not prepared.
	 * Do not use clock API in below code.
	 */
	if (pll_changing) {
		/*
		 * 1. Temporary Change divider for MFC and G3D
		 * SCLKA2M(200/1=200)->(200/4=50)Mhz
		 */
		reg = __raw_readl(S5P_CLK_DIV2);
		reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
		reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
			(3 << S5P_CLKDIV2_MFC_SHIFT);
		__raw_writel(reg, S5P_CLK_DIV2);

		/* For MFC, G3D dividing */
		do {
			reg = __raw_readl(S5P_CLKDIV_STAT0);
		} while (reg & ((1 << 16) | (1 << 17)));

		/*
		 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
		 * (200/4=50)->(667/4=166)Mhz
		 */
		reg = __raw_readl(S5P_CLK_SRC2);
		reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
		reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
			(1 << S5P_CLKSRC2_MFC_SHIFT);
		__raw_writel(reg, S5P_CLK_SRC2);

		do {
			reg = __raw_readl(S5P_CLKMUX_STAT1);
		} while (reg & ((1 << 7) | (1 << 3)));

		/*
		 * 3. DMC1 refresh count for 133Mhz if (index == L4) is
		 * true refresh counter is already programed in upper
		 * code. 0x287@83Mhz
		 */
		if (!bus_speed_changing)
			s5pv210_set_refresh(DMC1, 133000);

		/* 4. SCLKAPLL -> SCLKMPLL */
		reg = __raw_readl(S5P_CLK_SRC0);
		reg &= ~(S5P_CLKSRC0_MUX200_MASK);
		reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
		__raw_writel(reg, S5P_CLK_SRC0);

		do {
			reg = __raw_readl(S5P_CLKMUX_STAT0);
		} while (reg & (0x1 << 18));

	}

	/* Change divider */
	reg = __raw_readl(S5P_CLK_DIV0);

	reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
		S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
		S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK |
		S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK);

	reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
		(clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) |
		(clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) |
		(clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) |
		(clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) |
		(clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) |
		(clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
		(clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));

	__raw_writel(reg, S5P_CLK_DIV0);

	do {
		reg = __raw_readl(S5P_CLKDIV_STAT0);
	} while (reg & 0xff);

	/* ARM MCS value changed */
	reg = __raw_readl(S5P_ARM_MCS_CON);
	reg &= ~0x3;
	if (index >= L3)
		reg |= 0x3;
	else
		reg |= 0x1;

	__raw_writel(reg, S5P_ARM_MCS_CON);

	if (pll_changing) {
		/* 5. Set Lock time = 30us*24Mhz = 0x2cf */
		__raw_writel(0x2cf, S5P_APLL_LOCK);

		/*
		 * 6. Turn on APLL
		 * 6-1. Set PMS values
		 * 6-2. Wait untile the PLL is locked
		 */
		if (index == L0)
			__raw_writel(APLL_VAL_1000, S5P_APLL_CON);
		else
			__raw_writel(APLL_VAL_800, S5P_APLL_CON);

		do {
			reg = __raw_readl(S5P_APLL_CON);
		} while (!(reg & (0x1 << 29)));

		/*
		 * 7. Change souce clock from SCLKMPLL(667Mhz)
		 * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
		 * (667/4=166)->(200/4=50)Mhz
		 */
		reg = __raw_readl(S5P_CLK_SRC2);
		reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
		reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
			(0 << S5P_CLKSRC2_MFC_SHIFT);
		__raw_writel(reg, S5P_CLK_SRC2);

		do {
			reg = __raw_readl(S5P_CLKMUX_STAT1);
		} while (reg & ((1 << 7) | (1 << 3)));

		/*
		 * 8. Change divider for MFC and G3D
		 * (200/4=50)->(200/1=200)Mhz
		 */
		reg = __raw_readl(S5P_CLK_DIV2);
		reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
		reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
			(clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
		__raw_writel(reg, S5P_CLK_DIV2);

		/* For MFC, G3D dividing */
		do {
			reg = __raw_readl(S5P_CLKDIV_STAT0);
		} while (reg & ((1 << 16) | (1 << 17)));

		/* 9. Change MPLL to APLL in MSYS_MUX */
		reg = __raw_readl(S5P_CLK_SRC0);
		reg &= ~(S5P_CLKSRC0_MUX200_MASK);
		reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
		__raw_writel(reg, S5P_CLK_SRC0);

		do {
			reg = __raw_readl(S5P_CLKMUX_STAT0);
		} while (reg & (0x1 << 18));

		/*
		 * 10. DMC1 refresh counter
		 * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
		 * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
		 */
		if (!bus_speed_changing)
			s5pv210_set_refresh(DMC1, 200000);
	}

	/*
	 * L4 level need to change memory bus speed, hence onedram clock divier
	 * and memory refresh parameter should be changed
	 */
	if (bus_speed_changing) {
		reg = __raw_readl(S5P_CLK_DIV6);
		reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
		reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
		__raw_writel(reg, S5P_CLK_DIV6);

		do {
			reg = __raw_readl(S5P_CLKDIV_STAT1);
		} while (reg & (1 << 15));

		/* Reconfigure DRAM refresh counter value */
		if (index != L4) {
			/*
			 * DMC0 : 166Mhz
			 * DMC1 : 200Mhz
			 */
			s5pv210_set_refresh(DMC0, 166000);
			s5pv210_set_refresh(DMC1, 200000);
		} else {
			/*
			 * DMC0 : 83Mhz
			 * DMC1 : 100Mhz
			 */
			s5pv210_set_refresh(DMC0, 83000);
			s5pv210_set_refresh(DMC1, 100000);
		}
	}

	if (new_freq < old_freq) {
		regulator_set_voltage(int_regulator,
				int_volt, int_volt_max);

		regulator_set_voltage(arm_regulator,
				arm_volt, arm_volt_max);
	}

	printk(KERN_DEBUG "Perf changed[L%d]\n", index);

exit:
	mutex_unlock(&set_freq_lock);
	return ret;
}

static int check_mem_type(void __iomem *dmc_reg)
{
	unsigned long val;

	val = __raw_readl(dmc_reg + 0x4);
	val = (val & (0xf << 8));

	return val >> 8;
}

static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
{
	unsigned long mem_type;
	int ret;

	policy->clk = clk_get(NULL, "armclk");
	if (IS_ERR(policy->clk))
		return PTR_ERR(policy->clk);

	dmc0_clk = clk_get(NULL, "sclk_dmc0");
	if (IS_ERR(dmc0_clk)) {
		ret = PTR_ERR(dmc0_clk);
		goto out_dmc0;
	}

	dmc1_clk = clk_get(NULL, "hclk_msys");
	if (IS_ERR(dmc1_clk)) {
		ret = PTR_ERR(dmc1_clk);
		goto out_dmc1;
	}

	if (policy->cpu != 0) {
		ret = -EINVAL;
		goto out_dmc1;
	}

	/*
	 * check_mem_type : This driver only support LPDDR & LPDDR2.
	 * other memory type is not supported.
	 */
	mem_type = check_mem_type(S5P_VA_DMC0);

	if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
		printk(KERN_ERR "CPUFreq doesn't support this memory type\n");
		ret = -EINVAL;
		goto out_dmc1;
	}

	/* Find current refresh counter and frequency each DMC */
	s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000);
	s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);

	s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000);
	s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);

	policy->suspend_freq = SLEEP_FREQ;
	return cpufreq_generic_init(policy, s5pv210_freq_table, 40000);

out_dmc1:
	clk_put(dmc0_clk);
out_dmc0:
	clk_put(policy->clk);
	return ret;
}

static int s5pv210_cpufreq_reboot_notifier_event(struct notifier_block *this,
						 unsigned long event, void *ptr)
{
	int ret;

	ret = cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ, 0);
	if (ret < 0)
		return NOTIFY_BAD;

	no_cpufreq_access = true;
	return NOTIFY_DONE;
}

static struct cpufreq_driver s5pv210_driver = {
	.flags		= CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
	.verify		= cpufreq_generic_frequency_table_verify,
	.target_index	= s5pv210_target,
	.get		= cpufreq_generic_get,
	.init		= s5pv210_cpu_init,
	.name		= "s5pv210",
#ifdef CONFIG_PM
	.suspend	= cpufreq_generic_suspend,
	.resume		= cpufreq_generic_suspend, /* We need to set SLEEP FREQ again */
#endif
};

static struct notifier_block s5pv210_cpufreq_reboot_notifier = {
	.notifier_call = s5pv210_cpufreq_reboot_notifier_event,
};

static int __init s5pv210_cpufreq_init(void)
{
	arm_regulator = regulator_get(NULL, "vddarm");
	if (IS_ERR(arm_regulator)) {
		pr_err("failed to get regulator vddarm");
		return PTR_ERR(arm_regulator);
	}

	int_regulator = regulator_get(NULL, "vddint");
	if (IS_ERR(int_regulator)) {
		pr_err("failed to get regulator vddint");
		regulator_put(arm_regulator);
		return PTR_ERR(int_regulator);
	}

	register_reboot_notifier(&s5pv210_cpufreq_reboot_notifier);

	return cpufreq_register_driver(&s5pv210_driver);
}

late_initcall(s5pv210_cpufreq_init);
Commit	Line	Data
f7d77079	1	/*
83efc743 JL	2	* Copyright (c) 2010 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com
	4	*
	5	* CPU frequency scaling for S5PC110/S5PV210
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/types.h>
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
	15	#include <linux/err.h>
	16	#include <linux/clk.h>
	17	#include <linux/io.h>
	18	#include <linux/cpufreq.h>
fe7f1bcb	19	#include <linux/reboot.h>
e8b4c198	20	#include <linux/regulator/consumer.h>
83efc743 JL	21
	22	#include <mach/map.h>
	23	#include <mach/regs-clock.h>
	24
83efc743 JL	25	static struct clk *dmc0_clk;
83efc743 JL	26	static struct clk *dmc1_clk;
5b02b779	27	static DEFINE_MUTEX(set_freq_lock);
83efc743 JL	28
	29	/* APLL M,P,S values for 1G/800Mhz */
	30	#define APLL_VAL_1000 ((1 << 31) \| (125 << 16) \| (3 << 8) \| 1)
	31	#define APLL_VAL_800 ((1 << 31) \| (100 << 16) \| (3 << 8) \| 1)
	32
405e6d6d HK	33	/* Use 800MHz when entering sleep mode */
	34	#define SLEEP_FREQ (800 * 1000)
	35
9c0ebcf7	36	/* Tracks if cpu freqency can be updated anymore */
90d5d0a1 HK	37	static bool no_cpufreq_access;
90d5d0a1 HK	38
83efc743 JL	39	/*
	40	* DRAM configurations to calculate refresh counter for changing
	41	* frequency of memory.
	42	*/
	43	struct dram_conf {
	44	unsigned long freq; /* HZ */
	45	unsigned long refresh; /* DRAM refresh counter * 1000 */
	46	};
	47
	48	/* DRAM configuration (DMC0 and DMC1) */
	49	static struct dram_conf s5pv210_dram_conf[2];
	50
	51	enum perf_level {
	52	L0, L1, L2, L3, L4,
	53	};
	54
	55	enum s5pv210_mem_type {
	56	LPDDR = 0x1,
	57	LPDDR2 = 0x2,
	58	DDR2 = 0x4,
	59	};
	60
	61	enum s5pv210_dmc_port {
	62	DMC0 = 0,
	63	DMC1,
	64	};
	65
	66	static struct cpufreq_frequency_table s5pv210_freq_table[] = {
7f4b0461 VK	67	{0, L0, 1000*1000},
	68	{0, L1, 800*1000},
	69	{0, L2, 400*1000},
	70	{0, L3, 200*1000},
	71	{0, L4, 100*1000},
	72	{0, 0, CPUFREQ_TABLE_END},
83efc743 JL	73	};
83efc743 JL	74
e8b4c198 JC	75	static struct regulator *arm_regulator;
	76	static struct regulator *int_regulator;
	77
	78	struct s5pv210_dvs_conf {
	79	int arm_volt; /* uV */
	80	int int_volt; /* uV */
	81	};
	82
	83	static const int arm_volt_max = 1350000;
	84	static const int int_volt_max = 1250000;
	85
	86	static struct s5pv210_dvs_conf dvs_conf[] = {
	87	[L0] = {
	88	.arm_volt = 1250000,
	89	.int_volt = 1100000,
	90	},
	91	[L1] = {
	92	.arm_volt = 1200000,
	93	.int_volt = 1100000,
	94	},
	95	[L2] = {
	96	.arm_volt = 1050000,
	97	.int_volt = 1100000,
	98	},
	99	[L3] = {
	100	.arm_volt = 950000,
	101	.int_volt = 1100000,
	102	},
	103	[L4] = {
	104	.arm_volt = 950000,
	105	.int_volt = 1000000,
	106	},
	107	};
	108
83efc743 JL	109	static u32 clkdiv_val[5][11] = {
	110	/*
	111	* Clock divider value for following
	112	* { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
	113	* HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
	114	* ONEDRAM, MFC, G3D }
	115	*/
	116
	117	/* L0 : [1000/200/100][166/83][133/66][200/200] */
	118	{0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
	119
	120	/* L1 : [800/200/100][166/83][133/66][200/200] */
	121	{0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
	122
	123	/* L2 : [400/200/100][166/83][133/66][200/200] */
	124	{1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
	125
	126	/* L3 : [200/200/100][166/83][133/66][200/200] */
	127	{3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
	128
	129	/* L4 : [100/100/100][83/83][66/66][100/100] */
	130	{7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
	131	};
	132
	133	/*
	134	* This function set DRAM refresh counter
	135	* accoriding to operating frequency of DRAM
	136	* ch: DMC port number 0 or 1
	137	* freq: Operating frequency of DRAM(KHz)
	138	*/
	139	static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
	140	{
	141	unsigned long tmp, tmp1;
	142	void __iomem *reg = NULL;
	143
d62fa311	144	if (ch == DMC0) {
83efc743	145	reg = (S5P_VA_DMC0 + 0x30);
d62fa311	146	} else if (ch == DMC1) {
83efc743	147	reg = (S5P_VA_DMC1 + 0x30);
d62fa311	148	} else {
83efc743	149	printk(KERN_ERR "Cannot find DMC port\n");
d62fa311 JC	150	return;
d62fa311 JC	151	}
83efc743 JL	152
	153	/* Find current DRAM frequency */
	154	tmp = s5pv210_dram_conf[ch].freq;
	155
	156	do_div(tmp, freq);
	157
	158	tmp1 = s5pv210_dram_conf[ch].refresh;
	159
	160	do_div(tmp1, tmp);
	161
	162	__raw_writel(tmp1, reg);
	163	}
	164
9c0ebcf7	165	static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
83efc743 JL	166	{
83efc743 JL	167	unsigned long reg;
9c0ebcf7	168	unsigned int priv_index;
83efc743 JL	169	unsigned int pll_changing = 0;
83efc743 JL	170	unsigned int bus_speed_changing = 0;
d4019f0a	171	unsigned int old_freq, new_freq;
e8b4c198 JC	172	int arm_volt, int_volt;
e8b4c198 JC	173	int ret = 0;
83efc743	174
5b02b779 AH	175	mutex_lock(&set_freq_lock);
5b02b779 AH	176
90d5d0a1	177	if (no_cpufreq_access) {
1ef546f2 PB	178	pr_err("Denied access to %s as it is disabled temporarily\n",
1ef546f2 PB	179	__func__);
5b02b779 AH	180	ret = -EINVAL;
5b02b779 AH	181	goto exit;
90d5d0a1 HK	182	}
90d5d0a1 HK	183
652ed95d	184	old_freq = policy->cur;
d4019f0a	185	new_freq = s5pv210_freq_table[index].frequency;
83efc743	186
83efc743 JL	187	/* Finding current running level index */
83efc743 JL	188	if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
d4019f0a	189	old_freq, CPUFREQ_RELATION_H,
9c0ebcf7	190	&priv_index)) {
5b02b779 AH	191	ret = -EINVAL;
	192	goto exit;
	193	}
83efc743	194
e8b4c198 JC	195	arm_volt = dvs_conf[index].arm_volt;
e8b4c198 JC	196	int_volt = dvs_conf[index].int_volt;
83efc743	197
d4019f0a	198	if (new_freq > old_freq) {
e8b4c198 JC	199	ret = regulator_set_voltage(arm_regulator,
	200	arm_volt, arm_volt_max);
	201	if (ret)
5b02b779	202	goto exit;
e8b4c198 JC	203
	204	ret = regulator_set_voltage(int_regulator,
	205	int_volt, int_volt_max);
	206	if (ret)
5b02b779	207	goto exit;
83efc743 JL	208	}
	209
	210	/* Check if there need to change PLL */
	211	if ((index == L0) \|\| (priv_index == L0))
	212	pll_changing = 1;
	213
	214	/* Check if there need to change System bus clock */
	215	if ((index == L4) \|\| (priv_index == L4))
	216	bus_speed_changing = 1;
	217
	218	if (bus_speed_changing) {
	219	/*
	220	* Reconfigure DRAM refresh counter value for minimum
	221	* temporary clock while changing divider.
	222	* expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
	223	*/
	224	if (pll_changing)
	225	s5pv210_set_refresh(DMC1, 83000);
	226	else
	227	s5pv210_set_refresh(DMC1, 100000);
	228
	229	s5pv210_set_refresh(DMC0, 83000);
	230	}
	231
	232	/*
	233	* APLL should be changed in this level
	234	* APLL -> MPLL(for stable transition) -> APLL
	235	* Some clock source's clock API are not prepared.
	236	* Do not use clock API in below code.
	237	*/
	238	if (pll_changing) {
	239	/*
	240	* 1. Temporary Change divider for MFC and G3D
	241	* SCLKA2M(200/1=200)->(200/4=50)Mhz
	242	*/
	243	reg = __raw_readl(S5P_CLK_DIV2);
	244	reg &= ~(S5P_CLKDIV2_G3D_MASK \| S5P_CLKDIV2_MFC_MASK);
	245	reg \|= (3 << S5P_CLKDIV2_G3D_SHIFT) \|
	246	(3 << S5P_CLKDIV2_MFC_SHIFT);
	247	__raw_writel(reg, S5P_CLK_DIV2);
	248
	249	/* For MFC, G3D dividing */
	250	do {
	251	reg = __raw_readl(S5P_CLKDIV_STAT0);
	252	} while (reg & ((1 << 16) \| (1 << 17)));
	253
	254	/*
	255	* 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
	256	* (200/4=50)->(667/4=166)Mhz
	257	*/
	258	reg = __raw_readl(S5P_CLK_SRC2);
	259	reg &= ~(S5P_CLKSRC2_G3D_MASK \| S5P_CLKSRC2_MFC_MASK);
	260	reg \|= (1 << S5P_CLKSRC2_G3D_SHIFT) \|
	261	(1 << S5P_CLKSRC2_MFC_SHIFT);
	262	__raw_writel(reg, S5P_CLK_SRC2);
	263
	264	do {
	265	reg = __raw_readl(S5P_CLKMUX_STAT1);
	266	} while (reg & ((1 << 7) \| (1 << 3)));
	267
	268	/*
	269	* 3. DMC1 refresh count for 133Mhz if (index == L4) is
	270	* true refresh counter is already programed in upper
	271	* code. 0x287@83Mhz
272	*/
273	if (!bus_speed_changing)
274	s5pv210_set_refresh(DMC1, 133000);
275
276	/* 4. SCLKAPLL -> SCLKMPLL */
277	reg = __raw_readl(S5P_CLK_SRC0);
278	reg &= ~(S5P_CLKSRC0_MUX200_MASK);
279	reg \|= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
280	__raw_writel(reg, S5P_CLK_SRC0);
281
282	do {
283	reg = __raw_readl(S5P_CLKMUX_STAT0);
284	} while (reg & (0x1 << 18));
285
286	}
287
288	/* Change divider */
289	reg = __raw_readl(S5P_CLK_DIV0);
290
291	reg &= ~(S5P_CLKDIV0_APLL_MASK \| S5P_CLKDIV0_A2M_MASK \|
292	S5P_CLKDIV0_HCLK200_MASK \| S5P_CLKDIV0_PCLK100_MASK \|
293	S5P_CLKDIV0_HCLK166_MASK \| S5P_CLKDIV0_PCLK83_MASK \|
294	S5P_CLKDIV0_HCLK133_MASK \| S5P_CLKDIV0_PCLK66_MASK);
295
296	reg \|= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) \|
297	(clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) \|
298	(clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) \|
299	(clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) \|
300	(clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) \|
301	(clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) \|
302	(clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) \|
303	(clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
304
305	__raw_writel(reg, S5P_CLK_DIV0);
306
307	do {
308	reg = __raw_readl(S5P_CLKDIV_STAT0);
309	} while (reg & 0xff);
310
311	/* ARM MCS value changed */
312	reg = __raw_readl(S5P_ARM_MCS_CON);
313	reg &= ~0x3;
314	if (index >= L3)
315	reg \|= 0x3;
316	else
317	reg \|= 0x1;
318
319	__raw_writel(reg, S5P_ARM_MCS_CON);
320
321	if (pll_changing) {
322	/* 5. Set Lock time = 30us24Mhz = 0x2cf /
323	__raw_writel(0x2cf, S5P_APLL_LOCK);
324
325	/*
326	* 6. Turn on APLL
327	* 6-1. Set PMS values
328	* 6-2. Wait untile the PLL is locked
329	*/
330	if (index == L0)
331	__raw_writel(APLL_VAL_1000, S5P_APLL_CON);
332	else
333	__raw_writel(APLL_VAL_800, S5P_APLL_CON);
334
335	do {
336	reg = __raw_readl(S5P_APLL_CON);
337	} while (!(reg & (0x1 << 29)));
338
339	/*
340	* 7. Change souce clock from SCLKMPLL(667Mhz)
341	* to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
342	* (667/4=166)->(200/4=50)Mhz
343	*/
344	reg = __raw_readl(S5P_CLK_SRC2);
345	reg &= ~(S5P_CLKSRC2_G3D_MASK \| S5P_CLKSRC2_MFC_MASK);
346	reg \|= (0 << S5P_CLKSRC2_G3D_SHIFT) \|
347	(0 << S5P_CLKSRC2_MFC_SHIFT);
348	__raw_writel(reg, S5P_CLK_SRC2);
349
350	do {
351	reg = __raw_readl(S5P_CLKMUX_STAT1);
352	} while (reg & ((1 << 7) \| (1 << 3)));
353
354	/*
355	* 8. Change divider for MFC and G3D
356	* (200/4=50)->(200/1=200)Mhz
357	*/
358	reg = __raw_readl(S5P_CLK_DIV2);
359	reg &= ~(S5P_CLKDIV2_G3D_MASK \| S5P_CLKDIV2_MFC_MASK);
360	reg \|= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) \|
361	(clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
362	__raw_writel(reg, S5P_CLK_DIV2);
363
364	/* For MFC, G3D dividing */
365	do {
366	reg = __raw_readl(S5P_CLKDIV_STAT0);
367	} while (reg & ((1 << 16) \| (1 << 17)));
368
369	/* 9. Change MPLL to APLL in MSYS_MUX */
370	reg = __raw_readl(S5P_CLK_SRC0);
371	reg &= ~(S5P_CLKSRC0_MUX200_MASK);
372	reg \|= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
373	__raw_writel(reg, S5P_CLK_SRC0);
374
375	do {
376	reg = __raw_readl(S5P_CLKMUX_STAT0);
377	} while (reg & (0x1 << 18));
378
379	/*
380	* 10. DMC1 refresh counter
381	* L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
382	* Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
383	*/
384	if (!bus_speed_changing)
385	s5pv210_set_refresh(DMC1, 200000);
386	}
387
388	/*
389	* L4 level need to change memory bus speed, hence onedram clock divier
390	* and memory refresh parameter should be changed
391	*/
392	if (bus_speed_changing) {
393	reg = __raw_readl(S5P_CLK_DIV6);
394	reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
395	reg \|= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
396	__raw_writel(reg, S5P_CLK_DIV6);
397
398	do {
399	reg = __raw_readl(S5P_CLKDIV_STAT1);
400	} while (reg & (1 << 15));
401
402	/* Reconfigure DRAM refresh counter value */
403	if (index != L4) {
404	/*
405	* DMC0 : 166Mhz
406	* DMC1 : 200Mhz
407	*/
408	s5pv210_set_refresh(DMC0, 166000);
409	s5pv210_set_refresh(DMC1, 200000);
410	} else {
411	/*
412	* DMC0 : 83Mhz
413	* DMC1 : 100Mhz
414	*/
415	s5pv210_set_refresh(DMC0, 83000);
416	s5pv210_set_refresh(DMC1, 100000);
417	}
418	}
419
d4019f0a	420	if (new_freq < old_freq) {
e8b4c198 JC	421	regulator_set_voltage(int_regulator,
	422	int_volt, int_volt_max);
	423
	424	regulator_set_voltage(arm_regulator,
	425	arm_volt, arm_volt_max);
83efc743 JL	426	}
83efc743 JL	427
83efc743 JL	428	printk(KERN_DEBUG "Perf changed[L%d]\n", index);
83efc743 JL	429
5b02b779 AH	430	exit:
	431	mutex_unlock(&set_freq_lock);
	432	return ret;
83efc743 JL	433	}
83efc743 JL	434
83efc743 JL	435	static int check_mem_type(void __iomem *dmc_reg)
	436	{
	437	unsigned long val;
	438
	439	val = __raw_readl(dmc_reg + 0x4);
	440	val = (val & (0xf << 8));
	441
	442	return val >> 8;
	443	}
	444
	445	static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
	446	{
	447	unsigned long mem_type;
4911ca10	448	int ret;
83efc743	449
652ed95d VK	450	policy->clk = clk_get(NULL, "armclk");
	451	if (IS_ERR(policy->clk))
	452	return PTR_ERR(policy->clk);
83efc743 JL	453
	454	dmc0_clk = clk_get(NULL, "sclk_dmc0");
	455	if (IS_ERR(dmc0_clk)) {
4911ca10 JL	456	ret = PTR_ERR(dmc0_clk);
4911ca10 JL	457	goto out_dmc0;
83efc743 JL	458	}
	459
	460	dmc1_clk = clk_get(NULL, "hclk_msys");
	461	if (IS_ERR(dmc1_clk)) {
4911ca10 JL	462	ret = PTR_ERR(dmc1_clk);
4911ca10 JL	463	goto out_dmc1;
83efc743 JL	464	}
83efc743 JL	465
4911ca10 JL	466	if (policy->cpu != 0) {
	467	ret = -EINVAL;
	468	goto out_dmc1;
	469	}
83efc743 JL	470
	471	/*
	472	* check_mem_type : This driver only support LPDDR & LPDDR2.
	473	* other memory type is not supported.
	474	*/
	475	mem_type = check_mem_type(S5P_VA_DMC0);
	476
	477	if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
	478	printk(KERN_ERR "CPUFreq doesn't support this memory type\n");
4911ca10 JL	479	ret = -EINVAL;
4911ca10 JL	480	goto out_dmc1;
83efc743 JL	481	}
	482
	483	/* Find current refresh counter and frequency each DMC */
	484	s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000);
	485	s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
	486
	487	s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000);
	488	s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
	489
59625ba3	490	policy->suspend_freq = SLEEP_FREQ;
c3d7d87d	491	return cpufreq_generic_init(policy, s5pv210_freq_table, 40000);
4911ca10 JL	492
	493	out_dmc1:
	494	clk_put(dmc0_clk);
	495	out_dmc0:
652ed95d	496	clk_put(policy->clk);
4911ca10	497	return ret;
83efc743 JL	498	}
83efc743 JL	499
fe7f1bcb HK	500	static int s5pv210_cpufreq_reboot_notifier_event(struct notifier_block *this,
	501	unsigned long event, void *ptr)
	502	{
	503	int ret;
	504
9c0ebcf7	505	ret = cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ, 0);
fe7f1bcb HK	506	if (ret < 0)
	507	return NOTIFY_BAD;
	508
9c0ebcf7	509	no_cpufreq_access = true;
fe7f1bcb HK	510	return NOTIFY_DONE;
	511	}
	512
83efc743	513	static struct cpufreq_driver s5pv210_driver = {
ae6b4271	514	.flags = CPUFREQ_STICKY \| CPUFREQ_NEED_INITIAL_FREQ_CHECK,
9c3c6e33	515	.verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7	516	.target_index = s5pv210_target,
652ed95d	517	.get = cpufreq_generic_get,
83efc743 JL	518	.init = s5pv210_cpu_init,
	519	.name = "s5pv210",
	520	#ifdef CONFIG_PM
59625ba3 VK	521	.suspend = cpufreq_generic_suspend,
59625ba3 VK	522	.resume = cpufreq_generic_suspend, /* We need to set SLEEP FREQ again */
83efc743 JL	523	#endif
	524	};
	525
fe7f1bcb HK	526	static struct notifier_block s5pv210_cpufreq_reboot_notifier = {
	527	.notifier_call = s5pv210_cpufreq_reboot_notifier_event,
	528	};
	529
83efc743 JL	530	static int __init s5pv210_cpufreq_init(void)
83efc743 JL	531	{
e8b4c198 JC	532	arm_regulator = regulator_get(NULL, "vddarm");
	533	if (IS_ERR(arm_regulator)) {
	534	pr_err("failed to get regulator vddarm");
	535	return PTR_ERR(arm_regulator);
	536	}
	537
	538	int_regulator = regulator_get(NULL, "vddint");
	539	if (IS_ERR(int_regulator)) {
	540	pr_err("failed to get regulator vddint");
	541	regulator_put(arm_regulator);
	542	return PTR_ERR(int_regulator);
	543	}
	544
fe7f1bcb	545	register_reboot_notifier(&s5pv210_cpufreq_reboot_notifier);
405e6d6d	546
83efc743 JL	547	return cpufreq_register_driver(&s5pv210_driver);
	548	}
	549
	550	late_initcall(s5pv210_cpufreq_init);