Commit | Line | Data |
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f7d77079 | 1 | /* |
83efc743 JL |
2 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. |
3 | * http://www.samsung.com | |
4 | * | |
5 | * CPU frequency scaling for S5PC110/S5PV210 | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
1c5864e2 JP |
12 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
13 | ||
83efc743 JL |
14 | #include <linux/types.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/clk.h> | |
19 | #include <linux/io.h> | |
20 | #include <linux/cpufreq.h> | |
6d4ed0f4 TF |
21 | #include <linux/of.h> |
22 | #include <linux/of_address.h> | |
23 | #include <linux/platform_device.h> | |
fe7f1bcb | 24 | #include <linux/reboot.h> |
e8b4c198 | 25 | #include <linux/regulator/consumer.h> |
83efc743 | 26 | |
6d4ed0f4 TF |
27 | static void __iomem *clk_base; |
28 | static void __iomem *dmc_base[2]; | |
29 | ||
30 | #define S5P_CLKREG(x) (clk_base + (x)) | |
31 | ||
32 | #define S5P_APLL_LOCK S5P_CLKREG(0x00) | |
33 | #define S5P_APLL_CON S5P_CLKREG(0x100) | |
34 | #define S5P_CLK_SRC0 S5P_CLKREG(0x200) | |
35 | #define S5P_CLK_SRC2 S5P_CLKREG(0x208) | |
36 | #define S5P_CLK_DIV0 S5P_CLKREG(0x300) | |
37 | #define S5P_CLK_DIV2 S5P_CLKREG(0x308) | |
38 | #define S5P_CLK_DIV6 S5P_CLKREG(0x318) | |
39 | #define S5P_CLKDIV_STAT0 S5P_CLKREG(0x1000) | |
40 | #define S5P_CLKDIV_STAT1 S5P_CLKREG(0x1004) | |
41 | #define S5P_CLKMUX_STAT0 S5P_CLKREG(0x1100) | |
42 | #define S5P_CLKMUX_STAT1 S5P_CLKREG(0x1104) | |
43 | ||
44 | #define S5P_ARM_MCS_CON S5P_CLKREG(0x6100) | |
45 | ||
46 | /* CLKSRC0 */ | |
47 | #define S5P_CLKSRC0_MUX200_SHIFT (16) | |
48 | #define S5P_CLKSRC0_MUX200_MASK (0x1 << S5P_CLKSRC0_MUX200_SHIFT) | |
49 | #define S5P_CLKSRC0_MUX166_MASK (0x1<<20) | |
50 | #define S5P_CLKSRC0_MUX133_MASK (0x1<<24) | |
51 | ||
52 | /* CLKSRC2 */ | |
53 | #define S5P_CLKSRC2_G3D_SHIFT (0) | |
54 | #define S5P_CLKSRC2_G3D_MASK (0x3 << S5P_CLKSRC2_G3D_SHIFT) | |
55 | #define S5P_CLKSRC2_MFC_SHIFT (4) | |
56 | #define S5P_CLKSRC2_MFC_MASK (0x3 << S5P_CLKSRC2_MFC_SHIFT) | |
57 | ||
58 | /* CLKDIV0 */ | |
59 | #define S5P_CLKDIV0_APLL_SHIFT (0) | |
60 | #define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT) | |
61 | #define S5P_CLKDIV0_A2M_SHIFT (4) | |
62 | #define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT) | |
63 | #define S5P_CLKDIV0_HCLK200_SHIFT (8) | |
64 | #define S5P_CLKDIV0_HCLK200_MASK (0x7 << S5P_CLKDIV0_HCLK200_SHIFT) | |
65 | #define S5P_CLKDIV0_PCLK100_SHIFT (12) | |
66 | #define S5P_CLKDIV0_PCLK100_MASK (0x7 << S5P_CLKDIV0_PCLK100_SHIFT) | |
67 | #define S5P_CLKDIV0_HCLK166_SHIFT (16) | |
68 | #define S5P_CLKDIV0_HCLK166_MASK (0xF << S5P_CLKDIV0_HCLK166_SHIFT) | |
69 | #define S5P_CLKDIV0_PCLK83_SHIFT (20) | |
70 | #define S5P_CLKDIV0_PCLK83_MASK (0x7 << S5P_CLKDIV0_PCLK83_SHIFT) | |
71 | #define S5P_CLKDIV0_HCLK133_SHIFT (24) | |
72 | #define S5P_CLKDIV0_HCLK133_MASK (0xF << S5P_CLKDIV0_HCLK133_SHIFT) | |
73 | #define S5P_CLKDIV0_PCLK66_SHIFT (28) | |
74 | #define S5P_CLKDIV0_PCLK66_MASK (0x7 << S5P_CLKDIV0_PCLK66_SHIFT) | |
75 | ||
76 | /* CLKDIV2 */ | |
77 | #define S5P_CLKDIV2_G3D_SHIFT (0) | |
78 | #define S5P_CLKDIV2_G3D_MASK (0xF << S5P_CLKDIV2_G3D_SHIFT) | |
79 | #define S5P_CLKDIV2_MFC_SHIFT (4) | |
80 | #define S5P_CLKDIV2_MFC_MASK (0xF << S5P_CLKDIV2_MFC_SHIFT) | |
81 | ||
82 | /* CLKDIV6 */ | |
83 | #define S5P_CLKDIV6_ONEDRAM_SHIFT (28) | |
84 | #define S5P_CLKDIV6_ONEDRAM_MASK (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT) | |
83efc743 | 85 | |
83efc743 JL |
86 | static struct clk *dmc0_clk; |
87 | static struct clk *dmc1_clk; | |
5b02b779 | 88 | static DEFINE_MUTEX(set_freq_lock); |
83efc743 JL |
89 | |
90 | /* APLL M,P,S values for 1G/800Mhz */ | |
91 | #define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1) | |
92 | #define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1) | |
93 | ||
405e6d6d HK |
94 | /* Use 800MHz when entering sleep mode */ |
95 | #define SLEEP_FREQ (800 * 1000) | |
96 | ||
9c0ebcf7 | 97 | /* Tracks if cpu freqency can be updated anymore */ |
90d5d0a1 HK |
98 | static bool no_cpufreq_access; |
99 | ||
83efc743 JL |
100 | /* |
101 | * DRAM configurations to calculate refresh counter for changing | |
102 | * frequency of memory. | |
103 | */ | |
104 | struct dram_conf { | |
105 | unsigned long freq; /* HZ */ | |
106 | unsigned long refresh; /* DRAM refresh counter * 1000 */ | |
107 | }; | |
108 | ||
109 | /* DRAM configuration (DMC0 and DMC1) */ | |
110 | static struct dram_conf s5pv210_dram_conf[2]; | |
111 | ||
112 | enum perf_level { | |
113 | L0, L1, L2, L3, L4, | |
114 | }; | |
115 | ||
116 | enum s5pv210_mem_type { | |
117 | LPDDR = 0x1, | |
118 | LPDDR2 = 0x2, | |
119 | DDR2 = 0x4, | |
120 | }; | |
121 | ||
122 | enum s5pv210_dmc_port { | |
123 | DMC0 = 0, | |
124 | DMC1, | |
125 | }; | |
126 | ||
127 | static struct cpufreq_frequency_table s5pv210_freq_table[] = { | |
7f4b0461 VK |
128 | {0, L0, 1000*1000}, |
129 | {0, L1, 800*1000}, | |
130 | {0, L2, 400*1000}, | |
131 | {0, L3, 200*1000}, | |
132 | {0, L4, 100*1000}, | |
133 | {0, 0, CPUFREQ_TABLE_END}, | |
83efc743 JL |
134 | }; |
135 | ||
e8b4c198 JC |
136 | static struct regulator *arm_regulator; |
137 | static struct regulator *int_regulator; | |
138 | ||
139 | struct s5pv210_dvs_conf { | |
140 | int arm_volt; /* uV */ | |
141 | int int_volt; /* uV */ | |
142 | }; | |
143 | ||
144 | static const int arm_volt_max = 1350000; | |
145 | static const int int_volt_max = 1250000; | |
146 | ||
147 | static struct s5pv210_dvs_conf dvs_conf[] = { | |
148 | [L0] = { | |
149 | .arm_volt = 1250000, | |
150 | .int_volt = 1100000, | |
151 | }, | |
152 | [L1] = { | |
153 | .arm_volt = 1200000, | |
154 | .int_volt = 1100000, | |
155 | }, | |
156 | [L2] = { | |
157 | .arm_volt = 1050000, | |
158 | .int_volt = 1100000, | |
159 | }, | |
160 | [L3] = { | |
161 | .arm_volt = 950000, | |
162 | .int_volt = 1100000, | |
163 | }, | |
164 | [L4] = { | |
165 | .arm_volt = 950000, | |
166 | .int_volt = 1000000, | |
167 | }, | |
168 | }; | |
169 | ||
83efc743 JL |
170 | static u32 clkdiv_val[5][11] = { |
171 | /* | |
172 | * Clock divider value for following | |
173 | * { APLL, A2M, HCLK_MSYS, PCLK_MSYS, | |
174 | * HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS, | |
175 | * ONEDRAM, MFC, G3D } | |
176 | */ | |
177 | ||
178 | /* L0 : [1000/200/100][166/83][133/66][200/200] */ | |
179 | {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0}, | |
180 | ||
181 | /* L1 : [800/200/100][166/83][133/66][200/200] */ | |
182 | {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0}, | |
183 | ||
184 | /* L2 : [400/200/100][166/83][133/66][200/200] */ | |
185 | {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0}, | |
186 | ||
187 | /* L3 : [200/200/100][166/83][133/66][200/200] */ | |
188 | {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0}, | |
189 | ||
190 | /* L4 : [100/100/100][83/83][66/66][100/100] */ | |
191 | {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0}, | |
192 | }; | |
193 | ||
194 | /* | |
195 | * This function set DRAM refresh counter | |
196 | * accoriding to operating frequency of DRAM | |
197 | * ch: DMC port number 0 or 1 | |
198 | * freq: Operating frequency of DRAM(KHz) | |
199 | */ | |
200 | static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq) | |
201 | { | |
202 | unsigned long tmp, tmp1; | |
203 | void __iomem *reg = NULL; | |
204 | ||
d62fa311 | 205 | if (ch == DMC0) { |
6d4ed0f4 | 206 | reg = (dmc_base[0] + 0x30); |
d62fa311 | 207 | } else if (ch == DMC1) { |
6d4ed0f4 | 208 | reg = (dmc_base[1] + 0x30); |
d62fa311 | 209 | } else { |
b49c22a6 | 210 | pr_err("Cannot find DMC port\n"); |
d62fa311 JC |
211 | return; |
212 | } | |
83efc743 JL |
213 | |
214 | /* Find current DRAM frequency */ | |
215 | tmp = s5pv210_dram_conf[ch].freq; | |
216 | ||
d7e53e35 | 217 | tmp /= freq; |
83efc743 JL |
218 | |
219 | tmp1 = s5pv210_dram_conf[ch].refresh; | |
220 | ||
d7e53e35 | 221 | tmp1 /= tmp; |
83efc743 | 222 | |
187364b6 | 223 | writel_relaxed(tmp1, reg); |
83efc743 JL |
224 | } |
225 | ||
9c0ebcf7 | 226 | static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index) |
83efc743 JL |
227 | { |
228 | unsigned long reg; | |
9c0ebcf7 | 229 | unsigned int priv_index; |
83efc743 JL |
230 | unsigned int pll_changing = 0; |
231 | unsigned int bus_speed_changing = 0; | |
d4019f0a | 232 | unsigned int old_freq, new_freq; |
e8b4c198 JC |
233 | int arm_volt, int_volt; |
234 | int ret = 0; | |
83efc743 | 235 | |
5b02b779 AH |
236 | mutex_lock(&set_freq_lock); |
237 | ||
90d5d0a1 | 238 | if (no_cpufreq_access) { |
1ef546f2 PB |
239 | pr_err("Denied access to %s as it is disabled temporarily\n", |
240 | __func__); | |
5b02b779 AH |
241 | ret = -EINVAL; |
242 | goto exit; | |
90d5d0a1 HK |
243 | } |
244 | ||
652ed95d | 245 | old_freq = policy->cur; |
d4019f0a | 246 | new_freq = s5pv210_freq_table[index].frequency; |
83efc743 | 247 | |
83efc743 | 248 | /* Finding current running level index */ |
82577360 | 249 | priv_index = cpufreq_table_find_index_h(policy, old_freq); |
83efc743 | 250 | |
e8b4c198 JC |
251 | arm_volt = dvs_conf[index].arm_volt; |
252 | int_volt = dvs_conf[index].int_volt; | |
83efc743 | 253 | |
d4019f0a | 254 | if (new_freq > old_freq) { |
e8b4c198 JC |
255 | ret = regulator_set_voltage(arm_regulator, |
256 | arm_volt, arm_volt_max); | |
257 | if (ret) | |
5b02b779 | 258 | goto exit; |
e8b4c198 JC |
259 | |
260 | ret = regulator_set_voltage(int_regulator, | |
261 | int_volt, int_volt_max); | |
262 | if (ret) | |
5b02b779 | 263 | goto exit; |
83efc743 JL |
264 | } |
265 | ||
266 | /* Check if there need to change PLL */ | |
267 | if ((index == L0) || (priv_index == L0)) | |
268 | pll_changing = 1; | |
269 | ||
270 | /* Check if there need to change System bus clock */ | |
271 | if ((index == L4) || (priv_index == L4)) | |
272 | bus_speed_changing = 1; | |
273 | ||
274 | if (bus_speed_changing) { | |
275 | /* | |
276 | * Reconfigure DRAM refresh counter value for minimum | |
277 | * temporary clock while changing divider. | |
278 | * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287 | |
279 | */ | |
280 | if (pll_changing) | |
281 | s5pv210_set_refresh(DMC1, 83000); | |
282 | else | |
283 | s5pv210_set_refresh(DMC1, 100000); | |
284 | ||
285 | s5pv210_set_refresh(DMC0, 83000); | |
286 | } | |
287 | ||
288 | /* | |
289 | * APLL should be changed in this level | |
290 | * APLL -> MPLL(for stable transition) -> APLL | |
291 | * Some clock source's clock API are not prepared. | |
292 | * Do not use clock API in below code. | |
293 | */ | |
294 | if (pll_changing) { | |
295 | /* | |
296 | * 1. Temporary Change divider for MFC and G3D | |
297 | * SCLKA2M(200/1=200)->(200/4=50)Mhz | |
298 | */ | |
187364b6 | 299 | reg = readl_relaxed(S5P_CLK_DIV2); |
83efc743 JL |
300 | reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK); |
301 | reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) | | |
302 | (3 << S5P_CLKDIV2_MFC_SHIFT); | |
187364b6 | 303 | writel_relaxed(reg, S5P_CLK_DIV2); |
83efc743 JL |
304 | |
305 | /* For MFC, G3D dividing */ | |
306 | do { | |
187364b6 | 307 | reg = readl_relaxed(S5P_CLKDIV_STAT0); |
83efc743 JL |
308 | } while (reg & ((1 << 16) | (1 << 17))); |
309 | ||
310 | /* | |
311 | * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX | |
312 | * (200/4=50)->(667/4=166)Mhz | |
313 | */ | |
187364b6 | 314 | reg = readl_relaxed(S5P_CLK_SRC2); |
83efc743 JL |
315 | reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK); |
316 | reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) | | |
317 | (1 << S5P_CLKSRC2_MFC_SHIFT); | |
187364b6 | 318 | writel_relaxed(reg, S5P_CLK_SRC2); |
83efc743 JL |
319 | |
320 | do { | |
187364b6 | 321 | reg = readl_relaxed(S5P_CLKMUX_STAT1); |
83efc743 JL |
322 | } while (reg & ((1 << 7) | (1 << 3))); |
323 | ||
324 | /* | |
325 | * 3. DMC1 refresh count for 133Mhz if (index == L4) is | |
326 | * true refresh counter is already programed in upper | |
327 | * code. 0x287@83Mhz | |
328 | */ | |
329 | if (!bus_speed_changing) | |
330 | s5pv210_set_refresh(DMC1, 133000); | |
331 | ||
332 | /* 4. SCLKAPLL -> SCLKMPLL */ | |
187364b6 | 333 | reg = readl_relaxed(S5P_CLK_SRC0); |
83efc743 JL |
334 | reg &= ~(S5P_CLKSRC0_MUX200_MASK); |
335 | reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT); | |
187364b6 | 336 | writel_relaxed(reg, S5P_CLK_SRC0); |
83efc743 JL |
337 | |
338 | do { | |
187364b6 | 339 | reg = readl_relaxed(S5P_CLKMUX_STAT0); |
83efc743 JL |
340 | } while (reg & (0x1 << 18)); |
341 | ||
342 | } | |
343 | ||
344 | /* Change divider */ | |
187364b6 | 345 | reg = readl_relaxed(S5P_CLK_DIV0); |
83efc743 JL |
346 | |
347 | reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK | | |
348 | S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK | | |
349 | S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK | | |
350 | S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK); | |
351 | ||
352 | reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) | | |
353 | (clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) | | |
354 | (clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) | | |
355 | (clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) | | |
356 | (clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) | | |
357 | (clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) | | |
358 | (clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) | | |
359 | (clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT)); | |
360 | ||
187364b6 | 361 | writel_relaxed(reg, S5P_CLK_DIV0); |
83efc743 JL |
362 | |
363 | do { | |
187364b6 | 364 | reg = readl_relaxed(S5P_CLKDIV_STAT0); |
83efc743 JL |
365 | } while (reg & 0xff); |
366 | ||
367 | /* ARM MCS value changed */ | |
187364b6 | 368 | reg = readl_relaxed(S5P_ARM_MCS_CON); |
83efc743 JL |
369 | reg &= ~0x3; |
370 | if (index >= L3) | |
371 | reg |= 0x3; | |
372 | else | |
373 | reg |= 0x1; | |
374 | ||
187364b6 | 375 | writel_relaxed(reg, S5P_ARM_MCS_CON); |
83efc743 JL |
376 | |
377 | if (pll_changing) { | |
378 | /* 5. Set Lock time = 30us*24Mhz = 0x2cf */ | |
187364b6 | 379 | writel_relaxed(0x2cf, S5P_APLL_LOCK); |
83efc743 JL |
380 | |
381 | /* | |
382 | * 6. Turn on APLL | |
383 | * 6-1. Set PMS values | |
384 | * 6-2. Wait untile the PLL is locked | |
385 | */ | |
386 | if (index == L0) | |
187364b6 | 387 | writel_relaxed(APLL_VAL_1000, S5P_APLL_CON); |
83efc743 | 388 | else |
187364b6 | 389 | writel_relaxed(APLL_VAL_800, S5P_APLL_CON); |
83efc743 JL |
390 | |
391 | do { | |
187364b6 | 392 | reg = readl_relaxed(S5P_APLL_CON); |
83efc743 JL |
393 | } while (!(reg & (0x1 << 29))); |
394 | ||
395 | /* | |
396 | * 7. Change souce clock from SCLKMPLL(667Mhz) | |
397 | * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX | |
398 | * (667/4=166)->(200/4=50)Mhz | |
399 | */ | |
187364b6 | 400 | reg = readl_relaxed(S5P_CLK_SRC2); |
83efc743 JL |
401 | reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK); |
402 | reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) | | |
403 | (0 << S5P_CLKSRC2_MFC_SHIFT); | |
187364b6 | 404 | writel_relaxed(reg, S5P_CLK_SRC2); |
83efc743 JL |
405 | |
406 | do { | |
187364b6 | 407 | reg = readl_relaxed(S5P_CLKMUX_STAT1); |
83efc743 JL |
408 | } while (reg & ((1 << 7) | (1 << 3))); |
409 | ||
410 | /* | |
411 | * 8. Change divider for MFC and G3D | |
412 | * (200/4=50)->(200/1=200)Mhz | |
413 | */ | |
187364b6 | 414 | reg = readl_relaxed(S5P_CLK_DIV2); |
83efc743 JL |
415 | reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK); |
416 | reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) | | |
417 | (clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT); | |
187364b6 | 418 | writel_relaxed(reg, S5P_CLK_DIV2); |
83efc743 JL |
419 | |
420 | /* For MFC, G3D dividing */ | |
421 | do { | |
187364b6 | 422 | reg = readl_relaxed(S5P_CLKDIV_STAT0); |
83efc743 JL |
423 | } while (reg & ((1 << 16) | (1 << 17))); |
424 | ||
425 | /* 9. Change MPLL to APLL in MSYS_MUX */ | |
187364b6 | 426 | reg = readl_relaxed(S5P_CLK_SRC0); |
83efc743 JL |
427 | reg &= ~(S5P_CLKSRC0_MUX200_MASK); |
428 | reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT); | |
187364b6 | 429 | writel_relaxed(reg, S5P_CLK_SRC0); |
83efc743 JL |
430 | |
431 | do { | |
187364b6 | 432 | reg = readl_relaxed(S5P_CLKMUX_STAT0); |
83efc743 JL |
433 | } while (reg & (0x1 << 18)); |
434 | ||
435 | /* | |
436 | * 10. DMC1 refresh counter | |
437 | * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c | |
438 | * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618 | |
439 | */ | |
440 | if (!bus_speed_changing) | |
441 | s5pv210_set_refresh(DMC1, 200000); | |
442 | } | |
443 | ||
444 | /* | |
445 | * L4 level need to change memory bus speed, hence onedram clock divier | |
446 | * and memory refresh parameter should be changed | |
447 | */ | |
448 | if (bus_speed_changing) { | |
187364b6 | 449 | reg = readl_relaxed(S5P_CLK_DIV6); |
83efc743 JL |
450 | reg &= ~S5P_CLKDIV6_ONEDRAM_MASK; |
451 | reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT); | |
187364b6 | 452 | writel_relaxed(reg, S5P_CLK_DIV6); |
83efc743 JL |
453 | |
454 | do { | |
187364b6 | 455 | reg = readl_relaxed(S5P_CLKDIV_STAT1); |
83efc743 JL |
456 | } while (reg & (1 << 15)); |
457 | ||
458 | /* Reconfigure DRAM refresh counter value */ | |
459 | if (index != L4) { | |
460 | /* | |
461 | * DMC0 : 166Mhz | |
462 | * DMC1 : 200Mhz | |
463 | */ | |
464 | s5pv210_set_refresh(DMC0, 166000); | |
465 | s5pv210_set_refresh(DMC1, 200000); | |
466 | } else { | |
467 | /* | |
468 | * DMC0 : 83Mhz | |
469 | * DMC1 : 100Mhz | |
470 | */ | |
471 | s5pv210_set_refresh(DMC0, 83000); | |
472 | s5pv210_set_refresh(DMC1, 100000); | |
473 | } | |
474 | } | |
475 | ||
d4019f0a | 476 | if (new_freq < old_freq) { |
e8b4c198 JC |
477 | regulator_set_voltage(int_regulator, |
478 | int_volt, int_volt_max); | |
479 | ||
480 | regulator_set_voltage(arm_regulator, | |
481 | arm_volt, arm_volt_max); | |
83efc743 JL |
482 | } |
483 | ||
83efc743 JL |
484 | printk(KERN_DEBUG "Perf changed[L%d]\n", index); |
485 | ||
5b02b779 AH |
486 | exit: |
487 | mutex_unlock(&set_freq_lock); | |
488 | return ret; | |
83efc743 JL |
489 | } |
490 | ||
83efc743 JL |
491 | static int check_mem_type(void __iomem *dmc_reg) |
492 | { | |
493 | unsigned long val; | |
494 | ||
187364b6 | 495 | val = readl_relaxed(dmc_reg + 0x4); |
83efc743 JL |
496 | val = (val & (0xf << 8)); |
497 | ||
498 | return val >> 8; | |
499 | } | |
500 | ||
dc268742 | 501 | static int s5pv210_cpu_init(struct cpufreq_policy *policy) |
83efc743 JL |
502 | { |
503 | unsigned long mem_type; | |
4911ca10 | 504 | int ret; |
83efc743 | 505 | |
652ed95d VK |
506 | policy->clk = clk_get(NULL, "armclk"); |
507 | if (IS_ERR(policy->clk)) | |
508 | return PTR_ERR(policy->clk); | |
83efc743 JL |
509 | |
510 | dmc0_clk = clk_get(NULL, "sclk_dmc0"); | |
511 | if (IS_ERR(dmc0_clk)) { | |
4911ca10 JL |
512 | ret = PTR_ERR(dmc0_clk); |
513 | goto out_dmc0; | |
83efc743 JL |
514 | } |
515 | ||
516 | dmc1_clk = clk_get(NULL, "hclk_msys"); | |
517 | if (IS_ERR(dmc1_clk)) { | |
4911ca10 JL |
518 | ret = PTR_ERR(dmc1_clk); |
519 | goto out_dmc1; | |
83efc743 JL |
520 | } |
521 | ||
4911ca10 JL |
522 | if (policy->cpu != 0) { |
523 | ret = -EINVAL; | |
524 | goto out_dmc1; | |
525 | } | |
83efc743 JL |
526 | |
527 | /* | |
528 | * check_mem_type : This driver only support LPDDR & LPDDR2. | |
529 | * other memory type is not supported. | |
530 | */ | |
6d4ed0f4 | 531 | mem_type = check_mem_type(dmc_base[0]); |
83efc743 JL |
532 | |
533 | if ((mem_type != LPDDR) && (mem_type != LPDDR2)) { | |
b49c22a6 | 534 | pr_err("CPUFreq doesn't support this memory type\n"); |
4911ca10 JL |
535 | ret = -EINVAL; |
536 | goto out_dmc1; | |
83efc743 JL |
537 | } |
538 | ||
539 | /* Find current refresh counter and frequency each DMC */ | |
187364b6 | 540 | s5pv210_dram_conf[0].refresh = (readl_relaxed(dmc_base[0] + 0x30) * 1000); |
83efc743 JL |
541 | s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk); |
542 | ||
187364b6 | 543 | s5pv210_dram_conf[1].refresh = (readl_relaxed(dmc_base[1] + 0x30) * 1000); |
83efc743 JL |
544 | s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk); |
545 | ||
59625ba3 | 546 | policy->suspend_freq = SLEEP_FREQ; |
c3d7d87d | 547 | return cpufreq_generic_init(policy, s5pv210_freq_table, 40000); |
4911ca10 JL |
548 | |
549 | out_dmc1: | |
550 | clk_put(dmc0_clk); | |
551 | out_dmc0: | |
652ed95d | 552 | clk_put(policy->clk); |
4911ca10 | 553 | return ret; |
83efc743 JL |
554 | } |
555 | ||
fe7f1bcb HK |
556 | static int s5pv210_cpufreq_reboot_notifier_event(struct notifier_block *this, |
557 | unsigned long event, void *ptr) | |
558 | { | |
559 | int ret; | |
560 | ||
9c0ebcf7 | 561 | ret = cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ, 0); |
fe7f1bcb HK |
562 | if (ret < 0) |
563 | return NOTIFY_BAD; | |
564 | ||
9c0ebcf7 | 565 | no_cpufreq_access = true; |
fe7f1bcb HK |
566 | return NOTIFY_DONE; |
567 | } | |
568 | ||
83efc743 | 569 | static struct cpufreq_driver s5pv210_driver = { |
ae6b4271 | 570 | .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
9c3c6e33 | 571 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 572 | .target_index = s5pv210_target, |
652ed95d | 573 | .get = cpufreq_generic_get, |
83efc743 JL |
574 | .init = s5pv210_cpu_init, |
575 | .name = "s5pv210", | |
59625ba3 VK |
576 | .suspend = cpufreq_generic_suspend, |
577 | .resume = cpufreq_generic_suspend, /* We need to set SLEEP FREQ again */ | |
83efc743 JL |
578 | }; |
579 | ||
fe7f1bcb HK |
580 | static struct notifier_block s5pv210_cpufreq_reboot_notifier = { |
581 | .notifier_call = s5pv210_cpufreq_reboot_notifier_event, | |
582 | }; | |
583 | ||
6d4ed0f4 | 584 | static int s5pv210_cpufreq_probe(struct platform_device *pdev) |
83efc743 | 585 | { |
6d4ed0f4 TF |
586 | struct device_node *np; |
587 | int id; | |
588 | ||
589 | /* | |
590 | * HACK: This is a temporary workaround to get access to clock | |
591 | * and DMC controller registers directly and remove static mappings | |
592 | * and dependencies on platform headers. It is necessary to enable | |
593 | * S5PV210 multi-platform support and will be removed together with | |
594 | * this whole driver as soon as S5PV210 gets migrated to use | |
bbcf0719 | 595 | * cpufreq-dt driver. |
6d4ed0f4 TF |
596 | */ |
597 | np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); | |
598 | if (!np) { | |
599 | pr_err("%s: failed to find clock controller DT node\n", | |
600 | __func__); | |
601 | return -ENODEV; | |
602 | } | |
603 | ||
604 | clk_base = of_iomap(np, 0); | |
605 | if (!clk_base) { | |
606 | pr_err("%s: failed to map clock registers\n", __func__); | |
607 | return -EFAULT; | |
608 | } | |
609 | ||
610 | for_each_compatible_node(np, NULL, "samsung,s5pv210-dmc") { | |
611 | id = of_alias_get_id(np, "dmc"); | |
612 | if (id < 0 || id >= ARRAY_SIZE(dmc_base)) { | |
613 | pr_err("%s: failed to get alias of dmc node '%s'\n", | |
614 | __func__, np->name); | |
615 | return id; | |
616 | } | |
617 | ||
618 | dmc_base[id] = of_iomap(np, 0); | |
619 | if (!dmc_base[id]) { | |
620 | pr_err("%s: failed to map dmc%d registers\n", | |
621 | __func__, id); | |
622 | return -EFAULT; | |
623 | } | |
624 | } | |
625 | ||
626 | for (id = 0; id < ARRAY_SIZE(dmc_base); ++id) { | |
627 | if (!dmc_base[id]) { | |
628 | pr_err("%s: failed to find dmc%d node\n", __func__, id); | |
629 | return -ENODEV; | |
630 | } | |
631 | } | |
632 | ||
e8b4c198 JC |
633 | arm_regulator = regulator_get(NULL, "vddarm"); |
634 | if (IS_ERR(arm_regulator)) { | |
1c5864e2 | 635 | pr_err("failed to get regulator vddarm\n"); |
e8b4c198 JC |
636 | return PTR_ERR(arm_regulator); |
637 | } | |
638 | ||
639 | int_regulator = regulator_get(NULL, "vddint"); | |
640 | if (IS_ERR(int_regulator)) { | |
1c5864e2 | 641 | pr_err("failed to get regulator vddint\n"); |
e8b4c198 JC |
642 | regulator_put(arm_regulator); |
643 | return PTR_ERR(int_regulator); | |
644 | } | |
645 | ||
fe7f1bcb | 646 | register_reboot_notifier(&s5pv210_cpufreq_reboot_notifier); |
405e6d6d | 647 | |
83efc743 JL |
648 | return cpufreq_register_driver(&s5pv210_driver); |
649 | } | |
650 | ||
6d4ed0f4 TF |
651 | static struct platform_driver s5pv210_cpufreq_platdrv = { |
652 | .driver = { | |
653 | .name = "s5pv210-cpufreq", | |
6d4ed0f4 TF |
654 | }, |
655 | .probe = s5pv210_cpufreq_probe, | |
656 | }; | |
5b64127e | 657 | builtin_platform_driver(s5pv210_cpufreq_platdrv); |