[deliverable/linux.git] / drivers / cpufreq / s5pv210-cpufreq.c

/*
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * CPU frequency scaling for S5PC110/S5PV210
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/cpufreq.h>
#include <linux/regulator/consumer.h>
#include <linux/suspend.h>

#include <mach/map.h>
#include <mach/regs-clock.h>

static struct clk *cpu_clk;
static struct clk *dmc0_clk;
static struct clk *dmc1_clk;
static struct cpufreq_freqs freqs;
static DEFINE_MUTEX(set_freq_lock);

/* APLL M,P,S values for 1G/800Mhz */
#define APLL_VAL_1000	((1 << 31) | (125 << 16) | (3 << 8) | 1)
#define APLL_VAL_800	((1 << 31) | (100 << 16) | (3 << 8) | 1)

/* Use 800MHz when entering sleep mode */
#define SLEEP_FREQ	(800 * 1000)

/*
 * relation has an additional symantics other than the standard of cpufreq
 * DISALBE_FURTHER_CPUFREQ: disable further access to target
 * ENABLE_FURTUER_CPUFREQ: enable access to target
 */
enum cpufreq_access {
	DISABLE_FURTHER_CPUFREQ = 0x10,
	ENABLE_FURTHER_CPUFREQ = 0x20,
};

static bool no_cpufreq_access;

/*
 * DRAM configurations to calculate refresh counter for changing
 * frequency of memory.
 */
struct dram_conf {
	unsigned long freq;	/* HZ */
	unsigned long refresh;	/* DRAM refresh counter * 1000 */
};

/* DRAM configuration (DMC0 and DMC1) */
static struct dram_conf s5pv210_dram_conf[2];

enum perf_level {
	L0, L1, L2, L3, L4,
};

enum s5pv210_mem_type {
	LPDDR	= 0x1,
	LPDDR2	= 0x2,
	DDR2	= 0x4,
};

enum s5pv210_dmc_port {
	DMC0 = 0,
	DMC1,
};

static struct cpufreq_frequency_table s5pv210_freq_table[] = {
	{L0, 1000*1000},
	{L1, 800*1000},
	{L2, 400*1000},
	{L3, 200*1000},
	{L4, 100*1000},
	{0, CPUFREQ_TABLE_END},
};

static struct regulator *arm_regulator;
static struct regulator *int_regulator;

struct s5pv210_dvs_conf {
	int arm_volt;	/* uV */
	int int_volt;	/* uV */
};

static const int arm_volt_max = 1350000;
static const int int_volt_max = 1250000;

static struct s5pv210_dvs_conf dvs_conf[] = {
	[L0] = {
		.arm_volt	= 1250000,
		.int_volt	= 1100000,
	},
	[L1] = {
		.arm_volt	= 1200000,
		.int_volt	= 1100000,
	},
	[L2] = {
		.arm_volt	= 1050000,
		.int_volt	= 1100000,
	},
	[L3] = {
		.arm_volt	= 950000,
		.int_volt	= 1100000,
	},
	[L4] = {
		.arm_volt	= 950000,
		.int_volt	= 1000000,
	},
};

static u32 clkdiv_val[5][11] = {
	/*
	 * Clock divider value for following
	 * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
	 *   HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
	 *   ONEDRAM, MFC, G3D }
	 */

	/* L0 : [1000/200/100][166/83][133/66][200/200] */
	{0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},

	/* L1 : [800/200/100][166/83][133/66][200/200] */
	{0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},

	/* L2 : [400/200/100][166/83][133/66][200/200] */
	{1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},

	/* L3 : [200/200/100][166/83][133/66][200/200] */
	{3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},

	/* L4 : [100/100/100][83/83][66/66][100/100] */
	{7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
};

/*
 * This function set DRAM refresh counter
 * accoriding to operating frequency of DRAM
 * ch: DMC port number 0 or 1
 * freq: Operating frequency of DRAM(KHz)
 */
static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
{
	unsigned long tmp, tmp1;
	void __iomem *reg = NULL;

	if (ch == DMC0) {
		reg = (S5P_VA_DMC0 + 0x30);
	} else if (ch == DMC1) {
		reg = (S5P_VA_DMC1 + 0x30);
	} else {
		printk(KERN_ERR "Cannot find DMC port\n");
		return;
	}

	/* Find current DRAM frequency */
	tmp = s5pv210_dram_conf[ch].freq;

	do_div(tmp, freq);

	tmp1 = s5pv210_dram_conf[ch].refresh;

	do_div(tmp1, tmp);

	__raw_writel(tmp1, reg);
}

int s5pv210_verify_speed(struct cpufreq_policy *policy)
{
	if (policy->cpu)
		return -EINVAL;

	return cpufreq_frequency_table_verify(policy, s5pv210_freq_table);
}

unsigned int s5pv210_getspeed(unsigned int cpu)
{
	if (cpu)
		return 0;

	return clk_get_rate(cpu_clk) / 1000;
}

static int s5pv210_target(struct cpufreq_policy *policy,
			  unsigned int target_freq,
			  unsigned int relation)
{
	unsigned long reg;
	unsigned int index, priv_index;
	unsigned int pll_changing = 0;
	unsigned int bus_speed_changing = 0;
	int arm_volt, int_volt;
	int ret = 0;

	mutex_lock(&set_freq_lock);

	if (relation & ENABLE_FURTHER_CPUFREQ)
		no_cpufreq_access = false;

	if (no_cpufreq_access) {
#ifdef CONFIG_PM_VERBOSE
		pr_err("%s:%d denied access to %s as it is disabled"
				"temporarily\n", __FILE__, __LINE__, __func__);
#endif
		ret = -EINVAL;
		goto exit;
	}

	if (relation & DISABLE_FURTHER_CPUFREQ)
		no_cpufreq_access = true;

	relation &= ~(ENABLE_FURTHER_CPUFREQ | DISABLE_FURTHER_CPUFREQ);

	freqs.old = s5pv210_getspeed(0);

	if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
					   target_freq, relation, &index)) {
		ret = -EINVAL;
		goto exit;
	}

	freqs.new = s5pv210_freq_table[index].frequency;
	freqs.cpu = 0;

	if (freqs.new == freqs.old)
		goto exit;

	/* Finding current running level index */
	if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
					   freqs.old, relation, &priv_index)) {
		ret = -EINVAL;
		goto exit;
	}

	arm_volt = dvs_conf[index].arm_volt;
	int_volt = dvs_conf[index].int_volt;

	if (freqs.new > freqs.old) {
		ret = regulator_set_voltage(arm_regulator,
				arm_volt, arm_volt_max);
		if (ret)
			goto exit;

		ret = regulator_set_voltage(int_regulator,
				int_volt, int_volt_max);
		if (ret)
			goto exit;
	}

	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);

	/* Check if there need to change PLL */
	if ((index == L0) || (priv_index == L0))
		pll_changing = 1;

	/* Check if there need to change System bus clock */
	if ((index == L4) || (priv_index == L4))
		bus_speed_changing = 1;

	if (bus_speed_changing) {
		/*
		 * Reconfigure DRAM refresh counter value for minimum
		 * temporary clock while changing divider.
		 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
		 */
		if (pll_changing)
			s5pv210_set_refresh(DMC1, 83000);
		else
			s5pv210_set_refresh(DMC1, 100000);

		s5pv210_set_refresh(DMC0, 83000);
	}

	/*
	 * APLL should be changed in this level
	 * APLL -> MPLL(for stable transition) -> APLL
	 * Some clock source's clock API are not prepared.
	 * Do not use clock API in below code.
	 */
	if (pll_changing) {
		/*
		 * 1. Temporary Change divider for MFC and G3D
		 * SCLKA2M(200/1=200)->(200/4=50)Mhz
		 */
		reg = __raw_readl(S5P_CLK_DIV2);
		reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
		reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
			(3 << S5P_CLKDIV2_MFC_SHIFT);
		__raw_writel(reg, S5P_CLK_DIV2);

		/* For MFC, G3D dividing */
		do {
			reg = __raw_readl(S5P_CLKDIV_STAT0);
		} while (reg & ((1 << 16) | (1 << 17)));

		/*
		 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
		 * (200/4=50)->(667/4=166)Mhz
		 */
		reg = __raw_readl(S5P_CLK_SRC2);
		reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
		reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
			(1 << S5P_CLKSRC2_MFC_SHIFT);
		__raw_writel(reg, S5P_CLK_SRC2);

		do {
			reg = __raw_readl(S5P_CLKMUX_STAT1);
		} while (reg & ((1 << 7) | (1 << 3)));

		/*
		 * 3. DMC1 refresh count for 133Mhz if (index == L4) is
		 * true refresh counter is already programed in upper
		 * code. 0x287@83Mhz
		 */
		if (!bus_speed_changing)
			s5pv210_set_refresh(DMC1, 133000);

		/* 4. SCLKAPLL -> SCLKMPLL */
		reg = __raw_readl(S5P_CLK_SRC0);
		reg &= ~(S5P_CLKSRC0_MUX200_MASK);
		reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
		__raw_writel(reg, S5P_CLK_SRC0);

		do {
			reg = __raw_readl(S5P_CLKMUX_STAT0);
		} while (reg & (0x1 << 18));

	}

	/* Change divider */
	reg = __raw_readl(S5P_CLK_DIV0);

	reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
		S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
		S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK |
		S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK);

	reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
		(clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) |
		(clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) |
		(clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) |
		(clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) |
		(clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) |
		(clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
		(clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));

	__raw_writel(reg, S5P_CLK_DIV0);

	do {
		reg = __raw_readl(S5P_CLKDIV_STAT0);
	} while (reg & 0xff);

	/* ARM MCS value changed */
	reg = __raw_readl(S5P_ARM_MCS_CON);
	reg &= ~0x3;
	if (index >= L3)
		reg |= 0x3;
	else
		reg |= 0x1;

	__raw_writel(reg, S5P_ARM_MCS_CON);

	if (pll_changing) {
		/* 5. Set Lock time = 30us*24Mhz = 0x2cf */
		__raw_writel(0x2cf, S5P_APLL_LOCK);

		/*
		 * 6. Turn on APLL
		 * 6-1. Set PMS values
		 * 6-2. Wait untile the PLL is locked
		 */
		if (index == L0)
			__raw_writel(APLL_VAL_1000, S5P_APLL_CON);
		else
			__raw_writel(APLL_VAL_800, S5P_APLL_CON);

		do {
			reg = __raw_readl(S5P_APLL_CON);
		} while (!(reg & (0x1 << 29)));

		/*
		 * 7. Change souce clock from SCLKMPLL(667Mhz)
		 * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
		 * (667/4=166)->(200/4=50)Mhz
		 */
		reg = __raw_readl(S5P_CLK_SRC2);
		reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
		reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
			(0 << S5P_CLKSRC2_MFC_SHIFT);
		__raw_writel(reg, S5P_CLK_SRC2);

		do {
			reg = __raw_readl(S5P_CLKMUX_STAT1);
		} while (reg & ((1 << 7) | (1 << 3)));

		/*
		 * 8. Change divider for MFC and G3D
		 * (200/4=50)->(200/1=200)Mhz
		 */
		reg = __raw_readl(S5P_CLK_DIV2);
		reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
		reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
			(clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
		__raw_writel(reg, S5P_CLK_DIV2);

		/* For MFC, G3D dividing */
		do {
			reg = __raw_readl(S5P_CLKDIV_STAT0);
		} while (reg & ((1 << 16) | (1 << 17)));

		/* 9. Change MPLL to APLL in MSYS_MUX */
		reg = __raw_readl(S5P_CLK_SRC0);
		reg &= ~(S5P_CLKSRC0_MUX200_MASK);
		reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
		__raw_writel(reg, S5P_CLK_SRC0);

		do {
			reg = __raw_readl(S5P_CLKMUX_STAT0);
		} while (reg & (0x1 << 18));

		/*
		 * 10. DMC1 refresh counter
		 * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
		 * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
		 */
		if (!bus_speed_changing)
			s5pv210_set_refresh(DMC1, 200000);
	}

	/*
	 * L4 level need to change memory bus speed, hence onedram clock divier
	 * and memory refresh parameter should be changed
	 */
	if (bus_speed_changing) {
		reg = __raw_readl(S5P_CLK_DIV6);
		reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
		reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
		__raw_writel(reg, S5P_CLK_DIV6);

		do {
			reg = __raw_readl(S5P_CLKDIV_STAT1);
		} while (reg & (1 << 15));

		/* Reconfigure DRAM refresh counter value */
		if (index != L4) {
			/*
			 * DMC0 : 166Mhz
			 * DMC1 : 200Mhz
			 */
			s5pv210_set_refresh(DMC0, 166000);
			s5pv210_set_refresh(DMC1, 200000);
		} else {
			/*
			 * DMC0 : 83Mhz
			 * DMC1 : 100Mhz
			 */
			s5pv210_set_refresh(DMC0, 83000);
			s5pv210_set_refresh(DMC1, 100000);
		}
	}

	if (freqs.new < freqs.old) {
		regulator_set_voltage(int_regulator,
				int_volt, int_volt_max);

		regulator_set_voltage(arm_regulator,
				arm_volt, arm_volt_max);
	}

	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);

	printk(KERN_DEBUG "Perf changed[L%d]\n", index);

exit:
	mutex_unlock(&set_freq_lock);
	return ret;
}

#ifdef CONFIG_PM
static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy)
{
	return 0;
}

static int s5pv210_cpufreq_resume(struct cpufreq_policy *policy)
{
	return 0;
}
#endif

static int check_mem_type(void __iomem *dmc_reg)
{
	unsigned long val;

	val = __raw_readl(dmc_reg + 0x4);
	val = (val & (0xf << 8));

	return val >> 8;
}

static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
{
	unsigned long mem_type;
	int ret;

	cpu_clk = clk_get(NULL, "armclk");
	if (IS_ERR(cpu_clk))
		return PTR_ERR(cpu_clk);

	dmc0_clk = clk_get(NULL, "sclk_dmc0");
	if (IS_ERR(dmc0_clk)) {
		ret = PTR_ERR(dmc0_clk);
		goto out_dmc0;
	}

	dmc1_clk = clk_get(NULL, "hclk_msys");
	if (IS_ERR(dmc1_clk)) {
		ret = PTR_ERR(dmc1_clk);
		goto out_dmc1;
	}

	if (policy->cpu != 0) {
		ret = -EINVAL;
		goto out_dmc1;
	}

	/*
	 * check_mem_type : This driver only support LPDDR & LPDDR2.
	 * other memory type is not supported.
	 */
	mem_type = check_mem_type(S5P_VA_DMC0);

	if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
		printk(KERN_ERR "CPUFreq doesn't support this memory type\n");
		ret = -EINVAL;
		goto out_dmc1;
	}

	/* Find current refresh counter and frequency each DMC */
	s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000);
	s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);

	s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000);
	s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);

	policy->cur = policy->min = policy->max = s5pv210_getspeed(0);

	cpufreq_frequency_table_get_attr(s5pv210_freq_table, policy->cpu);

	policy->cpuinfo.transition_latency = 40000;

	return cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table);

out_dmc1:
	clk_put(dmc0_clk);
out_dmc0:
	clk_put(cpu_clk);
	return ret;
}

static int s5pv210_cpufreq_notifier_event(struct notifier_block *this,
					  unsigned long event, void *ptr)
{
	int ret;

	switch (event) {
	case PM_SUSPEND_PREPARE:
		ret = cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ,
					    DISABLE_FURTHER_CPUFREQ);
		if (ret < 0)
			return NOTIFY_BAD;

		return NOTIFY_OK;
	case PM_POST_RESTORE:
	case PM_POST_SUSPEND:
		cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ,
				      ENABLE_FURTHER_CPUFREQ);

		return NOTIFY_OK;
	}

	return NOTIFY_DONE;
}

static struct cpufreq_driver s5pv210_driver = {
	.flags		= CPUFREQ_STICKY,
	.verify		= s5pv210_verify_speed,
	.target		= s5pv210_target,
	.get		= s5pv210_getspeed,
	.init		= s5pv210_cpu_init,
	.name		= "s5pv210",
#ifdef CONFIG_PM
	.suspend	= s5pv210_cpufreq_suspend,
	.resume		= s5pv210_cpufreq_resume,
#endif
};

static struct notifier_block s5pv210_cpufreq_notifier = {
	.notifier_call = s5pv210_cpufreq_notifier_event,
};

static int __init s5pv210_cpufreq_init(void)
{
	arm_regulator = regulator_get(NULL, "vddarm");
	if (IS_ERR(arm_regulator)) {
		pr_err("failed to get regulator vddarm");
		return PTR_ERR(arm_regulator);
	}

	int_regulator = regulator_get(NULL, "vddint");
	if (IS_ERR(int_regulator)) {
		pr_err("failed to get regulator vddint");
		regulator_put(arm_regulator);
		return PTR_ERR(int_regulator);
	}

	register_pm_notifier(&s5pv210_cpufreq_notifier);

	return cpufreq_register_driver(&s5pv210_driver);
}

late_initcall(s5pv210_cpufreq_init);
Commit	Line	Data
f7d77079	1	/*
83efc743 JL	2	* Copyright (c) 2010 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com
	4	*
	5	* CPU frequency scaling for S5PC110/S5PV210
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/types.h>
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
	15	#include <linux/err.h>
	16	#include <linux/clk.h>
	17	#include <linux/io.h>
	18	#include <linux/cpufreq.h>
e8b4c198	19	#include <linux/regulator/consumer.h>
405e6d6d	20	#include <linux/suspend.h>
83efc743 JL	21
	22	#include <mach/map.h>
	23	#include <mach/regs-clock.h>
	24
	25	static struct clk *cpu_clk;
	26	static struct clk *dmc0_clk;
	27	static struct clk *dmc1_clk;
	28	static struct cpufreq_freqs freqs;
5b02b779	29	static DEFINE_MUTEX(set_freq_lock);
83efc743 JL	30
	31	/* APLL M,P,S values for 1G/800Mhz */
	32	#define APLL_VAL_1000 ((1 << 31) \| (125 << 16) \| (3 << 8) \| 1)
	33	#define APLL_VAL_800 ((1 << 31) \| (100 << 16) \| (3 << 8) \| 1)
	34
405e6d6d HK	35	/* Use 800MHz when entering sleep mode */
	36	#define SLEEP_FREQ (800 * 1000)
	37
90d5d0a1 HK	38	/*
	39	* relation has an additional symantics other than the standard of cpufreq
	40	* DISALBE_FURTHER_CPUFREQ: disable further access to target
	41	* ENABLE_FURTUER_CPUFREQ: enable access to target
	42	*/
	43	enum cpufreq_access {
	44	DISABLE_FURTHER_CPUFREQ = 0x10,
	45	ENABLE_FURTHER_CPUFREQ = 0x20,
	46	};
	47
	48	static bool no_cpufreq_access;
	49
83efc743 JL	50	/*
	51	* DRAM configurations to calculate refresh counter for changing
	52	* frequency of memory.
	53	*/
	54	struct dram_conf {
	55	unsigned long freq; /* HZ */
	56	unsigned long refresh; /* DRAM refresh counter * 1000 */
	57	};
	58
	59	/* DRAM configuration (DMC0 and DMC1) */
	60	static struct dram_conf s5pv210_dram_conf[2];
	61
	62	enum perf_level {
	63	L0, L1, L2, L3, L4,
	64	};
	65
	66	enum s5pv210_mem_type {
	67	LPDDR = 0x1,
	68	LPDDR2 = 0x2,
	69	DDR2 = 0x4,
	70	};
	71
	72	enum s5pv210_dmc_port {
	73	DMC0 = 0,
	74	DMC1,
	75	};
	76
	77	static struct cpufreq_frequency_table s5pv210_freq_table[] = {
	78	{L0, 1000*1000},
	79	{L1, 800*1000},
	80	{L2, 400*1000},
	81	{L3, 200*1000},
	82	{L4, 100*1000},
	83	{0, CPUFREQ_TABLE_END},
	84	};
	85
e8b4c198 JC	86	static struct regulator *arm_regulator;
	87	static struct regulator *int_regulator;
	88
	89	struct s5pv210_dvs_conf {
	90	int arm_volt; /* uV */
	91	int int_volt; /* uV */
	92	};
	93
	94	static const int arm_volt_max = 1350000;
	95	static const int int_volt_max = 1250000;
	96
	97	static struct s5pv210_dvs_conf dvs_conf[] = {
	98	[L0] = {
	99	.arm_volt = 1250000,
	100	.int_volt = 1100000,
	101	},
	102	[L1] = {
	103	.arm_volt = 1200000,
	104	.int_volt = 1100000,
	105	},
	106	[L2] = {
	107	.arm_volt = 1050000,
	108	.int_volt = 1100000,
	109	},
	110	[L3] = {
	111	.arm_volt = 950000,
	112	.int_volt = 1100000,
	113	},
	114	[L4] = {
	115	.arm_volt = 950000,
	116	.int_volt = 1000000,
	117	},
	118	};
	119
83efc743 JL	120	static u32 clkdiv_val[5][11] = {
	121	/*
	122	* Clock divider value for following
	123	* { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
	124	* HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
	125	* ONEDRAM, MFC, G3D }
	126	*/
	127
	128	/* L0 : [1000/200/100][166/83][133/66][200/200] */
	129	{0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
	130
	131	/* L1 : [800/200/100][166/83][133/66][200/200] */
	132	{0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
	133
	134	/* L2 : [400/200/100][166/83][133/66][200/200] */
	135	{1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
	136
	137	/* L3 : [200/200/100][166/83][133/66][200/200] */
	138	{3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
	139
	140	/* L4 : [100/100/100][83/83][66/66][100/100] */
	141	{7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
	142	};
	143
	144	/*
	145	* This function set DRAM refresh counter
	146	* accoriding to operating frequency of DRAM
	147	* ch: DMC port number 0 or 1
	148	* freq: Operating frequency of DRAM(KHz)
	149	*/
	150	static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
	151	{
	152	unsigned long tmp, tmp1;
	153	void __iomem *reg = NULL;
	154
d62fa311	155	if (ch == DMC0) {
83efc743	156	reg = (S5P_VA_DMC0 + 0x30);
d62fa311	157	} else if (ch == DMC1) {
83efc743	158	reg = (S5P_VA_DMC1 + 0x30);
d62fa311	159	} else {
83efc743	160	printk(KERN_ERR "Cannot find DMC port\n");
d62fa311 JC	161	return;
d62fa311 JC	162	}
83efc743 JL	163
	164	/* Find current DRAM frequency */
	165	tmp = s5pv210_dram_conf[ch].freq;
	166
	167	do_div(tmp, freq);
	168
	169	tmp1 = s5pv210_dram_conf[ch].refresh;
	170
	171	do_div(tmp1, tmp);
	172
	173	__raw_writel(tmp1, reg);
	174	}
	175
	176	int s5pv210_verify_speed(struct cpufreq_policy *policy)
	177	{
	178	if (policy->cpu)
	179	return -EINVAL;
	180
	181	return cpufreq_frequency_table_verify(policy, s5pv210_freq_table);
	182	}
	183
	184	unsigned int s5pv210_getspeed(unsigned int cpu)
	185	{
	186	if (cpu)
	187	return 0;
	188
	189	return clk_get_rate(cpu_clk) / 1000;
	190	}
	191
	192	static int s5pv210_target(struct cpufreq_policy *policy,
	193	unsigned int target_freq,
	194	unsigned int relation)
	195	{
	196	unsigned long reg;
	197	unsigned int index, priv_index;
	198	unsigned int pll_changing = 0;
	199	unsigned int bus_speed_changing = 0;
e8b4c198 JC	200	int arm_volt, int_volt;
e8b4c198 JC	201	int ret = 0;
83efc743	202
5b02b779 AH	203	mutex_lock(&set_freq_lock);
5b02b779 AH	204
90d5d0a1 HK	205	if (relation & ENABLE_FURTHER_CPUFREQ)
	206	no_cpufreq_access = false;
	207
	208	if (no_cpufreq_access) {
	209	#ifdef CONFIG_PM_VERBOSE
	210	pr_err("%s:%d denied access to %s as it is disabled"
	211	"temporarily\n", __FILE__, __LINE__, __func__);
	212	#endif
5b02b779 AH	213	ret = -EINVAL;
5b02b779 AH	214	goto exit;
90d5d0a1 HK	215	}
	216
	217	if (relation & DISABLE_FURTHER_CPUFREQ)
	218	no_cpufreq_access = true;
	219
	220	relation &= ~(ENABLE_FURTHER_CPUFREQ \| DISABLE_FURTHER_CPUFREQ);
	221
83efc743 JL	222	freqs.old = s5pv210_getspeed(0);
	223
	224	if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
5b02b779 AH	225	target_freq, relation, &index)) {
	226	ret = -EINVAL;
	227	goto exit;
	228	}
83efc743 JL	229
	230	freqs.new = s5pv210_freq_table[index].frequency;
	231	freqs.cpu = 0;
	232
	233	if (freqs.new == freqs.old)
5b02b779	234	goto exit;
83efc743 JL	235
	236	/* Finding current running level index */
	237	if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
5b02b779 AH	238	freqs.old, relation, &priv_index)) {
	239	ret = -EINVAL;
	240	goto exit;
	241	}
83efc743	242
e8b4c198 JC	243	arm_volt = dvs_conf[index].arm_volt;
e8b4c198 JC	244	int_volt = dvs_conf[index].int_volt;
83efc743 JL	245
83efc743 JL	246	if (freqs.new > freqs.old) {
e8b4c198 JC	247	ret = regulator_set_voltage(arm_regulator,
	248	arm_volt, arm_volt_max);
	249	if (ret)
5b02b779	250	goto exit;
e8b4c198 JC	251
	252	ret = regulator_set_voltage(int_regulator,
	253	int_volt, int_volt_max);
	254	if (ret)
5b02b779	255	goto exit;
83efc743 JL	256	}
83efc743 JL	257
e8b4c198 JC	258	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
e8b4c198 JC	259
83efc743 JL	260	/* Check if there need to change PLL */
	261	if ((index == L0) \|\| (priv_index == L0))
	262	pll_changing = 1;
	263
	264	/* Check if there need to change System bus clock */
	265	if ((index == L4) \|\| (priv_index == L4))
	266	bus_speed_changing = 1;
	267
	268	if (bus_speed_changing) {
	269	/*
	270	* Reconfigure DRAM refresh counter value for minimum
	271	* temporary clock while changing divider.
	272	* expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
	273	*/
	274	if (pll_changing)
	275	s5pv210_set_refresh(DMC1, 83000);
	276	else
	277	s5pv210_set_refresh(DMC1, 100000);
	278
	279	s5pv210_set_refresh(DMC0, 83000);
	280	}
	281
	282	/*
	283	* APLL should be changed in this level
	284	* APLL -> MPLL(for stable transition) -> APLL
	285	* Some clock source's clock API are not prepared.
	286	* Do not use clock API in below code.
	287	*/
	288	if (pll_changing) {
	289	/*
	290	* 1. Temporary Change divider for MFC and G3D
	291	* SCLKA2M(200/1=200)->(200/4=50)Mhz
	292	*/
	293	reg = __raw_readl(S5P_CLK_DIV2);
	294	reg &= ~(S5P_CLKDIV2_G3D_MASK \| S5P_CLKDIV2_MFC_MASK);
	295	reg \|= (3 << S5P_CLKDIV2_G3D_SHIFT) \|
	296	(3 << S5P_CLKDIV2_MFC_SHIFT);
	297	__raw_writel(reg, S5P_CLK_DIV2);
	298
	299	/* For MFC, G3D dividing */
	300	do {
	301	reg = __raw_readl(S5P_CLKDIV_STAT0);
	302	} while (reg & ((1 << 16) \| (1 << 17)));
	303
	304	/*
	305	* 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
	306	* (200/4=50)->(667/4=166)Mhz
	307	*/
	308	reg = __raw_readl(S5P_CLK_SRC2);
	309	reg &= ~(S5P_CLKSRC2_G3D_MASK \| S5P_CLKSRC2_MFC_MASK);
	310	reg \|= (1 << S5P_CLKSRC2_G3D_SHIFT) \|
	311	(1 << S5P_CLKSRC2_MFC_SHIFT);
	312	__raw_writel(reg, S5P_CLK_SRC2);
	313
	314	do {
	315	reg = __raw_readl(S5P_CLKMUX_STAT1);
	316	} while (reg & ((1 << 7) \| (1 << 3)));
	317
	318	/*
	319	* 3. DMC1 refresh count for 133Mhz if (index == L4) is
	320	* true refresh counter is already programed in upper
	321	* code. 0x287@83Mhz
	322	*/
	323	if (!bus_speed_changing)
324	s5pv210_set_refresh(DMC1, 133000);
325
326	/* 4. SCLKAPLL -> SCLKMPLL */
327	reg = __raw_readl(S5P_CLK_SRC0);
328	reg &= ~(S5P_CLKSRC0_MUX200_MASK);
329	reg \|= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
330	__raw_writel(reg, S5P_CLK_SRC0);
331
332	do {
333	reg = __raw_readl(S5P_CLKMUX_STAT0);
334	} while (reg & (0x1 << 18));
335
336	}
337
338	/* Change divider */
339	reg = __raw_readl(S5P_CLK_DIV0);
340
341	reg &= ~(S5P_CLKDIV0_APLL_MASK \| S5P_CLKDIV0_A2M_MASK \|
342	S5P_CLKDIV0_HCLK200_MASK \| S5P_CLKDIV0_PCLK100_MASK \|
343	S5P_CLKDIV0_HCLK166_MASK \| S5P_CLKDIV0_PCLK83_MASK \|
344	S5P_CLKDIV0_HCLK133_MASK \| S5P_CLKDIV0_PCLK66_MASK);
345
346	reg \|= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) \|
347	(clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) \|
348	(clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) \|
349	(clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) \|
350	(clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) \|
351	(clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) \|
352	(clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) \|
353	(clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
354
355	__raw_writel(reg, S5P_CLK_DIV0);
356
357	do {
358	reg = __raw_readl(S5P_CLKDIV_STAT0);
359	} while (reg & 0xff);
360
361	/* ARM MCS value changed */
362	reg = __raw_readl(S5P_ARM_MCS_CON);
363	reg &= ~0x3;
364	if (index >= L3)
365	reg \|= 0x3;
366	else
367	reg \|= 0x1;
368
369	__raw_writel(reg, S5P_ARM_MCS_CON);
370
371	if (pll_changing) {
372	/* 5. Set Lock time = 30us24Mhz = 0x2cf /
373	__raw_writel(0x2cf, S5P_APLL_LOCK);
374
375	/*
376	* 6. Turn on APLL
377	* 6-1. Set PMS values
378	* 6-2. Wait untile the PLL is locked
379	*/
380	if (index == L0)
381	__raw_writel(APLL_VAL_1000, S5P_APLL_CON);
382	else
383	__raw_writel(APLL_VAL_800, S5P_APLL_CON);
384
385	do {
386	reg = __raw_readl(S5P_APLL_CON);
387	} while (!(reg & (0x1 << 29)));
388
389	/*
390	* 7. Change souce clock from SCLKMPLL(667Mhz)
391	* to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
392	* (667/4=166)->(200/4=50)Mhz
393	*/
394	reg = __raw_readl(S5P_CLK_SRC2);
395	reg &= ~(S5P_CLKSRC2_G3D_MASK \| S5P_CLKSRC2_MFC_MASK);
396	reg \|= (0 << S5P_CLKSRC2_G3D_SHIFT) \|
397	(0 << S5P_CLKSRC2_MFC_SHIFT);
398	__raw_writel(reg, S5P_CLK_SRC2);
399
400	do {
401	reg = __raw_readl(S5P_CLKMUX_STAT1);
402	} while (reg & ((1 << 7) \| (1 << 3)));
403
404	/*
405	* 8. Change divider for MFC and G3D
406	* (200/4=50)->(200/1=200)Mhz
407	*/
408	reg = __raw_readl(S5P_CLK_DIV2);
409	reg &= ~(S5P_CLKDIV2_G3D_MASK \| S5P_CLKDIV2_MFC_MASK);
410	reg \|= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) \|
411	(clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
412	__raw_writel(reg, S5P_CLK_DIV2);
413
414	/* For MFC, G3D dividing */
415	do {
416	reg = __raw_readl(S5P_CLKDIV_STAT0);
417	} while (reg & ((1 << 16) \| (1 << 17)));
418
419	/* 9. Change MPLL to APLL in MSYS_MUX */
420	reg = __raw_readl(S5P_CLK_SRC0);
421	reg &= ~(S5P_CLKSRC0_MUX200_MASK);
422	reg \|= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
423	__raw_writel(reg, S5P_CLK_SRC0);
424
425	do {
426	reg = __raw_readl(S5P_CLKMUX_STAT0);
427	} while (reg & (0x1 << 18));
428
429	/*
430	* 10. DMC1 refresh counter
431	* L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
432	* Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
433	*/
434	if (!bus_speed_changing)
435	s5pv210_set_refresh(DMC1, 200000);
436	}
437
438	/*
439	* L4 level need to change memory bus speed, hence onedram clock divier
440	* and memory refresh parameter should be changed
441	*/
442	if (bus_speed_changing) {
443	reg = __raw_readl(S5P_CLK_DIV6);
444	reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
445	reg \|= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
446	__raw_writel(reg, S5P_CLK_DIV6);
447
448	do {
449	reg = __raw_readl(S5P_CLKDIV_STAT1);
450	} while (reg & (1 << 15));
451
452	/* Reconfigure DRAM refresh counter value */
453	if (index != L4) {
454	/*
455	* DMC0 : 166Mhz
456	* DMC1 : 200Mhz
457	*/
458	s5pv210_set_refresh(DMC0, 166000);
459	s5pv210_set_refresh(DMC1, 200000);
460	} else {
461	/*
462	* DMC0 : 83Mhz
463	* DMC1 : 100Mhz
464	*/
465	s5pv210_set_refresh(DMC0, 83000);
466	s5pv210_set_refresh(DMC1, 100000);
467	}
468	}
469
470	if (freqs.new < freqs.old) {
e8b4c198 JC	471	regulator_set_voltage(int_regulator,
	472	int_volt, int_volt_max);
	473
	474	regulator_set_voltage(arm_regulator,
	475	arm_volt, arm_volt_max);
83efc743 JL	476	}
	477
	478	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
	479
	480	printk(KERN_DEBUG "Perf changed[L%d]\n", index);
	481
5b02b779 AH	482	exit:
	483	mutex_unlock(&set_freq_lock);
	484	return ret;
83efc743 JL	485	}
	486
	487	#ifdef CONFIG_PM
7ca64e2d	488	static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy)
83efc743 JL	489	{
	490	return 0;
	491	}
	492
	493	static int s5pv210_cpufreq_resume(struct cpufreq_policy *policy)
	494	{
	495	return 0;
	496	}
	497	#endif
	498
	499	static int check_mem_type(void __iomem *dmc_reg)
	500	{
	501	unsigned long val;
	502
	503	val = __raw_readl(dmc_reg + 0x4);
	504	val = (val & (0xf << 8));
	505
	506	return val >> 8;
	507	}
	508
	509	static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
	510	{
	511	unsigned long mem_type;
4911ca10	512	int ret;
83efc743 JL	513
	514	cpu_clk = clk_get(NULL, "armclk");
	515	if (IS_ERR(cpu_clk))
	516	return PTR_ERR(cpu_clk);
	517
	518	dmc0_clk = clk_get(NULL, "sclk_dmc0");
	519	if (IS_ERR(dmc0_clk)) {
4911ca10 JL	520	ret = PTR_ERR(dmc0_clk);
4911ca10 JL	521	goto out_dmc0;
83efc743 JL	522	}
	523
	524	dmc1_clk = clk_get(NULL, "hclk_msys");
	525	if (IS_ERR(dmc1_clk)) {
4911ca10 JL	526	ret = PTR_ERR(dmc1_clk);
4911ca10 JL	527	goto out_dmc1;
83efc743 JL	528	}
83efc743 JL	529
4911ca10 JL	530	if (policy->cpu != 0) {
	531	ret = -EINVAL;
	532	goto out_dmc1;
	533	}
83efc743 JL	534
	535	/*
	536	* check_mem_type : This driver only support LPDDR & LPDDR2.
	537	* other memory type is not supported.
	538	*/
	539	mem_type = check_mem_type(S5P_VA_DMC0);
	540
	541	if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
	542	printk(KERN_ERR "CPUFreq doesn't support this memory type\n");
4911ca10 JL	543	ret = -EINVAL;
4911ca10 JL	544	goto out_dmc1;
83efc743 JL	545	}
	546
	547	/* Find current refresh counter and frequency each DMC */
	548	s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000);
	549	s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
	550
	551	s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000);
	552	s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
	553
	554	policy->cur = policy->min = policy->max = s5pv210_getspeed(0);
	555
	556	cpufreq_frequency_table_get_attr(s5pv210_freq_table, policy->cpu);
	557
	558	policy->cpuinfo.transition_latency = 40000;
	559
	560	return cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table);
4911ca10 JL	561
	562	out_dmc1:
	563	clk_put(dmc0_clk);
	564	out_dmc0:
	565	clk_put(cpu_clk);
	566	return ret;
83efc743 JL	567	}
83efc743 JL	568
405e6d6d HK	569	static int s5pv210_cpufreq_notifier_event(struct notifier_block *this,
	570	unsigned long event, void *ptr)
	571	{
	572	int ret;
	573
	574	switch (event) {
	575	case PM_SUSPEND_PREPARE:
	576	ret = cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ,
	577	DISABLE_FURTHER_CPUFREQ);
	578	if (ret < 0)
	579	return NOTIFY_BAD;
	580
	581	return NOTIFY_OK;
	582	case PM_POST_RESTORE:
	583	case PM_POST_SUSPEND:
	584	cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ,
	585	ENABLE_FURTHER_CPUFREQ);
	586
	587	return NOTIFY_OK;
	588	}
	589
	590	return NOTIFY_DONE;
	591	}
	592
83efc743 JL	593	static struct cpufreq_driver s5pv210_driver = {
	594	.flags = CPUFREQ_STICKY,
	595	.verify = s5pv210_verify_speed,
	596	.target = s5pv210_target,
	597	.get = s5pv210_getspeed,
	598	.init = s5pv210_cpu_init,
	599	.name = "s5pv210",
	600	#ifdef CONFIG_PM
	601	.suspend = s5pv210_cpufreq_suspend,
	602	.resume = s5pv210_cpufreq_resume,
	603	#endif
	604	};
	605
405e6d6d HK	606	static struct notifier_block s5pv210_cpufreq_notifier = {
	607	.notifier_call = s5pv210_cpufreq_notifier_event,
	608	};
	609
83efc743 JL	610	static int __init s5pv210_cpufreq_init(void)
83efc743 JL	611	{
e8b4c198 JC	612	arm_regulator = regulator_get(NULL, "vddarm");
	613	if (IS_ERR(arm_regulator)) {
	614	pr_err("failed to get regulator vddarm");
	615	return PTR_ERR(arm_regulator);
	616	}
	617
	618	int_regulator = regulator_get(NULL, "vddint");
	619	if (IS_ERR(int_regulator)) {
	620	pr_err("failed to get regulator vddint");
	621	regulator_put(arm_regulator);
	622	return PTR_ERR(int_regulator);
	623	}
	624
405e6d6d HK	625	register_pm_notifier(&s5pv210_cpufreq_notifier);
405e6d6d HK	626
83efc743 JL	627	return cpufreq_register_driver(&s5pv210_driver);
	628	}
	629
	630	late_initcall(s5pv210_cpufreq_init);