Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de> | |
3 | * | |
4 | * Licensed under the terms of the GNU GPL License version 2. | |
5 | * | |
6 | * Library for common functions for Intel SpeedStep v.1 and v.2 support | |
7 | * | |
8 | * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous* | |
9 | */ | |
10 | ||
11 | #include <linux/kernel.h> | |
32ee8c3e | 12 | #include <linux/module.h> |
1da177e4 LT |
13 | #include <linux/moduleparam.h> |
14 | #include <linux/init.h> | |
15 | #include <linux/cpufreq.h> | |
1da177e4 LT |
16 | |
17 | #include <asm/msr.h> | |
199785ea | 18 | #include <asm/tsc.h> |
1da177e4 LT |
19 | #include "speedstep-lib.h" |
20 | ||
bbfebd66 | 21 | #define PFX "speedstep-lib: " |
1da177e4 LT |
22 | |
23 | #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK | |
bbfebd66 | 24 | static int relaxed_check; |
1da177e4 LT |
25 | #else |
26 | #define relaxed_check 0 | |
27 | #endif | |
28 | ||
29 | /********************************************************************* | |
30 | * GET PROCESSOR CORE SPEED IN KHZ * | |
31 | *********************************************************************/ | |
32 | ||
1cce76c2 | 33 | static unsigned int pentium3_get_frequency(enum speedstep_processor processor) |
1da177e4 | 34 | { |
bbfebd66 | 35 | /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */ |
1da177e4 LT |
36 | struct { |
37 | unsigned int ratio; /* Frequency Multiplier (x10) */ | |
32ee8c3e DJ |
38 | u8 bitmap; /* power on configuration bits |
39 | [27, 25:22] (in MSR 0x2a) */ | |
bbfebd66 | 40 | } msr_decode_mult[] = { |
1da177e4 LT |
41 | { 30, 0x01 }, |
42 | { 35, 0x05 }, | |
43 | { 40, 0x02 }, | |
44 | { 45, 0x06 }, | |
45 | { 50, 0x00 }, | |
46 | { 55, 0x04 }, | |
47 | { 60, 0x0b }, | |
48 | { 65, 0x0f }, | |
49 | { 70, 0x09 }, | |
50 | { 75, 0x0d }, | |
51 | { 80, 0x0a }, | |
52 | { 85, 0x26 }, | |
53 | { 90, 0x20 }, | |
54 | { 100, 0x2b }, | |
bbfebd66 | 55 | { 0, 0xff } /* error or unknown value */ |
1da177e4 LT |
56 | }; |
57 | ||
58 | /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */ | |
59 | struct { | |
32ee8c3e DJ |
60 | unsigned int value; /* Front Side Bus speed in MHz */ |
61 | u8 bitmap; /* power on configuration bits [18: 19] | |
62 | (in MSR 0x2a) */ | |
bbfebd66 | 63 | } msr_decode_fsb[] = { |
1da177e4 LT |
64 | { 66, 0x0 }, |
65 | { 100, 0x2 }, | |
66 | { 133, 0x1 }, | |
67 | { 0, 0xff} | |
68 | }; | |
69 | ||
32ee8c3e DJ |
70 | u32 msr_lo, msr_tmp; |
71 | int i = 0, j = 0; | |
1da177e4 LT |
72 | |
73 | /* read MSR 0x2a - we only need the low 32 bits */ | |
74 | rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp); | |
2d06d8c4 | 75 | pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp); |
1da177e4 LT |
76 | msr_tmp = msr_lo; |
77 | ||
78 | /* decode the FSB */ | |
79 | msr_tmp &= 0x00c0000; | |
80 | msr_tmp >>= 18; | |
81 | while (msr_tmp != msr_decode_fsb[i].bitmap) { | |
82 | if (msr_decode_fsb[i].bitmap == 0xff) | |
83 | return 0; | |
84 | i++; | |
85 | } | |
86 | ||
87 | /* decode the multiplier */ | |
bbfebd66 | 88 | if (processor == SPEEDSTEP_CPU_PIII_C_EARLY) { |
2d06d8c4 | 89 | pr_debug("workaround for early PIIIs\n"); |
1da177e4 LT |
90 | msr_lo &= 0x03c00000; |
91 | } else | |
92 | msr_lo &= 0x0bc00000; | |
93 | msr_lo >>= 22; | |
94 | while (msr_lo != msr_decode_mult[j].bitmap) { | |
95 | if (msr_decode_mult[j].bitmap == 0xff) | |
96 | return 0; | |
97 | j++; | |
98 | } | |
99 | ||
2d06d8c4 | 100 | pr_debug("speed is %u\n", |
bbfebd66 | 101 | (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100)); |
1da177e4 | 102 | |
bbfebd66 | 103 | return msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100; |
1da177e4 LT |
104 | } |
105 | ||
106 | ||
107 | static unsigned int pentiumM_get_frequency(void) | |
108 | { | |
32ee8c3e | 109 | u32 msr_lo, msr_tmp; |
1da177e4 LT |
110 | |
111 | rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp); | |
2d06d8c4 | 112 | pr_debug("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp); |
1da177e4 LT |
113 | |
114 | /* see table B-2 of 24547212.pdf */ | |
115 | if (msr_lo & 0x00040000) { | |
bbfebd66 DJ |
116 | printk(KERN_DEBUG PFX "PM - invalid FSB: 0x%x 0x%x\n", |
117 | msr_lo, msr_tmp); | |
1da177e4 LT |
118 | return 0; |
119 | } | |
120 | ||
121 | msr_tmp = (msr_lo >> 22) & 0x1f; | |
2d06d8c4 | 122 | pr_debug("bits 22-26 are 0x%x, speed is %u\n", |
bbfebd66 | 123 | msr_tmp, (msr_tmp * 100 * 1000)); |
1da177e4 | 124 | |
bbfebd66 | 125 | return msr_tmp * 100 * 1000; |
1da177e4 LT |
126 | } |
127 | ||
4e74663c DB |
128 | static unsigned int pentium_core_get_frequency(void) |
129 | { | |
130 | u32 fsb = 0; | |
131 | u32 msr_lo, msr_tmp; | |
bbfebd66 | 132 | int ret; |
4e74663c DB |
133 | |
134 | rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp); | |
e11952b9 | 135 | /* see table B-2 of 25366920.pdf */ |
4e74663c DB |
136 | switch (msr_lo & 0x07) { |
137 | case 5: | |
e11952b9 | 138 | fsb = 100000; |
4e74663c DB |
139 | break; |
140 | case 1: | |
e11952b9 | 141 | fsb = 133333; |
4e74663c DB |
142 | break; |
143 | case 3: | |
e11952b9 | 144 | fsb = 166667; |
4e74663c | 145 | break; |
c60e19eb HRK |
146 | case 2: |
147 | fsb = 200000; | |
148 | break; | |
149 | case 0: | |
150 | fsb = 266667; | |
151 | break; | |
152 | case 4: | |
153 | fsb = 333333; | |
154 | break; | |
4e74663c DB |
155 | default: |
156 | printk(KERN_ERR "PCORE - MSR_FSB_FREQ undefined value"); | |
157 | } | |
158 | ||
159 | rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp); | |
2d06d8c4 | 160 | pr_debug("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", |
bbfebd66 | 161 | msr_lo, msr_tmp); |
4e74663c DB |
162 | |
163 | msr_tmp = (msr_lo >> 22) & 0x1f; | |
2d06d8c4 | 164 | pr_debug("bits 22-26 are 0x%x, speed is %u\n", |
bbfebd66 | 165 | msr_tmp, (msr_tmp * fsb)); |
4e74663c | 166 | |
bbfebd66 DJ |
167 | ret = (msr_tmp * fsb); |
168 | return ret; | |
4e74663c | 169 | } |
e11952b9 | 170 | |
1da177e4 LT |
171 | |
172 | static unsigned int pentium4_get_frequency(void) | |
173 | { | |
174 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
175 | u32 msr_lo, msr_hi, mult; | |
176 | unsigned int fsb = 0; | |
bbfebd66 | 177 | unsigned int ret; |
199785ea MCO |
178 | u8 fsb_code; |
179 | ||
180 | /* Pentium 4 Model 0 and 1 do not have the Core Clock Frequency | |
181 | * to System Bus Frequency Ratio Field in the Processor Frequency | |
182 | * Configuration Register of the MSR. Therefore the current | |
183 | * frequency cannot be calculated and has to be measured. | |
184 | */ | |
185 | if (c->x86_model < 2) | |
186 | return cpu_khz; | |
1da177e4 LT |
187 | |
188 | rdmsr(0x2c, msr_lo, msr_hi); | |
189 | ||
2d06d8c4 | 190 | pr_debug("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi); |
1da177e4 | 191 | |
32ee8c3e | 192 | /* decode the FSB: see IA-32 Intel (C) Architecture Software |
1da177e4 LT |
193 | * Developer's Manual, Volume 3: System Prgramming Guide, |
194 | * revision #12 in Table B-1: MSRs in the Pentium 4 and | |
195 | * Intel Xeon Processors, on page B-4 and B-5. | |
196 | */ | |
199785ea MCO |
197 | fsb_code = (msr_lo >> 16) & 0x7; |
198 | switch (fsb_code) { | |
199 | case 0: | |
1da177e4 | 200 | fsb = 100 * 1000; |
199785ea MCO |
201 | break; |
202 | case 1: | |
203 | fsb = 13333 * 10; | |
204 | break; | |
205 | case 2: | |
206 | fsb = 200 * 1000; | |
207 | break; | |
1da177e4 LT |
208 | } |
209 | ||
210 | if (!fsb) | |
bbfebd66 DJ |
211 | printk(KERN_DEBUG PFX "couldn't detect FSB speed. " |
212 | "Please send an e-mail to <linux@brodo.de>\n"); | |
1da177e4 LT |
213 | |
214 | /* Multiplier. */ | |
ed9cbcd4 | 215 | mult = msr_lo >> 24; |
1da177e4 | 216 | |
2d06d8c4 | 217 | pr_debug("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n", |
bbfebd66 | 218 | fsb, mult, (fsb * mult)); |
1da177e4 | 219 | |
bbfebd66 DJ |
220 | ret = (fsb * mult); |
221 | return ret; | |
1da177e4 LT |
222 | } |
223 | ||
32ee8c3e | 224 | |
394122ab | 225 | /* Warning: may get called from smp_call_function_single. */ |
1cce76c2 | 226 | unsigned int speedstep_get_frequency(enum speedstep_processor processor) |
1da177e4 LT |
227 | { |
228 | switch (processor) { | |
bbfebd66 | 229 | case SPEEDSTEP_CPU_PCORE: |
4e74663c | 230 | return pentium_core_get_frequency(); |
bbfebd66 | 231 | case SPEEDSTEP_CPU_PM: |
1da177e4 | 232 | return pentiumM_get_frequency(); |
bbfebd66 DJ |
233 | case SPEEDSTEP_CPU_P4D: |
234 | case SPEEDSTEP_CPU_P4M: | |
1da177e4 | 235 | return pentium4_get_frequency(); |
bbfebd66 DJ |
236 | case SPEEDSTEP_CPU_PIII_T: |
237 | case SPEEDSTEP_CPU_PIII_C: | |
238 | case SPEEDSTEP_CPU_PIII_C_EARLY: | |
1da177e4 LT |
239 | return pentium3_get_frequency(processor); |
240 | default: | |
241 | return 0; | |
242 | }; | |
243 | return 0; | |
244 | } | |
bbfebd66 | 245 | EXPORT_SYMBOL_GPL(speedstep_get_frequency); |
1da177e4 LT |
246 | |
247 | ||
248 | /********************************************************************* | |
249 | * DETECT SPEEDSTEP-CAPABLE PROCESSOR * | |
250 | *********************************************************************/ | |
251 | ||
fa8031ae | 252 | /* Keep in sync with the x86_cpu_id tables in the different modules */ |
bbfebd66 | 253 | unsigned int speedstep_detect_processor(void) |
1da177e4 | 254 | { |
92cb7612 | 255 | struct cpuinfo_x86 *c = &cpu_data(0); |
32ee8c3e | 256 | u32 ebx, msr_lo, msr_hi; |
1da177e4 | 257 | |
2d06d8c4 | 258 | pr_debug("x86: %x, model: %x\n", c->x86, c->x86_model); |
1da177e4 | 259 | |
32ee8c3e | 260 | if ((c->x86_vendor != X86_VENDOR_INTEL) || |
1da177e4 LT |
261 | ((c->x86 != 6) && (c->x86 != 0xF))) |
262 | return 0; | |
263 | ||
264 | if (c->x86 == 0xF) { | |
265 | /* Intel Mobile Pentium 4-M | |
266 | * or Intel Mobile Pentium 4 with 533 MHz FSB */ | |
267 | if (c->x86_model != 2) | |
268 | return 0; | |
269 | ||
270 | ebx = cpuid_ebx(0x00000001); | |
271 | ebx &= 0x000000FF; | |
272 | ||
2d06d8c4 | 273 | pr_debug("ebx value is %x, x86_mask is %x\n", ebx, c->x86_mask); |
1da177e4 LT |
274 | |
275 | switch (c->x86_mask) { | |
32ee8c3e | 276 | case 4: |
1da177e4 | 277 | /* |
32ee8c3e | 278 | * B-stepping [M-P4-M] |
1da177e4 LT |
279 | * sample has ebx = 0x0f, production has 0x0e. |
280 | */ | |
281 | if ((ebx == 0x0e) || (ebx == 0x0f)) | |
bbfebd66 | 282 | return SPEEDSTEP_CPU_P4M; |
1da177e4 | 283 | break; |
32ee8c3e | 284 | case 7: |
1da177e4 LT |
285 | /* |
286 | * C-stepping [M-P4-M] | |
287 | * needs to have ebx=0x0e, else it's a celeron: | |
288 | * cf. 25130917.pdf / page 7, footnote 5 even | |
289 | * though 25072120.pdf / page 7 doesn't say | |
290 | * samples are only of B-stepping... | |
291 | */ | |
292 | if (ebx == 0x0e) | |
bbfebd66 | 293 | return SPEEDSTEP_CPU_P4M; |
1da177e4 LT |
294 | break; |
295 | case 9: | |
296 | /* | |
297 | * D-stepping [M-P4-M or M-P4/533] | |
298 | * | |
299 | * this is totally strange: CPUID 0x0F29 is | |
300 | * used by M-P4-M, M-P4/533 and(!) Celeron CPUs. | |
301 | * The latter need to be sorted out as they don't | |
302 | * support speedstep. | |
303 | * Celerons with CPUID 0x0F29 may have either | |
304 | * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything | |
305 | * specific. | |
306 | * M-P4-Ms may have either ebx=0xe or 0xf [see above] | |
307 | * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf] | |
308 | * also, M-P4M HTs have ebx=0x8, too | |
bbfebd66 DJ |
309 | * For now, they are distinguished by the model_id |
310 | * string | |
1da177e4 | 311 | */ |
bbfebd66 DJ |
312 | if ((ebx == 0x0e) || |
313 | (strstr(c->x86_model_id, | |
314 | "Mobile Intel(R) Pentium(R) 4") != NULL)) | |
315 | return SPEEDSTEP_CPU_P4M; | |
1da177e4 LT |
316 | break; |
317 | default: | |
318 | break; | |
319 | } | |
320 | return 0; | |
321 | } | |
322 | ||
323 | switch (c->x86_model) { | |
324 | case 0x0B: /* Intel PIII [Tualatin] */ | |
bbfebd66 DJ |
325 | /* cpuid_ebx(1) is 0x04 for desktop PIII, |
326 | * 0x06 for mobile PIII-M */ | |
1da177e4 | 327 | ebx = cpuid_ebx(0x00000001); |
2d06d8c4 | 328 | pr_debug("ebx is %x\n", ebx); |
1da177e4 LT |
329 | |
330 | ebx &= 0x000000FF; | |
331 | ||
332 | if (ebx != 0x06) | |
333 | return 0; | |
334 | ||
335 | /* So far all PIII-M processors support SpeedStep. See | |
32ee8c3e | 336 | * Intel's 24540640.pdf of June 2003 |
1da177e4 | 337 | */ |
bbfebd66 | 338 | return SPEEDSTEP_CPU_PIII_T; |
1da177e4 LT |
339 | |
340 | case 0x08: /* Intel PIII [Coppermine] */ | |
341 | ||
342 | /* all mobile PIII Coppermines have FSB 100 MHz | |
343 | * ==> sort out a few desktop PIIIs. */ | |
344 | rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi); | |
2d06d8c4 | 345 | pr_debug("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n", |
bbfebd66 | 346 | msr_lo, msr_hi); |
1da177e4 LT |
347 | msr_lo &= 0x00c0000; |
348 | if (msr_lo != 0x0080000) | |
349 | return 0; | |
350 | ||
351 | /* | |
352 | * If the processor is a mobile version, | |
353 | * platform ID has bit 50 set | |
354 | * it has SpeedStep technology if either | |
355 | * bit 56 or 57 is set | |
356 | */ | |
357 | rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi); | |
2d06d8c4 | 358 | pr_debug("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n", |
bbfebd66 DJ |
359 | msr_lo, msr_hi); |
360 | if ((msr_hi & (1<<18)) && | |
361 | (relaxed_check ? 1 : (msr_hi & (3<<24)))) { | |
1da177e4 | 362 | if (c->x86_mask == 0x01) { |
2d06d8c4 | 363 | pr_debug("early PIII version\n"); |
bbfebd66 | 364 | return SPEEDSTEP_CPU_PIII_C_EARLY; |
1da177e4 | 365 | } else |
bbfebd66 | 366 | return SPEEDSTEP_CPU_PIII_C; |
1da177e4 LT |
367 | } |
368 | ||
369 | default: | |
370 | return 0; | |
371 | } | |
372 | } | |
373 | EXPORT_SYMBOL_GPL(speedstep_detect_processor); | |
374 | ||
375 | ||
376 | /********************************************************************* | |
377 | * DETECT SPEEDSTEP SPEEDS * | |
378 | *********************************************************************/ | |
379 | ||
1cce76c2 | 380 | unsigned int speedstep_get_freqs(enum speedstep_processor processor, |
1da177e4 LT |
381 | unsigned int *low_speed, |
382 | unsigned int *high_speed, | |
1a10760c | 383 | unsigned int *transition_latency, |
1da177e4 LT |
384 | void (*set_state) (unsigned int state)) |
385 | { | |
386 | unsigned int prev_speed; | |
387 | unsigned int ret = 0; | |
388 | unsigned long flags; | |
72e624de | 389 | ktime_t tv1, tv2; |
1da177e4 LT |
390 | |
391 | if ((!processor) || (!low_speed) || (!high_speed) || (!set_state)) | |
392 | return -EINVAL; | |
393 | ||
2d06d8c4 | 394 | pr_debug("trying to determine both speeds\n"); |
1da177e4 LT |
395 | |
396 | /* get current speed */ | |
bbfebd66 | 397 | prev_speed = speedstep_get_frequency(processor); |
1da177e4 LT |
398 | if (!prev_speed) |
399 | return -EIO; | |
400 | ||
2d06d8c4 | 401 | pr_debug("previous speed is %u\n", prev_speed); |
1a10760c | 402 | |
d4d4eda2 | 403 | preempt_disable(); |
1da177e4 LT |
404 | local_irq_save(flags); |
405 | ||
406 | /* switch to low state */ | |
407 | set_state(SPEEDSTEP_LOW); | |
bbfebd66 | 408 | *low_speed = speedstep_get_frequency(processor); |
1da177e4 LT |
409 | if (!*low_speed) { |
410 | ret = -EIO; | |
411 | goto out; | |
412 | } | |
413 | ||
2d06d8c4 | 414 | pr_debug("low speed is %u\n", *low_speed); |
1da177e4 | 415 | |
1a10760c MD |
416 | /* start latency measurement */ |
417 | if (transition_latency) | |
72e624de | 418 | tv1 = ktime_get(); |
1a10760c | 419 | |
1da177e4 LT |
420 | /* switch to high state */ |
421 | set_state(SPEEDSTEP_HIGH); | |
1a10760c MD |
422 | |
423 | /* end latency measurement */ | |
424 | if (transition_latency) | |
72e624de | 425 | tv2 = ktime_get(); |
1a10760c | 426 | |
bbfebd66 | 427 | *high_speed = speedstep_get_frequency(processor); |
1da177e4 LT |
428 | if (!*high_speed) { |
429 | ret = -EIO; | |
430 | goto out; | |
431 | } | |
432 | ||
2d06d8c4 | 433 | pr_debug("high speed is %u\n", *high_speed); |
1da177e4 LT |
434 | |
435 | if (*low_speed == *high_speed) { | |
436 | ret = -ENODEV; | |
437 | goto out; | |
438 | } | |
439 | ||
440 | /* switch to previous state, if necessary */ | |
441 | if (*high_speed != prev_speed) | |
442 | set_state(SPEEDSTEP_LOW); | |
443 | ||
1a10760c | 444 | if (transition_latency) { |
72e624de | 445 | *transition_latency = ktime_to_us(ktime_sub(tv2, tv1)); |
2d06d8c4 | 446 | pr_debug("transition latency is %u uSec\n", *transition_latency); |
1a10760c MD |
447 | |
448 | /* convert uSec to nSec and add 20% for safety reasons */ | |
449 | *transition_latency *= 1200; | |
450 | ||
451 | /* check if the latency measurement is too high or too low | |
452 | * and set it to a safe value (500uSec) in that case | |
453 | */ | |
bbfebd66 DJ |
454 | if (*transition_latency > 10000000 || |
455 | *transition_latency < 50000) { | |
456 | printk(KERN_WARNING PFX "frequency transition " | |
457 | "measured seems out of range (%u " | |
458 | "nSec), falling back to a safe one of" | |
459 | "%u nSec.\n", | |
1a10760c MD |
460 | *transition_latency, 500000); |
461 | *transition_latency = 500000; | |
462 | } | |
463 | } | |
464 | ||
32ee8c3e | 465 | out: |
1da177e4 | 466 | local_irq_restore(flags); |
d4d4eda2 MP |
467 | preempt_enable(); |
468 | ||
bbfebd66 | 469 | return ret; |
1da177e4 LT |
470 | } |
471 | EXPORT_SYMBOL_GPL(speedstep_get_freqs); | |
472 | ||
473 | #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK | |
474 | module_param(relaxed_check, int, 0444); | |
bbfebd66 DJ |
475 | MODULE_PARM_DESC(relaxed_check, |
476 | "Don't do all checks for speedstep capability."); | |
1da177e4 LT |
477 | #endif |
478 | ||
bbfebd66 DJ |
479 | MODULE_AUTHOR("Dominik Brodowski <linux@brodo.de>"); |
480 | MODULE_DESCRIPTION("Library for Intel SpeedStep 1 or 2 cpufreq drivers."); | |
481 | MODULE_LICENSE("GPL"); |