[deliverable/linux.git] / drivers / cpufreq / tegra-cpufreq.c

/*
 * Copyright (C) 2010 Google, Inc.
 *
 * Author:
 *	Colin Cross <ccross@google.com>
 *	Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/cpufreq.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/suspend.h>

static struct cpufreq_frequency_table freq_table[] = {
	{ .frequency = 216000 },
	{ .frequency = 312000 },
	{ .frequency = 456000 },
	{ .frequency = 608000 },
	{ .frequency = 760000 },
	{ .frequency = 816000 },
	{ .frequency = 912000 },
	{ .frequency = 1000000 },
	{ .frequency = CPUFREQ_TABLE_END },
};

#define NUM_CPUS	2

static struct clk *cpu_clk;
static struct clk *pll_x_clk;
static struct clk *pll_p_clk;
static struct clk *emc_clk;

static unsigned long target_cpu_speed[NUM_CPUS];
static DEFINE_MUTEX(tegra_cpu_lock);
static bool is_suspended;

static int tegra_verify_speed(struct cpufreq_policy *policy)
{
	return cpufreq_frequency_table_verify(policy, freq_table);
}

static unsigned int tegra_getspeed(unsigned int cpu)
{
	unsigned long rate;

	if (cpu >= NUM_CPUS)
		return 0;

	rate = clk_get_rate(cpu_clk) / 1000;
	return rate;
}

static int tegra_cpu_clk_set_rate(unsigned long rate)
{
	int ret;

	/*
	 * Take an extra reference to the main pll so it doesn't turn
	 * off when we move the cpu off of it
	 */
	clk_prepare_enable(pll_x_clk);

	ret = clk_set_parent(cpu_clk, pll_p_clk);
	if (ret) {
		pr_err("Failed to switch cpu to clock pll_p\n");
		goto out;
	}

	if (rate == clk_get_rate(pll_p_clk))
		goto out;

	ret = clk_set_rate(pll_x_clk, rate);
	if (ret) {
		pr_err("Failed to change pll_x to %lu\n", rate);
		goto out;
	}

	ret = clk_set_parent(cpu_clk, pll_x_clk);
	if (ret) {
		pr_err("Failed to switch cpu to clock pll_x\n");
		goto out;
	}

out:
	clk_disable_unprepare(pll_x_clk);
	return ret;
}

static int tegra_update_cpu_speed(struct cpufreq_policy *policy,
		unsigned long rate)
{
	int ret = 0;
	struct cpufreq_freqs freqs;

	freqs.old = tegra_getspeed(0);
	freqs.new = rate;

	if (freqs.old == freqs.new)
		return ret;

	/*
	 * Vote on memory bus frequency based on cpu frequency
	 * This sets the minimum frequency, display or avp may request higher
	 */
	if (rate >= 816000)
		clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
	else if (rate >= 456000)
		clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
	else
		clk_set_rate(emc_clk, 100000000);  /* emc 50Mhz */

	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);

#ifdef CONFIG_CPU_FREQ_DEBUG
	printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
	       freqs.old, freqs.new);
#endif

	ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
	if (ret) {
		pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
			freqs.new);
		freqs.new = freqs.old;
	}

	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);

	return ret;
}

static unsigned long tegra_cpu_highest_speed(void)
{
	unsigned long rate = 0;
	int i;

	for_each_online_cpu(i)
		rate = max(rate, target_cpu_speed[i]);
	return rate;
}

static int tegra_target(struct cpufreq_policy *policy,
		       unsigned int target_freq,
		       unsigned int relation)
{
	unsigned int idx;
	unsigned int freq;
	int ret = 0;

	mutex_lock(&tegra_cpu_lock);

	if (is_suspended) {
		ret = -EBUSY;
		goto out;
	}

	cpufreq_frequency_table_target(policy, freq_table, target_freq,
		relation, &idx);

	freq = freq_table[idx].frequency;

	target_cpu_speed[policy->cpu] = freq;

	ret = tegra_update_cpu_speed(policy, tegra_cpu_highest_speed());

out:
	mutex_unlock(&tegra_cpu_lock);
	return ret;
}

static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
	void *dummy)
{
	mutex_lock(&tegra_cpu_lock);
	if (event == PM_SUSPEND_PREPARE) {
		struct cpufreq_policy *policy = cpufreq_cpu_get(0);
		is_suspended = true;
		pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
			freq_table[0].frequency);
		tegra_update_cpu_speed(policy, freq_table[0].frequency);
		cpufreq_cpu_put(policy);
	} else if (event == PM_POST_SUSPEND) {
		is_suspended = false;
	}
	mutex_unlock(&tegra_cpu_lock);

	return NOTIFY_OK;
}

static struct notifier_block tegra_cpu_pm_notifier = {
	.notifier_call = tegra_pm_notify,
};

static int tegra_cpu_init(struct cpufreq_policy *policy)
{
	if (policy->cpu >= NUM_CPUS)
		return -EINVAL;

	clk_prepare_enable(emc_clk);
	clk_prepare_enable(cpu_clk);

	cpufreq_frequency_table_cpuinfo(policy, freq_table);
	cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
	policy->cur = tegra_getspeed(policy->cpu);
	target_cpu_speed[policy->cpu] = policy->cur;

	/* FIXME: what's the actual transition time? */
	policy->cpuinfo.transition_latency = 300 * 1000;

	cpumask_copy(policy->cpus, cpu_possible_mask);

	if (policy->cpu == 0)
		register_pm_notifier(&tegra_cpu_pm_notifier);

	return 0;
}

static int tegra_cpu_exit(struct cpufreq_policy *policy)
{
	cpufreq_frequency_table_cpuinfo(policy, freq_table);
	clk_disable_unprepare(emc_clk);
	return 0;
}

static struct freq_attr *tegra_cpufreq_attr[] = {
	&cpufreq_freq_attr_scaling_available_freqs,
	NULL,
};

static struct cpufreq_driver tegra_cpufreq_driver = {
	.verify		= tegra_verify_speed,
	.target		= tegra_target,
	.get		= tegra_getspeed,
	.init		= tegra_cpu_init,
	.exit		= tegra_cpu_exit,
	.name		= "tegra",
	.attr		= tegra_cpufreq_attr,
};

static int __init tegra_cpufreq_init(void)
{
	cpu_clk = clk_get_sys(NULL, "cclk");
	if (IS_ERR(cpu_clk))
		return PTR_ERR(cpu_clk);

	pll_x_clk = clk_get_sys(NULL, "pll_x");
	if (IS_ERR(pll_x_clk))
		return PTR_ERR(pll_x_clk);

	pll_p_clk = clk_get_sys(NULL, "pll_p");
	if (IS_ERR(pll_p_clk))
		return PTR_ERR(pll_p_clk);

	emc_clk = clk_get_sys("cpu", "emc");
	if (IS_ERR(emc_clk)) {
		clk_put(cpu_clk);
		return PTR_ERR(emc_clk);
	}

	return cpufreq_register_driver(&tegra_cpufreq_driver);
}

static void __exit tegra_cpufreq_exit(void)
{
        cpufreq_unregister_driver(&tegra_cpufreq_driver);
	clk_put(emc_clk);
	clk_put(cpu_clk);
}


MODULE_AUTHOR("Colin Cross <ccross@android.com>");
MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
MODULE_LICENSE("GPL");
module_init(tegra_cpufreq_init);
module_exit(tegra_cpufreq_exit);
Commit	Line	Data
7056d423	1	/*
7056d423 CC	2	* Copyright (C) 2010 Google, Inc.
	3	*
	4	* Author:
	5	* Colin Cross <ccross@google.com>
	6	* Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
	7	*
	8	* This software is licensed under the terms of the GNU General Public
	9	* License version 2, as published by the Free Software Foundation, and
	10	* may be copied, distributed, and modified under those terms.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/types.h>
	22	#include <linux/sched.h>
	23	#include <linux/cpufreq.h>
	24	#include <linux/delay.h>
	25	#include <linux/init.h>
	26	#include <linux/err.h>
	27	#include <linux/clk.h>
	28	#include <linux/io.h>
1eb2ecf1	29	#include <linux/suspend.h>
7056d423	30
7056d423	31	static struct cpufreq_frequency_table freq_table[] = {
5d69030d VK	32	{ .frequency = 216000 },
	33	{ .frequency = 312000 },
	34	{ .frequency = 456000 },
	35	{ .frequency = 608000 },
	36	{ .frequency = 760000 },
	37	{ .frequency = 816000 },
	38	{ .frequency = 912000 },
	39	{ .frequency = 1000000 },
	40	{ .frequency = CPUFREQ_TABLE_END },
7056d423 CC	41	};
	42
	43	#define NUM_CPUS 2
	44
	45	static struct clk *cpu_clk;
ce32ddaa SW	46	static struct clk *pll_x_clk;
ce32ddaa SW	47	static struct clk *pll_p_clk;
7a281284	48	static struct clk *emc_clk;
7056d423 CC	49
7056d423 CC	50	static unsigned long target_cpu_speed[NUM_CPUS];
1eb2ecf1 CC	51	static DEFINE_MUTEX(tegra_cpu_lock);
1eb2ecf1 CC	52	static bool is_suspended;
7056d423	53
6686c733	54	static int tegra_verify_speed(struct cpufreq_policy *policy)
7056d423 CC	55	{
	56	return cpufreq_frequency_table_verify(policy, freq_table);
	57	}
	58
6686c733	59	static unsigned int tegra_getspeed(unsigned int cpu)
7056d423 CC	60	{
	61	unsigned long rate;
	62
	63	if (cpu >= NUM_CPUS)
	64	return 0;
	65
	66	rate = clk_get_rate(cpu_clk) / 1000;
	67	return rate;
	68	}
	69
ce32ddaa SW	70	static int tegra_cpu_clk_set_rate(unsigned long rate)
	71	{
	72	int ret;
	73
	74	/*
	75	* Take an extra reference to the main pll so it doesn't turn
	76	* off when we move the cpu off of it
	77	*/
	78	clk_prepare_enable(pll_x_clk);
	79
	80	ret = clk_set_parent(cpu_clk, pll_p_clk);
	81	if (ret) {
	82	pr_err("Failed to switch cpu to clock pll_p\n");
	83	goto out;
	84	}
	85
	86	if (rate == clk_get_rate(pll_p_clk))
	87	goto out;
	88
	89	ret = clk_set_rate(pll_x_clk, rate);
	90	if (ret) {
	91	pr_err("Failed to change pll_x to %lu\n", rate);
	92	goto out;
	93	}
	94
	95	ret = clk_set_parent(cpu_clk, pll_x_clk);
	96	if (ret) {
	97	pr_err("Failed to switch cpu to clock pll_x\n");
	98	goto out;
	99	}
	100
	101	out:
	102	clk_disable_unprepare(pll_x_clk);
	103	return ret;
	104	}
	105
b43a7ffb VK	106	static int tegra_update_cpu_speed(struct cpufreq_policy *policy,
b43a7ffb VK	107	unsigned long rate)
7056d423	108	{
7056d423 CC	109	int ret = 0;
	110	struct cpufreq_freqs freqs;
	111
7056d423 CC	112	freqs.old = tegra_getspeed(0);
	113	freqs.new = rate;
	114
	115	if (freqs.old == freqs.new)
	116	return ret;
	117
7a281284 CC	118	/*
	119	* Vote on memory bus frequency based on cpu frequency
	120	* This sets the minimum frequency, display or avp may request higher
	121	*/
	122	if (rate >= 816000)
	123	clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
	124	else if (rate >= 456000)
	125	clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
	126	else
	127	clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
	128
b43a7ffb	129	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
7056d423 CC	130
	131	#ifdef CONFIG_CPU_FREQ_DEBUG
	132	printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
	133	freqs.old, freqs.new);
	134	#endif
	135
ce32ddaa	136	ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
7056d423 CC	137	if (ret) {
	138	pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
	139	freqs.new);
f56cc99e	140	freqs.new = freqs.old;
7056d423 CC	141	}
7056d423 CC	142
b43a7ffb	143	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
7056d423	144
f56cc99e	145	return ret;
7056d423 CC	146	}
7056d423 CC	147
1eb2ecf1 CC	148	static unsigned long tegra_cpu_highest_speed(void)
	149	{
	150	unsigned long rate = 0;
	151	int i;
	152
	153	for_each_online_cpu(i)
	154	rate = max(rate, target_cpu_speed[i]);
	155	return rate;
	156	}
	157
7056d423 CC	158	static int tegra_target(struct cpufreq_policy *policy,
	159	unsigned int target_freq,
	160	unsigned int relation)
	161	{
fdb684ac	162	unsigned int idx;
7056d423	163	unsigned int freq;
1eb2ecf1 CC	164	int ret = 0;
	165
	166	mutex_lock(&tegra_cpu_lock);
	167
	168	if (is_suspended) {
	169	ret = -EBUSY;
	170	goto out;
	171	}
7056d423 CC	172
	173	cpufreq_frequency_table_target(policy, freq_table, target_freq,
	174	relation, &idx);
	175
	176	freq = freq_table[idx].frequency;
	177
	178	target_cpu_speed[policy->cpu] = freq;
	179
b43a7ffb	180	ret = tegra_update_cpu_speed(policy, tegra_cpu_highest_speed());
1eb2ecf1 CC	181
	182	out:
	183	mutex_unlock(&tegra_cpu_lock);
	184	return ret;
7056d423 CC	185	}
7056d423 CC	186
1eb2ecf1 CC	187	static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
	188	void *dummy)
	189	{
	190	mutex_lock(&tegra_cpu_lock);
	191	if (event == PM_SUSPEND_PREPARE) {
b43a7ffb	192	struct cpufreq_policy *policy = cpufreq_cpu_get(0);
1eb2ecf1 CC	193	is_suspended = true;
	194	pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
	195	freq_table[0].frequency);
b43a7ffb VK	196	tegra_update_cpu_speed(policy, freq_table[0].frequency);
b43a7ffb VK	197	cpufreq_cpu_put(policy);
1eb2ecf1 CC	198	} else if (event == PM_POST_SUSPEND) {
	199	is_suspended = false;
	200	}
	201	mutex_unlock(&tegra_cpu_lock);
	202
	203	return NOTIFY_OK;
	204	}
	205
	206	static struct notifier_block tegra_cpu_pm_notifier = {
	207	.notifier_call = tegra_pm_notify,
	208	};
	209
7056d423 CC	210	static int tegra_cpu_init(struct cpufreq_policy *policy)
	211	{
	212	if (policy->cpu >= NUM_CPUS)
	213	return -EINVAL;
	214
6a5278d0 PG	215	clk_prepare_enable(emc_clk);
6a5278d0 PG	216	clk_prepare_enable(cpu_clk);
89a5fb84	217
7056d423 CC	218	cpufreq_frequency_table_cpuinfo(policy, freq_table);
	219	cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
	220	policy->cur = tegra_getspeed(policy->cpu);
	221	target_cpu_speed[policy->cpu] = policy->cur;
	222
	223	/* FIXME: what's the actual transition time? */
	224	policy->cpuinfo.transition_latency = 300 * 1000;
	225
16a44f82	226	cpumask_copy(policy->cpus, cpu_possible_mask);
7056d423	227
1eb2ecf1 CC	228	if (policy->cpu == 0)
	229	register_pm_notifier(&tegra_cpu_pm_notifier);
	230
7056d423 CC	231	return 0;
	232	}
	233
	234	static int tegra_cpu_exit(struct cpufreq_policy *policy)
	235	{
	236	cpufreq_frequency_table_cpuinfo(policy, freq_table);
6a5278d0	237	clk_disable_unprepare(emc_clk);
7056d423 CC	238	return 0;
	239	}
	240
	241	static struct freq_attr *tegra_cpufreq_attr[] = {
	242	&cpufreq_freq_attr_scaling_available_freqs,
	243	NULL,
	244	};
	245
	246	static struct cpufreq_driver tegra_cpufreq_driver = {
	247	.verify = tegra_verify_speed,
	248	.target = tegra_target,
	249	.get = tegra_getspeed,
	250	.init = tegra_cpu_init,
	251	.exit = tegra_cpu_exit,
	252	.name = "tegra",
	253	.attr = tegra_cpufreq_attr,
	254	};
	255
	256	static int __init tegra_cpufreq_init(void)
	257	{
b192b910	258	cpu_clk = clk_get_sys(NULL, "cclk");
c26cefd0 RZ	259	if (IS_ERR(cpu_clk))
	260	return PTR_ERR(cpu_clk);
	261
	262	pll_x_clk = clk_get_sys(NULL, "pll_x");
	263	if (IS_ERR(pll_x_clk))
	264	return PTR_ERR(pll_x_clk);
	265
b192b910	266	pll_p_clk = clk_get_sys(NULL, "pll_p");
c26cefd0 RZ	267	if (IS_ERR(pll_p_clk))
	268	return PTR_ERR(pll_p_clk);
	269
	270	emc_clk = clk_get_sys("cpu", "emc");
	271	if (IS_ERR(emc_clk)) {
	272	clk_put(cpu_clk);
	273	return PTR_ERR(emc_clk);
	274	}
	275
7056d423 CC	276	return cpufreq_register_driver(&tegra_cpufreq_driver);
	277	}
	278
	279	static void __exit tegra_cpufreq_exit(void)
	280	{
	281	cpufreq_unregister_driver(&tegra_cpufreq_driver);
c26cefd0 RZ	282	clk_put(emc_clk);
c26cefd0 RZ	283	clk_put(cpu_clk);
7056d423 CC	284	}
	285
	286
	287	MODULE_AUTHOR("Colin Cross <ccross@android.com>");
	288	MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
	289	MODULE_LICENSE("GPL");
	290	module_init(tegra_cpufreq_init);
	291	module_exit(tegra_cpufreq_exit);