[deliverable/linux.git] / drivers / cpufreq / tegra-cpufreq.c

/*
 * Copyright (C) 2010 Google, Inc.
 *
 * Author:
 *	Colin Cross <ccross@google.com>
 *	Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/cpufreq.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/suspend.h>

static struct cpufreq_frequency_table freq_table[] = {
	{ .frequency = 216000 },
	{ .frequency = 312000 },
	{ .frequency = 456000 },
	{ .frequency = 608000 },
	{ .frequency = 760000 },
	{ .frequency = 816000 },
	{ .frequency = 912000 },
	{ .frequency = 1000000 },
	{ .frequency = CPUFREQ_TABLE_END },
};

#define NUM_CPUS	2

static struct clk *cpu_clk;
static struct clk *pll_x_clk;
static struct clk *pll_p_clk;
static struct clk *emc_clk;

static unsigned long target_cpu_speed[NUM_CPUS];
static DEFINE_MUTEX(tegra_cpu_lock);
static bool is_suspended;

static unsigned int tegra_getspeed(unsigned int cpu)
{
	unsigned long rate;

	if (cpu >= NUM_CPUS)
		return 0;

	rate = clk_get_rate(cpu_clk) / 1000;
	return rate;
}

static int tegra_cpu_clk_set_rate(unsigned long rate)
{
	int ret;

	/*
	 * Take an extra reference to the main pll so it doesn't turn
	 * off when we move the cpu off of it
	 */
	clk_prepare_enable(pll_x_clk);

	ret = clk_set_parent(cpu_clk, pll_p_clk);
	if (ret) {
		pr_err("Failed to switch cpu to clock pll_p\n");
		goto out;
	}

	if (rate == clk_get_rate(pll_p_clk))
		goto out;

	ret = clk_set_rate(pll_x_clk, rate);
	if (ret) {
		pr_err("Failed to change pll_x to %lu\n", rate);
		goto out;
	}

	ret = clk_set_parent(cpu_clk, pll_x_clk);
	if (ret) {
		pr_err("Failed to switch cpu to clock pll_x\n");
		goto out;
	}

out:
	clk_disable_unprepare(pll_x_clk);
	return ret;
}

static int tegra_update_cpu_speed(struct cpufreq_policy *policy,
		unsigned long rate)
{
	int ret = 0;

	if (tegra_getspeed(0) == rate)
		return ret;

	/*
	 * Vote on memory bus frequency based on cpu frequency
	 * This sets the minimum frequency, display or avp may request higher
	 */
	if (rate >= 816000)
		clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
	else if (rate >= 456000)
		clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
	else
		clk_set_rate(emc_clk, 100000000);  /* emc 50Mhz */

	ret = tegra_cpu_clk_set_rate(rate * 1000);
	if (ret)
		pr_err("cpu-tegra: Failed to set cpu frequency to %lu kHz\n",
			rate);

	return ret;
}

static unsigned long tegra_cpu_highest_speed(void)
{
	unsigned long rate = 0;
	int i;

	for_each_online_cpu(i)
		rate = max(rate, target_cpu_speed[i]);
	return rate;
}

static int tegra_target(struct cpufreq_policy *policy, unsigned int index)
{
	unsigned int freq;
	int ret = 0;

	mutex_lock(&tegra_cpu_lock);

	if (is_suspended) {
		ret = -EBUSY;
		goto out;
	}

	freq = freq_table[index].frequency;

	target_cpu_speed[policy->cpu] = freq;

	ret = tegra_update_cpu_speed(policy, tegra_cpu_highest_speed());

out:
	mutex_unlock(&tegra_cpu_lock);
	return ret;
}

static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
	void *dummy)
{
	mutex_lock(&tegra_cpu_lock);
	if (event == PM_SUSPEND_PREPARE) {
		struct cpufreq_policy *policy = cpufreq_cpu_get(0);
		is_suspended = true;
		pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
			freq_table[0].frequency);
		tegra_update_cpu_speed(policy, freq_table[0].frequency);
		cpufreq_cpu_put(policy);
	} else if (event == PM_POST_SUSPEND) {
		is_suspended = false;
	}
	mutex_unlock(&tegra_cpu_lock);

	return NOTIFY_OK;
}

static struct notifier_block tegra_cpu_pm_notifier = {
	.notifier_call = tegra_pm_notify,
};

static int tegra_cpu_init(struct cpufreq_policy *policy)
{
	int ret;

	if (policy->cpu >= NUM_CPUS)
		return -EINVAL;

	clk_prepare_enable(emc_clk);
	clk_prepare_enable(cpu_clk);

	target_cpu_speed[policy->cpu] = tegra_getspeed(policy->cpu);

	/* FIXME: what's the actual transition time? */
	ret = cpufreq_generic_init(policy, freq_table, 300 * 1000);
	if (ret) {
		clk_disable_unprepare(cpu_clk);
		clk_disable_unprepare(emc_clk);
		return ret;
	}

	if (policy->cpu == 0)
		register_pm_notifier(&tegra_cpu_pm_notifier);

	return 0;
}

static int tegra_cpu_exit(struct cpufreq_policy *policy)
{
	cpufreq_frequency_table_put_attr(policy->cpu);
	clk_disable_unprepare(cpu_clk);
	clk_disable_unprepare(emc_clk);
	return 0;
}

static struct cpufreq_driver tegra_cpufreq_driver = {
	.verify		= cpufreq_generic_frequency_table_verify,
	.target_index	= tegra_target,
	.get		= tegra_getspeed,
	.init		= tegra_cpu_init,
	.exit		= tegra_cpu_exit,
	.name		= "tegra",
	.attr		= cpufreq_generic_attr,
};

static int __init tegra_cpufreq_init(void)
{
	cpu_clk = clk_get_sys(NULL, "cclk");
	if (IS_ERR(cpu_clk))
		return PTR_ERR(cpu_clk);

	pll_x_clk = clk_get_sys(NULL, "pll_x");
	if (IS_ERR(pll_x_clk))
		return PTR_ERR(pll_x_clk);

	pll_p_clk = clk_get_sys(NULL, "pll_p");
	if (IS_ERR(pll_p_clk))
		return PTR_ERR(pll_p_clk);

	emc_clk = clk_get_sys("cpu", "emc");
	if (IS_ERR(emc_clk)) {
		clk_put(cpu_clk);
		return PTR_ERR(emc_clk);
	}

	return cpufreq_register_driver(&tegra_cpufreq_driver);
}

static void __exit tegra_cpufreq_exit(void)
{
        cpufreq_unregister_driver(&tegra_cpufreq_driver);
	clk_put(emc_clk);
	clk_put(cpu_clk);
}


MODULE_AUTHOR("Colin Cross <ccross@android.com>");
MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
MODULE_LICENSE("GPL");
module_init(tegra_cpufreq_init);
module_exit(tegra_cpufreq_exit);
Commit	Line	Data
7056d423	1	/*
7056d423 CC	2	* Copyright (C) 2010 Google, Inc.
	3	*
	4	* Author:
	5	* Colin Cross <ccross@google.com>
	6	* Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
	7	*
	8	* This software is licensed under the terms of the GNU General Public
	9	* License version 2, as published by the Free Software Foundation, and
	10	* may be copied, distributed, and modified under those terms.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/types.h>
	22	#include <linux/sched.h>
	23	#include <linux/cpufreq.h>
	24	#include <linux/delay.h>
	25	#include <linux/init.h>
	26	#include <linux/err.h>
	27	#include <linux/clk.h>
	28	#include <linux/io.h>
1eb2ecf1	29	#include <linux/suspend.h>
7056d423	30
7056d423	31	static struct cpufreq_frequency_table freq_table[] = {
5d69030d VK	32	{ .frequency = 216000 },
	33	{ .frequency = 312000 },
	34	{ .frequency = 456000 },
	35	{ .frequency = 608000 },
	36	{ .frequency = 760000 },
	37	{ .frequency = 816000 },
	38	{ .frequency = 912000 },
	39	{ .frequency = 1000000 },
	40	{ .frequency = CPUFREQ_TABLE_END },
7056d423 CC	41	};
	42
	43	#define NUM_CPUS 2
	44
	45	static struct clk *cpu_clk;
ce32ddaa SW	46	static struct clk *pll_x_clk;
ce32ddaa SW	47	static struct clk *pll_p_clk;
7a281284	48	static struct clk *emc_clk;
7056d423 CC	49
7056d423 CC	50	static unsigned long target_cpu_speed[NUM_CPUS];
1eb2ecf1 CC	51	static DEFINE_MUTEX(tegra_cpu_lock);
1eb2ecf1 CC	52	static bool is_suspended;
7056d423	53
6686c733	54	static unsigned int tegra_getspeed(unsigned int cpu)
7056d423 CC	55	{
	56	unsigned long rate;
	57
	58	if (cpu >= NUM_CPUS)
	59	return 0;
	60
	61	rate = clk_get_rate(cpu_clk) / 1000;
	62	return rate;
	63	}
	64
ce32ddaa SW	65	static int tegra_cpu_clk_set_rate(unsigned long rate)
	66	{
	67	int ret;
	68
	69	/*
	70	* Take an extra reference to the main pll so it doesn't turn
	71	* off when we move the cpu off of it
	72	*/
	73	clk_prepare_enable(pll_x_clk);
	74
	75	ret = clk_set_parent(cpu_clk, pll_p_clk);
	76	if (ret) {
	77	pr_err("Failed to switch cpu to clock pll_p\n");
	78	goto out;
	79	}
	80
	81	if (rate == clk_get_rate(pll_p_clk))
	82	goto out;
	83
	84	ret = clk_set_rate(pll_x_clk, rate);
	85	if (ret) {
	86	pr_err("Failed to change pll_x to %lu\n", rate);
	87	goto out;
	88	}
	89
	90	ret = clk_set_parent(cpu_clk, pll_x_clk);
	91	if (ret) {
	92	pr_err("Failed to switch cpu to clock pll_x\n");
	93	goto out;
	94	}
	95
	96	out:
	97	clk_disable_unprepare(pll_x_clk);
	98	return ret;
	99	}
	100
b43a7ffb VK	101	static int tegra_update_cpu_speed(struct cpufreq_policy *policy,
b43a7ffb VK	102	unsigned long rate)
7056d423	103	{
7056d423	104	int ret = 0;
7056d423	105
d4019f0a	106	if (tegra_getspeed(0) == rate)
7056d423 CC	107	return ret;
7056d423 CC	108
7a281284 CC	109	/*
	110	* Vote on memory bus frequency based on cpu frequency
	111	* This sets the minimum frequency, display or avp may request higher
	112	*/
	113	if (rate >= 816000)
	114	clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
	115	else if (rate >= 456000)
	116	clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
	117	else
	118	clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
	119
d4019f0a VK	120	ret = tegra_cpu_clk_set_rate(rate * 1000);
	121	if (ret)
	122	pr_err("cpu-tegra: Failed to set cpu frequency to %lu kHz\n",
	123	rate);
7056d423	124
f56cc99e	125	return ret;
7056d423 CC	126	}
7056d423 CC	127
1eb2ecf1 CC	128	static unsigned long tegra_cpu_highest_speed(void)
	129	{
	130	unsigned long rate = 0;
	131	int i;
	132
	133	for_each_online_cpu(i)
	134	rate = max(rate, target_cpu_speed[i]);
	135	return rate;
	136	}
	137
9c0ebcf7	138	static int tegra_target(struct cpufreq_policy *policy, unsigned int index)
7056d423	139	{
7056d423	140	unsigned int freq;
1eb2ecf1 CC	141	int ret = 0;
	142
	143	mutex_lock(&tegra_cpu_lock);
	144
	145	if (is_suspended) {
	146	ret = -EBUSY;
	147	goto out;
	148	}
7056d423	149
9c0ebcf7	150	freq = freq_table[index].frequency;
7056d423 CC	151
	152	target_cpu_speed[policy->cpu] = freq;
	153
b43a7ffb	154	ret = tegra_update_cpu_speed(policy, tegra_cpu_highest_speed());
1eb2ecf1 CC	155
	156	out:
	157	mutex_unlock(&tegra_cpu_lock);
	158	return ret;
7056d423 CC	159	}
7056d423 CC	160
1eb2ecf1 CC	161	static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
	162	void *dummy)
	163	{
	164	mutex_lock(&tegra_cpu_lock);
	165	if (event == PM_SUSPEND_PREPARE) {
b43a7ffb	166	struct cpufreq_policy *policy = cpufreq_cpu_get(0);
1eb2ecf1 CC	167	is_suspended = true;
	168	pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
	169	freq_table[0].frequency);
b43a7ffb VK	170	tegra_update_cpu_speed(policy, freq_table[0].frequency);
b43a7ffb VK	171	cpufreq_cpu_put(policy);
1eb2ecf1 CC	172	} else if (event == PM_POST_SUSPEND) {
	173	is_suspended = false;
	174	}
	175	mutex_unlock(&tegra_cpu_lock);
	176
	177	return NOTIFY_OK;
	178	}
	179
	180	static struct notifier_block tegra_cpu_pm_notifier = {
	181	.notifier_call = tegra_pm_notify,
	182	};
	183
7056d423 CC	184	static int tegra_cpu_init(struct cpufreq_policy *policy)
7056d423 CC	185	{
99d428cf VK	186	int ret;
99d428cf VK	187
7056d423 CC	188	if (policy->cpu >= NUM_CPUS)
	189	return -EINVAL;
	190
6a5278d0 PG	191	clk_prepare_enable(emc_clk);
6a5278d0 PG	192	clk_prepare_enable(cpu_clk);
89a5fb84	193
21c895ce	194	target_cpu_speed[policy->cpu] = tegra_getspeed(policy->cpu);
7056d423 CC	195
7056d423 CC	196	/* FIXME: what's the actual transition time? */
99d428cf VK	197	ret = cpufreq_generic_init(policy, freq_table, 300 * 1000);
	198	if (ret) {
	199	clk_disable_unprepare(cpu_clk);
	200	clk_disable_unprepare(emc_clk);
	201	return ret;
	202	}
7056d423	203
1eb2ecf1 CC	204	if (policy->cpu == 0)
	205	register_pm_notifier(&tegra_cpu_pm_notifier);
	206
7056d423 CC	207	return 0;
	208	}
	209
	210	static int tegra_cpu_exit(struct cpufreq_policy *policy)
	211	{
2e6a5c80	212	cpufreq_frequency_table_put_attr(policy->cpu);
99d428cf	213	clk_disable_unprepare(cpu_clk);
6a5278d0	214	clk_disable_unprepare(emc_clk);
7056d423 CC	215	return 0;
	216	}
	217
7056d423	218	static struct cpufreq_driver tegra_cpufreq_driver = {
8e08cf03	219	.verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7	220	.target_index = tegra_target,
7056d423 CC	221	.get = tegra_getspeed,
	222	.init = tegra_cpu_init,
	223	.exit = tegra_cpu_exit,
	224	.name = "tegra",
8e08cf03	225	.attr = cpufreq_generic_attr,
7056d423 CC	226	};
	227
	228	static int __init tegra_cpufreq_init(void)
	229	{
b192b910	230	cpu_clk = clk_get_sys(NULL, "cclk");
c26cefd0 RZ	231	if (IS_ERR(cpu_clk))
	232	return PTR_ERR(cpu_clk);
	233
	234	pll_x_clk = clk_get_sys(NULL, "pll_x");
	235	if (IS_ERR(pll_x_clk))
	236	return PTR_ERR(pll_x_clk);
	237
b192b910	238	pll_p_clk = clk_get_sys(NULL, "pll_p");
c26cefd0 RZ	239	if (IS_ERR(pll_p_clk))
	240	return PTR_ERR(pll_p_clk);
	241
	242	emc_clk = clk_get_sys("cpu", "emc");
	243	if (IS_ERR(emc_clk)) {
	244	clk_put(cpu_clk);
	245	return PTR_ERR(emc_clk);
	246	}
	247
7056d423 CC	248	return cpufreq_register_driver(&tegra_cpufreq_driver);
	249	}
	250
	251	static void __exit tegra_cpufreq_exit(void)
	252	{
	253	cpufreq_unregister_driver(&tegra_cpufreq_driver);
c26cefd0 RZ	254	clk_put(emc_clk);
c26cefd0 RZ	255	clk_put(cpu_clk);
7056d423 CC	256	}
	257
	258
	259	MODULE_AUTHOR("Colin Cross <ccross@android.com>");
	260	MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
	261	MODULE_LICENSE("GPL");
	262	module_init(tegra_cpufreq_init);
	263	module_exit(tegra_cpufreq_exit);