[deliverable/linux.git] / drivers / cpufreq / tegra-cpufreq.c

/*
 * Copyright (C) 2010 Google, Inc.
 *
 * Author:
 *	Colin Cross <ccross@google.com>
 *	Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/cpufreq.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/suspend.h>

/* Frequency table index must be sequential starting at 0 */
static struct cpufreq_frequency_table freq_table[] = {
	{ 0, 216000 },
	{ 1, 312000 },
	{ 2, 456000 },
	{ 3, 608000 },
	{ 4, 760000 },
	{ 5, 816000 },
	{ 6, 912000 },
	{ 7, 1000000 },
	{ 8, CPUFREQ_TABLE_END },
};

#define NUM_CPUS	2

static struct clk *cpu_clk;
static struct clk *pll_x_clk;
static struct clk *pll_p_clk;
static struct clk *emc_clk;

static unsigned long target_cpu_speed[NUM_CPUS];
static DEFINE_MUTEX(tegra_cpu_lock);
static bool is_suspended;

static int tegra_verify_speed(struct cpufreq_policy *policy)
{
	return cpufreq_frequency_table_verify(policy, freq_table);
}

static unsigned int tegra_getspeed(unsigned int cpu)
{
	unsigned long rate;

	if (cpu >= NUM_CPUS)
		return 0;

	rate = clk_get_rate(cpu_clk) / 1000;
	return rate;
}

static int tegra_cpu_clk_set_rate(unsigned long rate)
{
	int ret;

	/*
	 * Take an extra reference to the main pll so it doesn't turn
	 * off when we move the cpu off of it
	 */
	clk_prepare_enable(pll_x_clk);

	ret = clk_set_parent(cpu_clk, pll_p_clk);
	if (ret) {
		pr_err("Failed to switch cpu to clock pll_p\n");
		goto out;
	}

	if (rate == clk_get_rate(pll_p_clk))
		goto out;

	ret = clk_set_rate(pll_x_clk, rate);
	if (ret) {
		pr_err("Failed to change pll_x to %lu\n", rate);
		goto out;
	}

	ret = clk_set_parent(cpu_clk, pll_x_clk);
	if (ret) {
		pr_err("Failed to switch cpu to clock pll_x\n");
		goto out;
	}

out:
	clk_disable_unprepare(pll_x_clk);
	return ret;
}

static int tegra_update_cpu_speed(struct cpufreq_policy *policy,
		unsigned long rate)
{
	int ret = 0;
	struct cpufreq_freqs freqs;

	freqs.old = tegra_getspeed(0);
	freqs.new = rate;

	if (freqs.old == freqs.new)
		return ret;

	/*
	 * Vote on memory bus frequency based on cpu frequency
	 * This sets the minimum frequency, display or avp may request higher
	 */
	if (rate >= 816000)
		clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
	else if (rate >= 456000)
		clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
	else
		clk_set_rate(emc_clk, 100000000);  /* emc 50Mhz */

	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);

#ifdef CONFIG_CPU_FREQ_DEBUG
	printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
	       freqs.old, freqs.new);
#endif

	ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
	if (ret) {
		pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
			freqs.new);
		return ret;
	}

	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);

	return 0;
}

static unsigned long tegra_cpu_highest_speed(void)
{
	unsigned long rate = 0;
	int i;

	for_each_online_cpu(i)
		rate = max(rate, target_cpu_speed[i]);
	return rate;
}

static int tegra_target(struct cpufreq_policy *policy,
		       unsigned int target_freq,
		       unsigned int relation)
{
	unsigned int idx;
	unsigned int freq;
	int ret = 0;

	mutex_lock(&tegra_cpu_lock);

	if (is_suspended) {
		ret = -EBUSY;
		goto out;
	}

	cpufreq_frequency_table_target(policy, freq_table, target_freq,
		relation, &idx);

	freq = freq_table[idx].frequency;

	target_cpu_speed[policy->cpu] = freq;

	ret = tegra_update_cpu_speed(policy, tegra_cpu_highest_speed());

out:
	mutex_unlock(&tegra_cpu_lock);
	return ret;
}

static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
	void *dummy)
{
	mutex_lock(&tegra_cpu_lock);
	if (event == PM_SUSPEND_PREPARE) {
		struct cpufreq_policy *policy = cpufreq_cpu_get(0);
		is_suspended = true;
		pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
			freq_table[0].frequency);
		tegra_update_cpu_speed(policy, freq_table[0].frequency);
		cpufreq_cpu_put(policy);
	} else if (event == PM_POST_SUSPEND) {
		is_suspended = false;
	}
	mutex_unlock(&tegra_cpu_lock);

	return NOTIFY_OK;
}

static struct notifier_block tegra_cpu_pm_notifier = {
	.notifier_call = tegra_pm_notify,
};

static int tegra_cpu_init(struct cpufreq_policy *policy)
{
	if (policy->cpu >= NUM_CPUS)
		return -EINVAL;

	clk_prepare_enable(emc_clk);
	clk_prepare_enable(cpu_clk);

	cpufreq_frequency_table_cpuinfo(policy, freq_table);
	cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
	policy->cur = tegra_getspeed(policy->cpu);
	target_cpu_speed[policy->cpu] = policy->cur;

	/* FIXME: what's the actual transition time? */
	policy->cpuinfo.transition_latency = 300 * 1000;

	cpumask_copy(policy->cpus, cpu_possible_mask);

	if (policy->cpu == 0)
		register_pm_notifier(&tegra_cpu_pm_notifier);

	return 0;
}

static int tegra_cpu_exit(struct cpufreq_policy *policy)
{
	cpufreq_frequency_table_cpuinfo(policy, freq_table);
	clk_disable_unprepare(emc_clk);
	return 0;
}

static struct freq_attr *tegra_cpufreq_attr[] = {
	&cpufreq_freq_attr_scaling_available_freqs,
	NULL,
};

static struct cpufreq_driver tegra_cpufreq_driver = {
	.verify		= tegra_verify_speed,
	.target		= tegra_target,
	.get		= tegra_getspeed,
	.init		= tegra_cpu_init,
	.exit		= tegra_cpu_exit,
	.name		= "tegra",
	.attr		= tegra_cpufreq_attr,
};

static int __init tegra_cpufreq_init(void)
{
	cpu_clk = clk_get_sys(NULL, "cpu");
	if (IS_ERR(cpu_clk))
		return PTR_ERR(cpu_clk);

	pll_x_clk = clk_get_sys(NULL, "pll_x");
	if (IS_ERR(pll_x_clk))
		return PTR_ERR(pll_x_clk);

	pll_p_clk = clk_get_sys(NULL, "pll_p_cclk");
	if (IS_ERR(pll_p_clk))
		return PTR_ERR(pll_p_clk);

	emc_clk = clk_get_sys("cpu", "emc");
	if (IS_ERR(emc_clk)) {
		clk_put(cpu_clk);
		return PTR_ERR(emc_clk);
	}

	return cpufreq_register_driver(&tegra_cpufreq_driver);
}

static void __exit tegra_cpufreq_exit(void)
{
        cpufreq_unregister_driver(&tegra_cpufreq_driver);
	clk_put(emc_clk);
	clk_put(cpu_clk);
}


MODULE_AUTHOR("Colin Cross <ccross@android.com>");
MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
MODULE_LICENSE("GPL");
module_init(tegra_cpufreq_init);
module_exit(tegra_cpufreq_exit);
Commit	Line	Data
7056d423	1	/*
7056d423 CC	2	* Copyright (C) 2010 Google, Inc.
	3	*
	4	* Author:
	5	* Colin Cross <ccross@google.com>
	6	* Based on arch/arm/plat-omap/cpu-omap.c, (C) 2005 Nokia Corporation
	7	*
	8	* This software is licensed under the terms of the GNU General Public
	9	* License version 2, as published by the Free Software Foundation, and
	10	* may be copied, distributed, and modified under those terms.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/types.h>
	22	#include <linux/sched.h>
	23	#include <linux/cpufreq.h>
	24	#include <linux/delay.h>
	25	#include <linux/init.h>
	26	#include <linux/err.h>
	27	#include <linux/clk.h>
	28	#include <linux/io.h>
1eb2ecf1	29	#include <linux/suspend.h>
7056d423	30
7056d423 CC	31	/* Frequency table index must be sequential starting at 0 */
7056d423 CC	32	static struct cpufreq_frequency_table freq_table[] = {
1eb2ecf1 CC	33	{ 0, 216000 },
	34	{ 1, 312000 },
	35	{ 2, 456000 },
	36	{ 3, 608000 },
	37	{ 4, 760000 },
	38	{ 5, 816000 },
	39	{ 6, 912000 },
	40	{ 7, 1000000 },
	41	{ 8, CPUFREQ_TABLE_END },
7056d423 CC	42	};
	43
	44	#define NUM_CPUS 2
	45
	46	static struct clk *cpu_clk;
ce32ddaa SW	47	static struct clk *pll_x_clk;
ce32ddaa SW	48	static struct clk *pll_p_clk;
7a281284	49	static struct clk *emc_clk;
7056d423 CC	50
7056d423 CC	51	static unsigned long target_cpu_speed[NUM_CPUS];
1eb2ecf1 CC	52	static DEFINE_MUTEX(tegra_cpu_lock);
1eb2ecf1 CC	53	static bool is_suspended;
7056d423	54
6686c733	55	static int tegra_verify_speed(struct cpufreq_policy *policy)
7056d423 CC	56	{
	57	return cpufreq_frequency_table_verify(policy, freq_table);
	58	}
	59
6686c733	60	static unsigned int tegra_getspeed(unsigned int cpu)
7056d423 CC	61	{
	62	unsigned long rate;
	63
	64	if (cpu >= NUM_CPUS)
	65	return 0;
	66
	67	rate = clk_get_rate(cpu_clk) / 1000;
	68	return rate;
	69	}
	70
ce32ddaa SW	71	static int tegra_cpu_clk_set_rate(unsigned long rate)
	72	{
	73	int ret;
	74
	75	/*
	76	* Take an extra reference to the main pll so it doesn't turn
	77	* off when we move the cpu off of it
	78	*/
	79	clk_prepare_enable(pll_x_clk);
	80
	81	ret = clk_set_parent(cpu_clk, pll_p_clk);
	82	if (ret) {
	83	pr_err("Failed to switch cpu to clock pll_p\n");
	84	goto out;
	85	}
	86
	87	if (rate == clk_get_rate(pll_p_clk))
	88	goto out;
	89
	90	ret = clk_set_rate(pll_x_clk, rate);
	91	if (ret) {
	92	pr_err("Failed to change pll_x to %lu\n", rate);
	93	goto out;
	94	}
	95
	96	ret = clk_set_parent(cpu_clk, pll_x_clk);
	97	if (ret) {
	98	pr_err("Failed to switch cpu to clock pll_x\n");
	99	goto out;
	100	}
	101
	102	out:
	103	clk_disable_unprepare(pll_x_clk);
	104	return ret;
	105	}
	106
b43a7ffb VK	107	static int tegra_update_cpu_speed(struct cpufreq_policy *policy,
b43a7ffb VK	108	unsigned long rate)
7056d423	109	{
7056d423 CC	110	int ret = 0;
	111	struct cpufreq_freqs freqs;
	112
7056d423 CC	113	freqs.old = tegra_getspeed(0);
	114	freqs.new = rate;
	115
	116	if (freqs.old == freqs.new)
	117	return ret;
	118
7a281284 CC	119	/*
	120	* Vote on memory bus frequency based on cpu frequency
	121	* This sets the minimum frequency, display or avp may request higher
	122	*/
	123	if (rate >= 816000)
	124	clk_set_rate(emc_clk, 600000000); /* cpu 816 MHz, emc max */
	125	else if (rate >= 456000)
	126	clk_set_rate(emc_clk, 300000000); /* cpu 456 MHz, emc 150Mhz */
	127	else
	128	clk_set_rate(emc_clk, 100000000); /* emc 50Mhz */
	129
b43a7ffb	130	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
7056d423 CC	131
	132	#ifdef CONFIG_CPU_FREQ_DEBUG
	133	printk(KERN_DEBUG "cpufreq-tegra: transition: %u --> %u\n",
	134	freqs.old, freqs.new);
	135	#endif
	136
ce32ddaa	137	ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
7056d423 CC	138	if (ret) {
	139	pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
	140	freqs.new);
	141	return ret;
	142	}
	143
b43a7ffb	144	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
7056d423 CC	145
	146	return 0;
	147	}
	148
1eb2ecf1 CC	149	static unsigned long tegra_cpu_highest_speed(void)
	150	{
	151	unsigned long rate = 0;
	152	int i;
	153
	154	for_each_online_cpu(i)
	155	rate = max(rate, target_cpu_speed[i]);
	156	return rate;
	157	}
	158
7056d423 CC	159	static int tegra_target(struct cpufreq_policy *policy,
	160	unsigned int target_freq,
	161	unsigned int relation)
	162	{
fdb684ac	163	unsigned int idx;
7056d423	164	unsigned int freq;
1eb2ecf1 CC	165	int ret = 0;
	166
	167	mutex_lock(&tegra_cpu_lock);
	168
	169	if (is_suspended) {
	170	ret = -EBUSY;
	171	goto out;
	172	}
7056d423 CC	173
	174	cpufreq_frequency_table_target(policy, freq_table, target_freq,
	175	relation, &idx);
	176
	177	freq = freq_table[idx].frequency;
	178
	179	target_cpu_speed[policy->cpu] = freq;
	180
b43a7ffb	181	ret = tegra_update_cpu_speed(policy, tegra_cpu_highest_speed());
1eb2ecf1 CC	182
	183	out:
	184	mutex_unlock(&tegra_cpu_lock);
	185	return ret;
7056d423 CC	186	}
7056d423 CC	187
1eb2ecf1 CC	188	static int tegra_pm_notify(struct notifier_block *nb, unsigned long event,
	189	void *dummy)
	190	{
	191	mutex_lock(&tegra_cpu_lock);
	192	if (event == PM_SUSPEND_PREPARE) {
b43a7ffb	193	struct cpufreq_policy *policy = cpufreq_cpu_get(0);
1eb2ecf1 CC	194	is_suspended = true;
	195	pr_info("Tegra cpufreq suspend: setting frequency to %d kHz\n",
	196	freq_table[0].frequency);
b43a7ffb VK	197	tegra_update_cpu_speed(policy, freq_table[0].frequency);
b43a7ffb VK	198	cpufreq_cpu_put(policy);
1eb2ecf1 CC	199	} else if (event == PM_POST_SUSPEND) {
	200	is_suspended = false;
	201	}
	202	mutex_unlock(&tegra_cpu_lock);
	203
	204	return NOTIFY_OK;
	205	}
	206
	207	static struct notifier_block tegra_cpu_pm_notifier = {
	208	.notifier_call = tegra_pm_notify,
	209	};
	210
7056d423 CC	211	static int tegra_cpu_init(struct cpufreq_policy *policy)
	212	{
	213	if (policy->cpu >= NUM_CPUS)
	214	return -EINVAL;
	215
6a5278d0 PG	216	clk_prepare_enable(emc_clk);
6a5278d0 PG	217	clk_prepare_enable(cpu_clk);
89a5fb84	218
7056d423 CC	219	cpufreq_frequency_table_cpuinfo(policy, freq_table);
	220	cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
	221	policy->cur = tegra_getspeed(policy->cpu);
	222	target_cpu_speed[policy->cpu] = policy->cur;
	223
	224	/* FIXME: what's the actual transition time? */
	225	policy->cpuinfo.transition_latency = 300 * 1000;
	226
16a44f82	227	cpumask_copy(policy->cpus, cpu_possible_mask);
7056d423	228
1eb2ecf1 CC	229	if (policy->cpu == 0)
	230	register_pm_notifier(&tegra_cpu_pm_notifier);
	231
7056d423 CC	232	return 0;
	233	}
	234
	235	static int tegra_cpu_exit(struct cpufreq_policy *policy)
	236	{
	237	cpufreq_frequency_table_cpuinfo(policy, freq_table);
6a5278d0	238	clk_disable_unprepare(emc_clk);
7056d423 CC	239	return 0;
	240	}
	241
	242	static struct freq_attr *tegra_cpufreq_attr[] = {
	243	&cpufreq_freq_attr_scaling_available_freqs,
	244	NULL,
	245	};
	246
	247	static struct cpufreq_driver tegra_cpufreq_driver = {
	248	.verify = tegra_verify_speed,
	249	.target = tegra_target,
	250	.get = tegra_getspeed,
	251	.init = tegra_cpu_init,
	252	.exit = tegra_cpu_exit,
	253	.name = "tegra",
	254	.attr = tegra_cpufreq_attr,
	255	};
	256
	257	static int __init tegra_cpufreq_init(void)
	258	{
c26cefd0 RZ	259	cpu_clk = clk_get_sys(NULL, "cpu");
	260	if (IS_ERR(cpu_clk))
	261	return PTR_ERR(cpu_clk);
	262
	263	pll_x_clk = clk_get_sys(NULL, "pll_x");
	264	if (IS_ERR(pll_x_clk))
	265	return PTR_ERR(pll_x_clk);
	266
61fd290d	267	pll_p_clk = clk_get_sys(NULL, "pll_p_cclk");
c26cefd0 RZ	268	if (IS_ERR(pll_p_clk))
	269	return PTR_ERR(pll_p_clk);
	270
	271	emc_clk = clk_get_sys("cpu", "emc");
	272	if (IS_ERR(emc_clk)) {
	273	clk_put(cpu_clk);
	274	return PTR_ERR(emc_clk);
	275	}
	276
7056d423 CC	277	return cpufreq_register_driver(&tegra_cpufreq_driver);
	278	}
	279
	280	static void __exit tegra_cpufreq_exit(void)
	281	{
	282	cpufreq_unregister_driver(&tegra_cpufreq_driver);
c26cefd0 RZ	283	clk_put(emc_clk);
c26cefd0 RZ	284	clk_put(cpu_clk);
7056d423 CC	285	}
	286
	287
	288	MODULE_AUTHOR("Colin Cross <ccross@android.com>");
	289	MODULE_DESCRIPTION("cpufreq driver for Nvidia Tegra2");
	290	MODULE_LICENSE("GPL");
	291	module_init(tegra_cpufreq_init);
	292	module_exit(tegra_cpufreq_exit);