[deliverable/linux.git] / drivers / cpuidle / cpuidle-exynos.c

/*
 * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Coupled cpuidle support based on the work of:
 *	Colin Cross <ccross@android.com>
 *	Daniel Lezcano <daniel.lezcano@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/export.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/platform_data/cpuidle-exynos.h>

#include <asm/suspend.h>
#include <asm/cpuidle.h>

static atomic_t exynos_idle_barrier;

static struct cpuidle_exynos_data *exynos_cpuidle_pdata;
static void (*exynos_enter_aftr)(void);

static int exynos_enter_coupled_lowpower(struct cpuidle_device *dev,
					 struct cpuidle_driver *drv,
					 int index)
{
	int ret;

	exynos_cpuidle_pdata->pre_enter_aftr();

	/*
	 * Waiting all cpus to reach this point at the same moment
	 */
	cpuidle_coupled_parallel_barrier(dev, &exynos_idle_barrier);

	/*
	 * Both cpus will reach this point at the same time
	 */
	ret = dev->cpu ? exynos_cpuidle_pdata->cpu1_powerdown()
		       : exynos_cpuidle_pdata->cpu0_enter_aftr();
	if (ret)
		index = ret;

	/*
	 * Waiting all cpus to finish the power sequence before going further
	 */
	cpuidle_coupled_parallel_barrier(dev, &exynos_idle_barrier);

	exynos_cpuidle_pdata->post_enter_aftr();

	return index;
}

static int exynos_enter_lowpower(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	int new_index = index;

	/* AFTR can only be entered when cores other than CPU0 are offline */
	if (num_online_cpus() > 1 || dev->cpu != 0)
		new_index = drv->safe_state_index;

	if (new_index == 0)
		return arm_cpuidle_simple_enter(dev, drv, new_index);

	exynos_enter_aftr();

	return new_index;
}

static struct cpuidle_driver exynos_idle_driver = {
	.name			= "exynos_idle",
	.owner			= THIS_MODULE,
	.states = {
		[0] = ARM_CPUIDLE_WFI_STATE,
		[1] = {
			.enter			= exynos_enter_lowpower,
			.exit_latency		= 300,
			.target_residency	= 100000,
			.name			= "C1",
			.desc			= "ARM power down",
		},
	},
	.state_count = 2,
	.safe_state_index = 0,
};

static struct cpuidle_driver exynos_coupled_idle_driver = {
	.name			= "exynos_coupled_idle",
	.owner			= THIS_MODULE,
	.states = {
		[0] = ARM_CPUIDLE_WFI_STATE,
		[1] = {
			.enter			= exynos_enter_coupled_lowpower,
			.exit_latency		= 5000,
			.target_residency	= 10000,
			.flags			= CPUIDLE_FLAG_COUPLED |
						  CPUIDLE_FLAG_TIMER_STOP,
			.name			= "C1",
			.desc			= "ARM power down",
		},
	},
	.state_count = 2,
	.safe_state_index = 0,
};

static int exynos_cpuidle_probe(struct platform_device *pdev)
{
	int ret;

	if (IS_ENABLED(CONFIG_SMP) &&
	    of_machine_is_compatible("samsung,exynos4210")) {
		exynos_cpuidle_pdata = pdev->dev.platform_data;

		ret = cpuidle_register(&exynos_coupled_idle_driver,
				       cpu_possible_mask);
	} else {
		exynos_enter_aftr = (void *)(pdev->dev.platform_data);

		ret = cpuidle_register(&exynos_idle_driver, NULL);
	}

	if (ret) {
		dev_err(&pdev->dev, "failed to register cpuidle driver\n");
		return ret;
	}

	return 0;
}

static struct platform_driver exynos_cpuidle_driver = {
	.probe	= exynos_cpuidle_probe,
	.driver = {
		.name = "exynos_cpuidle",
	},
};
builtin_platform_driver(exynos_cpuidle_driver);
Commit	Line	Data
712eddf7 BZ	1	/*
712eddf7 BZ	2	* Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
3d739985 JL	3	* http://www.samsung.com
3d739985 JL	4	*
712eddf7 BZ	5	* Coupled cpuidle support based on the work of:
	6	* Colin Cross <ccross@android.com>
	7	* Daniel Lezcano <daniel.lezcano@linaro.org>
	8	*
3d739985 JL	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
3d739985	14	#include <linux/cpuidle.h>
67173ca4	15	#include <linux/cpu_pm.h>
76ee4557	16	#include <linux/export.h>
84599238	17	#include <linux/init.h>
35baa336	18	#include <linux/platform_device.h>
712eddf7 BZ	19	#include <linux/of.h>
712eddf7 BZ	20	#include <linux/platform_data/cpuidle-exynos.h>
3d739985	21
67173ca4	22	#include <asm/suspend.h>
06c77b3c	23	#include <asm/cpuidle.h>
67173ca4	24
712eddf7 BZ	25	static atomic_t exynos_idle_barrier;
	26
	27	static struct cpuidle_exynos_data *exynos_cpuidle_pdata;
277f5046	28	static void (*exynos_enter_aftr)(void);
ccd458c1	29
712eddf7 BZ	30	static int exynos_enter_coupled_lowpower(struct cpuidle_device *dev,
	31	struct cpuidle_driver *drv,
	32	int index)
	33	{
	34	int ret;
	35
	36	exynos_cpuidle_pdata->pre_enter_aftr();
	37
	38	/*
	39	* Waiting all cpus to reach this point at the same moment
	40	*/
	41	cpuidle_coupled_parallel_barrier(dev, &exynos_idle_barrier);
	42
	43	/*
	44	* Both cpus will reach this point at the same time
	45	*/
	46	ret = dev->cpu ? exynos_cpuidle_pdata->cpu1_powerdown()
	47	: exynos_cpuidle_pdata->cpu0_enter_aftr();
	48	if (ret)
	49	index = ret;
	50
	51	/*
	52	* Waiting all cpus to finish the power sequence before going further
	53	*/
	54	cpuidle_coupled_parallel_barrier(dev, &exynos_idle_barrier);
	55
	56	exynos_cpuidle_pdata->post_enter_aftr();
	57
	58	return index;
	59	}
	60
7880e45e	61	static int exynos_enter_lowpower(struct cpuidle_device *dev,
67173ca4 ADK	62	struct cpuidle_driver *drv,
	63	int index)
	64	{
	65	int new_index = index;
	66
118f5c1d BZ	67	/* AFTR can only be entered when cores other than CPU0 are offline */
118f5c1d BZ	68	if (num_online_cpus() > 1 \|\| dev->cpu != 0)
67173ca4 ADK	69	new_index = drv->safe_state_index;
	70
	71	if (new_index == 0)
06c77b3c	72	return arm_cpuidle_simple_enter(dev, drv, new_index);
01601b34 TF	73
	74	exynos_enter_aftr();
	75
	76	return new_index;
67173ca4 ADK	77	}
67173ca4 ADK	78
7880e45e DL	79	static struct cpuidle_driver exynos_idle_driver = {
7880e45e DL	80	.name = "exynos_idle",
53af16a1 DL	81	.owner = THIS_MODULE,
	82	.states = {
	83	[0] = ARM_CPUIDLE_WFI_STATE,
	84	[1] = {
7880e45e	85	.enter = exynos_enter_lowpower,
53af16a1 DL	86	.exit_latency = 300,
53af16a1 DL	87	.target_residency = 100000,
53af16a1 DL	88	.name = "C1",
	89	.desc = "ARM power down",
	90	},
	91	},
	92	.state_count = 2,
	93	.safe_state_index = 0,
	94	};
	95
712eddf7 BZ	96	static struct cpuidle_driver exynos_coupled_idle_driver = {
	97	.name = "exynos_coupled_idle",
	98	.owner = THIS_MODULE,
	99	.states = {
	100	[0] = ARM_CPUIDLE_WFI_STATE,
	101	[1] = {
	102	.enter = exynos_enter_coupled_lowpower,
	103	.exit_latency = 5000,
	104	.target_residency = 10000,
	105	.flags = CPUIDLE_FLAG_COUPLED \|
	106	CPUIDLE_FLAG_TIMER_STOP,
	107	.name = "C1",
	108	.desc = "ARM power down",
	109	},
	110	},
	111	.state_count = 2,
	112	.safe_state_index = 0,
	113	};
	114
f612a4fb	115	static int exynos_cpuidle_probe(struct platform_device *pdev)
3d739985	116	{
043c86b6	117	int ret;
46bcfad7	118
cfdda353 BZ	119	if (IS_ENABLED(CONFIG_SMP) &&
cfdda353 BZ	120	of_machine_is_compatible("samsung,exynos4210")) {
712eddf7 BZ	121	exynos_cpuidle_pdata = pdev->dev.platform_data;
	122
	123	ret = cpuidle_register(&exynos_coupled_idle_driver,
	124	cpu_possible_mask);
	125	} else {
	126	exynos_enter_aftr = (void *)(pdev->dev.platform_data);
	127
	128	ret = cpuidle_register(&exynos_idle_driver, NULL);
	129	}
277f5046	130
5db9f436	131	if (ret) {
ae7c4c87	132	dev_err(&pdev->dev, "failed to register cpuidle driver\n");
5db9f436	133	return ret;
46bcfad7	134	}
3d739985	135
3d739985 JL	136	return 0;
3d739985 JL	137	}
35baa336 BZ	138
	139	static struct platform_driver exynos_cpuidle_driver = {
	140	.probe = exynos_cpuidle_probe,
	141	.driver = {
	142	.name = "exynos_cpuidle",
35baa336 BZ	143	},
35baa336 BZ	144	};
84599238	145	builtin_platform_driver(exynos_cpuidle_driver);