projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| bd2a337a MS |
1 | /* |
| 2 | * Copyright (C) 2012-2013 Xilinx | |
| 3 | * | |
| 4 | * CPU idle support for Xilinx Zynq | |
| 5 | * | |
| 6 | * based on arch/arm/mach-at91/cpuidle.c | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify it | |
| 9 | * under the terms and conditions of the GNU General Public License, | |
| 10 | * version 2, as published by the Free Software Foundation. | |
| 11 | * | |
| 12 | * This program is distributed in the hope it will be useful, but WITHOUT | |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 15 | * more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License along with | |
| 18 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
| 19 | * | |
| 20 | * The cpu idle uses wait-for-interrupt and RAM self refresh in order | |
| 21 | * to implement two idle states - | |
| 22 | * #1 wait-for-interrupt | |
| 23 | * #2 wait-for-interrupt and RAM self refresh | |
| 24 | * | |
| 25 | * Maintainer: Michal Simek <michal.simek@xilinx.com> | |
| 26 | */ | |
| 27 | ||
| 28 | #include <linux/init.h> | |
| 29 | #include <linux/cpu_pm.h> | |
| 30 | #include <linux/cpuidle.h> | |
| bd2a337a MS |
31 | #include <asm/proc-fns.h> |
| 32 | #include <asm/cpuidle.h> | |
| 33 | ||
| 34 | #define ZYNQ_MAX_STATES 2 | |
| 35 | ||
| 36 | /* Actual code that puts the SoC in different idle states */ | |
| 37 | static int zynq_enter_idle(struct cpuidle_device *dev, | |
| 38 | struct cpuidle_driver *drv, int index) | |
| 39 | { | |
| 40 | /* Devices must be stopped here */ | |
| 41 | cpu_pm_enter(); | |
| 42 | ||
| 43 | /* Add code for DDR self refresh start */ | |
| 44 | cpu_do_idle(); | |
| 45 | ||
| 46 | /* Add code for DDR self refresh stop */ | |
| 47 | cpu_pm_exit(); | |
| 48 | ||
| 49 | return index; | |
| 50 | } | |
| 51 | ||
| 52 | static struct cpuidle_driver zynq_idle_driver = { | |
| 53 | .name = "zynq_idle", | |
| 54 | .owner = THIS_MODULE, | |
| 55 | .states = { | |
| 56 | ARM_CPUIDLE_WFI_STATE, | |
| 57 | { | |
| 58 | .enter = zynq_enter_idle, | |
| 59 | .exit_latency = 10, | |
| 60 | .target_residency = 10000, | |
| 61 | .flags = CPUIDLE_FLAG_TIME_VALID | | |
| 62 | CPUIDLE_FLAG_TIMER_STOP, | |
| 63 | .name = "RAM_SR", | |
| 64 | .desc = "WFI and RAM Self Refresh", | |
| 65 | }, | |
| 66 | }, | |
| 67 | .safe_state_index = 0, | |
| 68 | .state_count = ZYNQ_MAX_STATES, | |
| 69 | }; | |
| 70 | ||
| 71 | /* Initialize CPU idle by registering the idle states */ | |
| 72 | static int __init zynq_cpuidle_init(void) | |
| 73 | { | |
| bd2a337a MS |
74 | pr_info("Xilinx Zynq CpuIdle Driver started\n"); |
| 75 | ||
| 76 | return cpuidle_register(&zynq_idle_driver, NULL); | |
| 77 | } | |
| 78 | ||
| 79 | device_initcall(zynq_cpuidle_init); |