Commit | Line | Data |
---|---|---|
049359d6 JH |
1 | /** |
2 | * AMCC SoC PPC4xx Crypto Driver | |
3 | * | |
4 | * Copyright (c) 2008 Applied Micro Circuits Corporation. | |
5 | * All rights reserved. James Hsiao <jhsiao@amcc.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * This is the header file for AMCC Crypto offload Linux device driver for | |
18 | * use with Linux CryptoAPI. | |
19 | ||
20 | */ | |
21 | ||
22 | #ifndef __CRYPTO4XX_CORE_H__ | |
23 | #define __CRYPTO4XX_CORE_H__ | |
24 | ||
4dc10c01 HX |
25 | #include <crypto/internal/hash.h> |
26 | ||
049359d6 JH |
27 | #define PPC460SX_SDR0_SRST 0x201 |
28 | #define PPC405EX_SDR0_SRST 0x200 | |
29 | #define PPC460EX_SDR0_SRST 0x201 | |
30 | #define PPC460EX_CE_RESET 0x08000000 | |
31 | #define PPC460SX_CE_RESET 0x20000000 | |
32 | #define PPC405EX_CE_RESET 0x00000008 | |
33 | ||
34 | #define CRYPTO4XX_CRYPTO_PRIORITY 300 | |
35 | #define PPC4XX_LAST_PD 63 | |
36 | #define PPC4XX_NUM_PD 64 | |
37 | #define PPC4XX_LAST_GD 1023 | |
38 | #define PPC4XX_NUM_GD 1024 | |
39 | #define PPC4XX_LAST_SD 63 | |
40 | #define PPC4XX_NUM_SD 64 | |
41 | #define PPC4XX_SD_BUFFER_SIZE 2048 | |
42 | ||
43 | #define PD_ENTRY_INUSE 1 | |
44 | #define PD_ENTRY_FREE 0 | |
45 | #define ERING_WAS_FULL 0xffffffff | |
46 | ||
47 | struct crypto4xx_device; | |
48 | ||
49 | struct pd_uinfo { | |
50 | struct crypto4xx_device *dev; | |
51 | u32 state; | |
52 | u32 using_sd; | |
53 | u32 first_gd; /* first gather discriptor | |
54 | used by this packet */ | |
55 | u32 num_gd; /* number of gather discriptor | |
56 | used by this packet */ | |
57 | u32 first_sd; /* first scatter discriptor | |
58 | used by this packet */ | |
59 | u32 num_sd; /* number of scatter discriptors | |
60 | used by this packet */ | |
61 | void *sa_va; /* shadow sa, when using cp from ctx->sa */ | |
62 | u32 sa_pa; | |
63 | void *sr_va; /* state record for shadow sa */ | |
64 | u32 sr_pa; | |
65 | struct scatterlist *dest_va; | |
66 | struct crypto_async_request *async_req; /* base crypto request | |
67 | for this packet */ | |
68 | }; | |
69 | ||
70 | struct crypto4xx_device { | |
71 | struct crypto4xx_core_device *core_dev; | |
72 | char *name; | |
73 | u64 ce_phy_address; | |
74 | void __iomem *ce_base; | |
75 | ||
76 | void *pdr; /* base address of packet | |
77 | descriptor ring */ | |
78 | dma_addr_t pdr_pa; /* physical address used to | |
79 | program ce pdr_base_register */ | |
80 | void *gdr; /* gather descriptor ring */ | |
81 | dma_addr_t gdr_pa; /* physical address used to | |
82 | program ce gdr_base_register */ | |
83 | void *sdr; /* scatter descriptor ring */ | |
84 | dma_addr_t sdr_pa; /* physical address used to | |
85 | program ce sdr_base_register */ | |
86 | void *scatter_buffer_va; | |
87 | dma_addr_t scatter_buffer_pa; | |
88 | u32 scatter_buffer_size; | |
89 | ||
90 | void *shadow_sa_pool; /* pool of memory for sa in pd_uinfo */ | |
91 | dma_addr_t shadow_sa_pool_pa; | |
92 | void *shadow_sr_pool; /* pool of memory for sr in pd_uinfo */ | |
93 | dma_addr_t shadow_sr_pool_pa; | |
94 | u32 pdr_tail; | |
95 | u32 pdr_head; | |
96 | u32 gdr_tail; | |
97 | u32 gdr_head; | |
98 | u32 sdr_tail; | |
99 | u32 sdr_head; | |
100 | void *pdr_uinfo; | |
101 | struct list_head alg_list; /* List of algorithm supported | |
102 | by this device */ | |
103 | }; | |
104 | ||
105 | struct crypto4xx_core_device { | |
106 | struct device *device; | |
107 | struct of_device *ofdev; | |
108 | struct crypto4xx_device *dev; | |
109 | u32 int_status; | |
110 | u32 irq; | |
111 | struct tasklet_struct tasklet; | |
112 | spinlock_t lock; | |
113 | }; | |
114 | ||
115 | struct crypto4xx_ctx { | |
116 | struct crypto4xx_device *dev; | |
117 | void *sa_in; | |
118 | dma_addr_t sa_in_dma_addr; | |
119 | void *sa_out; | |
120 | dma_addr_t sa_out_dma_addr; | |
121 | void *state_record; | |
122 | dma_addr_t state_record_dma_addr; | |
123 | u32 sa_len; | |
124 | u32 offset_to_sr_ptr; /* offset to state ptr, in dynamic sa */ | |
125 | u32 direction; | |
126 | u32 next_hdr; | |
127 | u32 save_iv; | |
128 | u32 pd_ctl_len; | |
129 | u32 pd_ctl; | |
130 | u32 bypass; | |
131 | u32 is_hash; | |
132 | u32 hash_final; | |
133 | }; | |
134 | ||
135 | struct crypto4xx_req_ctx { | |
136 | struct crypto4xx_device *dev; /* Device in which | |
137 | operation to send to */ | |
138 | void *sa; | |
139 | u32 sa_dma_addr; | |
140 | u16 sa_len; | |
141 | }; | |
142 | ||
4dc10c01 HX |
143 | struct crypto4xx_alg_common { |
144 | u32 type; | |
145 | union { | |
146 | struct crypto_alg cipher; | |
147 | struct ahash_alg hash; | |
148 | } u; | |
149 | }; | |
150 | ||
049359d6 JH |
151 | struct crypto4xx_alg { |
152 | struct list_head entry; | |
4dc10c01 | 153 | struct crypto4xx_alg_common alg; |
049359d6 JH |
154 | struct crypto4xx_device *dev; |
155 | }; | |
156 | ||
4dc10c01 HX |
157 | static inline struct crypto4xx_alg *crypto_alg_to_crypto4xx_alg( |
158 | struct crypto_alg *x) | |
159 | { | |
160 | switch (x->cra_flags & CRYPTO_ALG_TYPE_MASK) { | |
161 | case CRYPTO_ALG_TYPE_AHASH: | |
162 | return container_of(__crypto_ahash_alg(x), | |
163 | struct crypto4xx_alg, alg.u.hash); | |
164 | } | |
165 | ||
166 | return container_of(x, struct crypto4xx_alg, alg.u.cipher); | |
167 | } | |
049359d6 JH |
168 | |
169 | extern int crypto4xx_alloc_sa(struct crypto4xx_ctx *ctx, u32 size); | |
170 | extern void crypto4xx_free_sa(struct crypto4xx_ctx *ctx); | |
171 | extern u32 crypto4xx_alloc_sa_rctx(struct crypto4xx_ctx *ctx, | |
172 | struct crypto4xx_ctx *rctx); | |
173 | extern void crypto4xx_free_sa_rctx(struct crypto4xx_ctx *rctx); | |
174 | extern void crypto4xx_free_ctx(struct crypto4xx_ctx *ctx); | |
175 | extern u32 crypto4xx_alloc_state_record(struct crypto4xx_ctx *ctx); | |
176 | extern u32 get_dynamic_sa_offset_state_ptr_field(struct crypto4xx_ctx *ctx); | |
177 | extern u32 get_dynamic_sa_offset_key_field(struct crypto4xx_ctx *ctx); | |
178 | extern u32 get_dynamic_sa_iv_size(struct crypto4xx_ctx *ctx); | |
179 | extern void crypto4xx_memcpy_le(unsigned int *dst, | |
180 | const unsigned char *buf, int len); | |
181 | extern u32 crypto4xx_build_pd(struct crypto_async_request *req, | |
182 | struct crypto4xx_ctx *ctx, | |
183 | struct scatterlist *src, | |
184 | struct scatterlist *dst, | |
185 | unsigned int datalen, | |
186 | void *iv, u32 iv_len); | |
187 | extern int crypto4xx_setkey_aes_cbc(struct crypto_ablkcipher *cipher, | |
188 | const u8 *key, unsigned int keylen); | |
189 | extern int crypto4xx_encrypt(struct ablkcipher_request *req); | |
190 | extern int crypto4xx_decrypt(struct ablkcipher_request *req); | |
191 | extern int crypto4xx_sha1_alg_init(struct crypto_tfm *tfm); | |
192 | extern int crypto4xx_hash_digest(struct ahash_request *req); | |
193 | extern int crypto4xx_hash_final(struct ahash_request *req); | |
194 | extern int crypto4xx_hash_update(struct ahash_request *req); | |
195 | extern int crypto4xx_hash_init(struct ahash_request *req); | |
196 | #endif |