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crypto: atmel-aes - remove unused header includes
[deliverable/linux.git] / drivers / crypto / atmel-aes.c
CommitLineData
bd3c7b5c
NR		 1/*
2 * Cryptographic API.
3 *
4 * Support for ATMEL AES HW acceleration.
5 *
6 * Copyright (c) 2012 Eukréa Electromatique - ATMEL
7 * Author: Nicolas Royer <nicolas@eukrea.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 *
13 * Some ideas are from omap-aes.c driver.
14 */
15
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/slab.h>
20#include <linux/err.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23#include <linux/hw_random.h>
24#include <linux/platform_device.h>
25
26#include <linux/device.h>
bd3c7b5c
NR		 27#include <linux/init.h>
28#include <linux/errno.h>
29#include <linux/interrupt.h>
bd3c7b5c 30#include <linux/irq.h>
bd3c7b5c
NR		 31#include <linux/scatterlist.h>
32#include <linux/dma-mapping.h>
be943c7d 33#include <linux/of_device.h>
bd3c7b5c
NR		 34#include <linux/delay.h>
35#include <linux/crypto.h>
bd3c7b5c
NR		 36#include <crypto/scatterwalk.h>
37#include <crypto/algapi.h>
38#include <crypto/aes.h>
cadc4ab8 39#include <linux/platform_data/crypto-atmel.h>
be943c7d 40#include <dt-bindings/dma/at91.h>
bd3c7b5c
NR		 41#include "atmel-aes-regs.h"
42
88efd9a9
CP		 43#define ATMEL_AES_PRIORITY 300
44
bd3c7b5c
NR		 45#define CFB8_BLOCK_SIZE 1
46#define CFB16_BLOCK_SIZE 2
47#define CFB32_BLOCK_SIZE 4
48#define CFB64_BLOCK_SIZE 8
49
50/* AES flags */
cadc4ab8 51#define AES_FLAGS_MODE_MASK 0x03ff
bd3c7b5c
NR		 52#define AES_FLAGS_ENCRYPT BIT(0)
53#define AES_FLAGS_CBC BIT(1)
54#define AES_FLAGS_CFB BIT(2)
55#define AES_FLAGS_CFB8 BIT(3)
56#define AES_FLAGS_CFB16 BIT(4)
57#define AES_FLAGS_CFB32 BIT(5)
58#define AES_FLAGS_CFB64 BIT(6)
cadc4ab8
NR		 59#define AES_FLAGS_CFB128 BIT(7)
60#define AES_FLAGS_OFB BIT(8)
61#define AES_FLAGS_CTR BIT(9)
bd3c7b5c
NR		 62
63#define AES_FLAGS_INIT BIT(16)
64#define AES_FLAGS_DMA BIT(17)
65#define AES_FLAGS_BUSY BIT(18)
cadc4ab8 66#define AES_FLAGS_FAST BIT(19)
bd3c7b5c 67
cadc4ab8 68#define ATMEL_AES_QUEUE_LENGTH 50
bd3c7b5c
NR		 69
70#define ATMEL_AES_DMA_THRESHOLD 16
71
72
cadc4ab8
NR		 73struct atmel_aes_caps {
74 bool has_dualbuff;
75 bool has_cfb64;
76 u32 max_burst_size;
77};
78
bd3c7b5c
NR		 79struct atmel_aes_dev;
80
81struct atmel_aes_ctx {
82 struct atmel_aes_dev *dd;
83
84 int keylen;
85 u32 key[AES_KEYSIZE_256 / sizeof(u32)];
cadc4ab8
NR		 86
87 u16 block_size;
bd3c7b5c
NR		 88};
89
90struct atmel_aes_reqctx {
91 unsigned long mode;
92};
93
94struct atmel_aes_dma {
95 struct dma_chan *chan;
96 struct dma_slave_config dma_conf;
97};
98
99struct atmel_aes_dev {
100 struct list_head list;
101 unsigned long phys_base;
102 void __iomem *io_base;
103
104 struct atmel_aes_ctx *ctx;
105 struct device *dev;
106 struct clk *iclk;
107 int irq;
108
109 unsigned long flags;
110 int err;
111
112 spinlock_t lock;
113 struct crypto_queue queue;
114
115 struct tasklet_struct done_task;
116 struct tasklet_struct queue_task;
117
118 struct ablkcipher_request *req;
119 size_t total;
120
121 struct scatterlist *in_sg;
122 unsigned int nb_in_sg;
cadc4ab8 123 size_t in_offset;
bd3c7b5c
NR		 124 struct scatterlist *out_sg;
125 unsigned int nb_out_sg;
cadc4ab8 126 size_t out_offset;
bd3c7b5c
NR		 127
128 size_t bufcnt;
cadc4ab8
NR		 129 size_t buflen;
130 size_t dma_size;
bd3c7b5c 131
cadc4ab8
NR		 132 void *buf_in;
133 int dma_in;
134 dma_addr_t dma_addr_in;
bd3c7b5c
NR		 135 struct atmel_aes_dma dma_lch_in;
136
cadc4ab8
NR		 137 void *buf_out;
138 int dma_out;
139 dma_addr_t dma_addr_out;
bd3c7b5c
NR		 140 struct atmel_aes_dma dma_lch_out;
141
cadc4ab8
NR		 142 struct atmel_aes_caps caps;
143
bd3c7b5c
NR		 144 u32 hw_version;
145};
146
147struct atmel_aes_drv {
148 struct list_head dev_list;
149 spinlock_t lock;
150};
151
152static struct atmel_aes_drv atmel_aes = {
153 .dev_list = LIST_HEAD_INIT(atmel_aes.dev_list),
154 .lock = __SPIN_LOCK_UNLOCKED(atmel_aes.lock),
155};
156
157static int atmel_aes_sg_length(struct ablkcipher_request *req,
158 struct scatterlist *sg)
159{
160 unsigned int total = req->nbytes;
161 int sg_nb;
162 unsigned int len;
163 struct scatterlist *sg_list;
164
165 sg_nb = 0;
166 sg_list = sg;
167 total = req->nbytes;
168
169 while (total) {
170 len = min(sg_list->length, total);
171
172 sg_nb++;
173 total -= len;
174
175 sg_list = sg_next(sg_list);
176 if (!sg_list)
177 total = 0;
178 }
179
180 return sg_nb;
181}
182
cadc4ab8
NR		 183static int atmel_aes_sg_copy(struct scatterlist **sg, size_t *offset,
184 void *buf, size_t buflen, size_t total, int out)
185{
20ecae79 186 size_t count, off = 0;
cadc4ab8
NR		 187
188 while (buflen && total) {
189 count = min((*sg)->length - *offset, total);
190 count = min(count, buflen);
191
192 if (!count)
193 return off;
194
195 scatterwalk_map_and_copy(buf + off, *sg, *offset, count, out);
196
197 off += count;
198 buflen -= count;
199 *offset += count;
200 total -= count;
201
202 if (*offset == (*sg)->length) {
203 *sg = sg_next(*sg);
204 if (*sg)
205 *offset = 0;
206 else
207 total = 0;
208 }
209 }
210
211 return off;
212}
213
bd3c7b5c
NR		 214static inline u32 atmel_aes_read(struct atmel_aes_dev *dd, u32 offset)
215{
216 return readl_relaxed(dd->io_base + offset);
217}
218
219static inline void atmel_aes_write(struct atmel_aes_dev *dd,
220 u32 offset, u32 value)
221{
222 writel_relaxed(value, dd->io_base + offset);
223}
224
225static void atmel_aes_read_n(struct atmel_aes_dev *dd, u32 offset,
226 u32 *value, int count)
227{
228 for (; count--; value++, offset += 4)
229 *value = atmel_aes_read(dd, offset);
230}
231
232static void atmel_aes_write_n(struct atmel_aes_dev *dd, u32 offset,
c0b28d8c 233 const u32 *value, int count)
bd3c7b5c
NR		 234{
235 for (; count--; value++, offset += 4)
236 atmel_aes_write(dd, offset, *value);
237}
238
bd3c7b5c
NR		 239static struct atmel_aes_dev *atmel_aes_find_dev(struct atmel_aes_ctx *ctx)
240{
241 struct atmel_aes_dev *aes_dd = NULL;
242 struct atmel_aes_dev *tmp;
243
244 spin_lock_bh(&atmel_aes.lock);
245 if (!ctx->dd) {
246 list_for_each_entry(tmp, &atmel_aes.dev_list, list) {
247 aes_dd = tmp;
248 break;
249 }
250 ctx->dd = aes_dd;
251 } else {
252 aes_dd = ctx->dd;
253 }
254
255 spin_unlock_bh(&atmel_aes.lock);
256
257 return aes_dd;
258}
259
260static int atmel_aes_hw_init(struct atmel_aes_dev *dd)
261{
9d83d299
LC		 262 int err;
263
264 err = clk_prepare_enable(dd->iclk);
265 if (err)
266 return err;
bd3c7b5c
NR		 267
268 if (!(dd->flags & AES_FLAGS_INIT)) {
269 atmel_aes_write(dd, AES_CR, AES_CR_SWRST);
cadc4ab8 270 atmel_aes_write(dd, AES_MR, 0xE << AES_MR_CKEY_OFFSET);
bd3c7b5c
NR		 271 dd->flags |= AES_FLAGS_INIT;
272 dd->err = 0;
273 }
274
275 return 0;
276}
277
cadc4ab8
NR		 278static inline unsigned int atmel_aes_get_version(struct atmel_aes_dev *dd)
279{
280 return atmel_aes_read(dd, AES_HW_VERSION) & 0x00000fff;
281}
282
bd3c7b5c
NR		 283static void atmel_aes_hw_version_init(struct atmel_aes_dev *dd)
284{
285 atmel_aes_hw_init(dd);
286
cadc4ab8
NR		 287 dd->hw_version = atmel_aes_get_version(dd);
288
289 dev_info(dd->dev,
290 "version: 0x%x\n", dd->hw_version);
bd3c7b5c
NR		 291
292 clk_disable_unprepare(dd->iclk);
293}
294
295static void atmel_aes_finish_req(struct atmel_aes_dev *dd, int err)
296{
297 struct ablkcipher_request *req = dd->req;
298
299 clk_disable_unprepare(dd->iclk);
300 dd->flags &= ~AES_FLAGS_BUSY;
301
302 req->base.complete(&req->base, err);
303}
304
305static void atmel_aes_dma_callback(void *data)
306{
307 struct atmel_aes_dev *dd = data;
308
309 /* dma_lch_out - completed */
310 tasklet_schedule(&dd->done_task);
311}
312
cadc4ab8
NR		 313static int atmel_aes_crypt_dma(struct atmel_aes_dev *dd,
314 dma_addr_t dma_addr_in, dma_addr_t dma_addr_out, int length)
bd3c7b5c 315{
cadc4ab8 316 struct scatterlist sg[2];
bd3c7b5c 317 struct dma_async_tx_descriptor *in_desc, *out_desc;
bd3c7b5c 318
cadc4ab8 319 dd->dma_size = length;
bd3c7b5c 320
289b2623
LZ		 321 dma_sync_single_for_device(dd->dev, dma_addr_in, length,
322 DMA_TO_DEVICE);
323 dma_sync_single_for_device(dd->dev, dma_addr_out, length,
324 DMA_FROM_DEVICE);
bd3c7b5c 325
cadc4ab8
NR		 326 if (dd->flags & AES_FLAGS_CFB8) {
327 dd->dma_lch_in.dma_conf.dst_addr_width =
328 DMA_SLAVE_BUSWIDTH_1_BYTE;
329 dd->dma_lch_out.dma_conf.src_addr_width =
330 DMA_SLAVE_BUSWIDTH_1_BYTE;
331 } else if (dd->flags & AES_FLAGS_CFB16) {
332 dd->dma_lch_in.dma_conf.dst_addr_width =
333 DMA_SLAVE_BUSWIDTH_2_BYTES;
334 dd->dma_lch_out.dma_conf.src_addr_width =
335 DMA_SLAVE_BUSWIDTH_2_BYTES;
336 } else {
337 dd->dma_lch_in.dma_conf.dst_addr_width =
338 DMA_SLAVE_BUSWIDTH_4_BYTES;
339 dd->dma_lch_out.dma_conf.src_addr_width =
340 DMA_SLAVE_BUSWIDTH_4_BYTES;
341 }
bd3c7b5c 342
cadc4ab8
NR		 343 if (dd->flags & (AES_FLAGS_CFB8 | AES_FLAGS_CFB16 |
344 AES_FLAGS_CFB32 | AES_FLAGS_CFB64)) {
345 dd->dma_lch_in.dma_conf.src_maxburst = 1;
346 dd->dma_lch_in.dma_conf.dst_maxburst = 1;
347 dd->dma_lch_out.dma_conf.src_maxburst = 1;
348 dd->dma_lch_out.dma_conf.dst_maxburst = 1;
349 } else {
350 dd->dma_lch_in.dma_conf.src_maxburst = dd->caps.max_burst_size;
351 dd->dma_lch_in.dma_conf.dst_maxburst = dd->caps.max_burst_size;
352 dd->dma_lch_out.dma_conf.src_maxburst = dd->caps.max_burst_size;
353 dd->dma_lch_out.dma_conf.dst_maxburst = dd->caps.max_burst_size;
354 }
bd3c7b5c 355
cadc4ab8
NR		 356 dmaengine_slave_config(dd->dma_lch_in.chan, &dd->dma_lch_in.dma_conf);
357 dmaengine_slave_config(dd->dma_lch_out.chan, &dd->dma_lch_out.dma_conf);
bd3c7b5c 358
cadc4ab8 359 dd->flags |= AES_FLAGS_DMA;
bd3c7b5c 360
cadc4ab8
NR		 361 sg_init_table(&sg[0], 1);
362 sg_dma_address(&sg[0]) = dma_addr_in;
363 sg_dma_len(&sg[0]) = length;
bd3c7b5c 364
cadc4ab8
NR		 365 sg_init_table(&sg[1], 1);
366 sg_dma_address(&sg[1]) = dma_addr_out;
367 sg_dma_len(&sg[1]) = length;
368
369 in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, &sg[0],
370 1, DMA_MEM_TO_DEV,
371 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
372 if (!in_desc)
373 return -EINVAL;
bd3c7b5c 374
cadc4ab8
NR		 375 out_desc = dmaengine_prep_slave_sg(dd->dma_lch_out.chan, &sg[1],
376 1, DMA_DEV_TO_MEM,
377 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
bd3c7b5c 378 if (!out_desc)
cadc4ab8 379 return -EINVAL;
bd3c7b5c
NR		 380
381 out_desc->callback = atmel_aes_dma_callback;
382 out_desc->callback_param = dd;
383
bd3c7b5c
NR		 384 dmaengine_submit(out_desc);
385 dma_async_issue_pending(dd->dma_lch_out.chan);
386
387 dmaengine_submit(in_desc);
388 dma_async_issue_pending(dd->dma_lch_in.chan);
389
390 return 0;
bd3c7b5c
NR		 391}
392
393static int atmel_aes_crypt_cpu_start(struct atmel_aes_dev *dd)
394{
395 dd->flags &= ~AES_FLAGS_DMA;
396
289b2623
LZ		 397 dma_sync_single_for_cpu(dd->dev, dd->dma_addr_in,
398 dd->dma_size, DMA_TO_DEVICE);
399 dma_sync_single_for_cpu(dd->dev, dd->dma_addr_out,
400 dd->dma_size, DMA_FROM_DEVICE);
401
bd3c7b5c
NR		 402 /* use cache buffers */
403 dd->nb_in_sg = atmel_aes_sg_length(dd->req, dd->in_sg);
404 if (!dd->nb_in_sg)
405 return -EINVAL;
406
407 dd->nb_out_sg = atmel_aes_sg_length(dd->req, dd->out_sg);
7b5c253c 408 if (!dd->nb_out_sg)
bd3c7b5c
NR		 409 return -EINVAL;
410
411 dd->bufcnt = sg_copy_to_buffer(dd->in_sg, dd->nb_in_sg,
412 dd->buf_in, dd->total);
413
414 if (!dd->bufcnt)
415 return -EINVAL;
416
417 dd->total -= dd->bufcnt;
418
419 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
420 atmel_aes_write_n(dd, AES_IDATAR(0), (u32 *) dd->buf_in,
421 dd->bufcnt >> 2);
422
423 return 0;
424}
425
426static int atmel_aes_crypt_dma_start(struct atmel_aes_dev *dd)
427{
cadc4ab8
NR		 428 int err, fast = 0, in, out;
429 size_t count;
430 dma_addr_t addr_in, addr_out;
431
432 if ((!dd->in_offset) && (!dd->out_offset)) {
433 /* check for alignment */
434 in = IS_ALIGNED((u32)dd->in_sg->offset, sizeof(u32)) &&
435 IS_ALIGNED(dd->in_sg->length, dd->ctx->block_size);
436 out = IS_ALIGNED((u32)dd->out_sg->offset, sizeof(u32)) &&
437 IS_ALIGNED(dd->out_sg->length, dd->ctx->block_size);
438 fast = in && out;
439
440 if (sg_dma_len(dd->in_sg) != sg_dma_len(dd->out_sg))
441 fast = 0;
442 }
443
444
445 if (fast) {
20ecae79
AB		 446 count = min_t(size_t, dd->total, sg_dma_len(dd->in_sg));
447 count = min_t(size_t, count, sg_dma_len(dd->out_sg));
cadc4ab8
NR		 448
449 err = dma_map_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
450 if (!err) {
451 dev_err(dd->dev, "dma_map_sg() error\n");
452 return -EINVAL;
453 }
454
455 err = dma_map_sg(dd->dev, dd->out_sg, 1,
456 DMA_FROM_DEVICE);
457 if (!err) {
458 dev_err(dd->dev, "dma_map_sg() error\n");
459 dma_unmap_sg(dd->dev, dd->in_sg, 1,
460 DMA_TO_DEVICE);
461 return -EINVAL;
462 }
463
464 addr_in = sg_dma_address(dd->in_sg);
465 addr_out = sg_dma_address(dd->out_sg);
466
467 dd->flags |= AES_FLAGS_FAST;
bd3c7b5c 468
bd3c7b5c 469 } else {
289b2623
LZ		 470 dma_sync_single_for_cpu(dd->dev, dd->dma_addr_in,
471 dd->dma_size, DMA_TO_DEVICE);
472
cadc4ab8
NR		 473 /* use cache buffers */
474 count = atmel_aes_sg_copy(&dd->in_sg, &dd->in_offset,
475 dd->buf_in, dd->buflen, dd->total, 0);
476
477 addr_in = dd->dma_addr_in;
478 addr_out = dd->dma_addr_out;
479
480 dd->flags &= ~AES_FLAGS_FAST;
bd3c7b5c
NR		 481 }
482
cadc4ab8 483 dd->total -= count;
bd3c7b5c 484
cadc4ab8
NR		 485 err = atmel_aes_crypt_dma(dd, addr_in, addr_out, count);
486
487 if (err && (dd->flags & AES_FLAGS_FAST)) {
488 dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
489 dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_TO_DEVICE);
490 }
bd3c7b5c
NR		 491
492 return err;
493}
494
495static int atmel_aes_write_ctrl(struct atmel_aes_dev *dd)
496{
497 int err;
498 u32 valcr = 0, valmr = 0;
499
500 err = atmel_aes_hw_init(dd);
501
502 if (err)
503 return err;
504
505 /* MR register must be set before IV registers */
506 if (dd->ctx->keylen == AES_KEYSIZE_128)
507 valmr |= AES_MR_KEYSIZE_128;
508 else if (dd->ctx->keylen == AES_KEYSIZE_192)
509 valmr |= AES_MR_KEYSIZE_192;
510 else
511 valmr |= AES_MR_KEYSIZE_256;
512
513 if (dd->flags & AES_FLAGS_CBC) {
514 valmr |= AES_MR_OPMOD_CBC;
515 } else if (dd->flags & AES_FLAGS_CFB) {
516 valmr |= AES_MR_OPMOD_CFB;
517 if (dd->flags & AES_FLAGS_CFB8)
518 valmr |= AES_MR_CFBS_8b;
519 else if (dd->flags & AES_FLAGS_CFB16)
520 valmr |= AES_MR_CFBS_16b;
521 else if (dd->flags & AES_FLAGS_CFB32)
522 valmr |= AES_MR_CFBS_32b;
523 else if (dd->flags & AES_FLAGS_CFB64)
524 valmr |= AES_MR_CFBS_64b;
cadc4ab8
NR		 525 else if (dd->flags & AES_FLAGS_CFB128)
526 valmr |= AES_MR_CFBS_128b;
bd3c7b5c
NR		 527 } else if (dd->flags & AES_FLAGS_OFB) {
528 valmr |= AES_MR_OPMOD_OFB;
529 } else if (dd->flags & AES_FLAGS_CTR) {
530 valmr |= AES_MR_OPMOD_CTR;
531 } else {
532 valmr |= AES_MR_OPMOD_ECB;
533 }
534
535 if (dd->flags & AES_FLAGS_ENCRYPT)
536 valmr |= AES_MR_CYPHER_ENC;
537
538 if (dd->total > ATMEL_AES_DMA_THRESHOLD) {
539 valmr |= AES_MR_SMOD_IDATAR0;
cadc4ab8 540 if (dd->caps.has_dualbuff)
bd3c7b5c
NR		 541 valmr |= AES_MR_DUALBUFF;
542 } else {
543 valmr |= AES_MR_SMOD_AUTO;
544 }
545
546 atmel_aes_write(dd, AES_CR, valcr);
547 atmel_aes_write(dd, AES_MR, valmr);
548
549 atmel_aes_write_n(dd, AES_KEYWR(0), dd->ctx->key,
550 dd->ctx->keylen >> 2);
551
552 if (((dd->flags & AES_FLAGS_CBC) || (dd->flags & AES_FLAGS_CFB) ||
553 (dd->flags & AES_FLAGS_OFB) || (dd->flags & AES_FLAGS_CTR)) &&
554 dd->req->info) {
555 atmel_aes_write_n(dd, AES_IVR(0), dd->req->info, 4);
556 }
557
558 return 0;
559}
560
561static int atmel_aes_handle_queue(struct atmel_aes_dev *dd,
562 struct ablkcipher_request *req)
563{
564 struct crypto_async_request *async_req, *backlog;
565 struct atmel_aes_ctx *ctx;
566 struct atmel_aes_reqctx *rctx;
567 unsigned long flags;
568 int err, ret = 0;
569
570 spin_lock_irqsave(&dd->lock, flags);
571 if (req)
572 ret = ablkcipher_enqueue_request(&dd->queue, req);
573 if (dd->flags & AES_FLAGS_BUSY) {
574 spin_unlock_irqrestore(&dd->lock, flags);
575 return ret;
576 }
577 backlog = crypto_get_backlog(&dd->queue);
578 async_req = crypto_dequeue_request(&dd->queue);
579 if (async_req)
580 dd->flags |= AES_FLAGS_BUSY;
581 spin_unlock_irqrestore(&dd->lock, flags);
582
583 if (!async_req)
584 return ret;
585
586 if (backlog)
587 backlog->complete(backlog, -EINPROGRESS);
588
589 req = ablkcipher_request_cast(async_req);
590
591 /* assign new request to device */
592 dd->req = req;
593 dd->total = req->nbytes;
cadc4ab8 594 dd->in_offset = 0;
bd3c7b5c 595 dd->in_sg = req->src;
cadc4ab8 596 dd->out_offset = 0;
bd3c7b5c
NR		 597 dd->out_sg = req->dst;
598
599 rctx = ablkcipher_request_ctx(req);
600 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
601 rctx->mode &= AES_FLAGS_MODE_MASK;
602 dd->flags = (dd->flags & ~AES_FLAGS_MODE_MASK) | rctx->mode;
603 dd->ctx = ctx;
604 ctx->dd = dd;
605
606 err = atmel_aes_write_ctrl(dd);
607 if (!err) {
608 if (dd->total > ATMEL_AES_DMA_THRESHOLD)
609 err = atmel_aes_crypt_dma_start(dd);
610 else
611 err = atmel_aes_crypt_cpu_start(dd);
612 }
613 if (err) {
614 /* aes_task will not finish it, so do it here */
615 atmel_aes_finish_req(dd, err);
616 tasklet_schedule(&dd->queue_task);
617 }
618
619 return ret;
620}
621
622static int atmel_aes_crypt_dma_stop(struct atmel_aes_dev *dd)
623{
624 int err = -EINVAL;
cadc4ab8 625 size_t count;
bd3c7b5c
NR		 626
627 if (dd->flags & AES_FLAGS_DMA) {
bd3c7b5c 628 err = 0;
cadc4ab8
NR		 629 if (dd->flags & AES_FLAGS_FAST) {
630 dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
631 dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
632 } else {
9cd22323 633 dma_sync_single_for_cpu(dd->dev, dd->dma_addr_out,
cadc4ab8
NR		 634 dd->dma_size, DMA_FROM_DEVICE);
635
636 /* copy data */
637 count = atmel_aes_sg_copy(&dd->out_sg, &dd->out_offset,
638 dd->buf_out, dd->buflen, dd->dma_size, 1);
639 if (count != dd->dma_size) {
640 err = -EINVAL;
20ecae79 641 pr_err("not all data converted: %zu\n", count);
cadc4ab8
NR		 642 }
643 }
bd3c7b5c
NR		 644 }
645
646 return err;
647}
648
cadc4ab8
NR		 649
650static int atmel_aes_buff_init(struct atmel_aes_dev *dd)
651{
652 int err = -ENOMEM;
653
654 dd->buf_in = (void *)__get_free_pages(GFP_KERNEL, 0);
655 dd->buf_out = (void *)__get_free_pages(GFP_KERNEL, 0);
656 dd->buflen = PAGE_SIZE;
657 dd->buflen &= ~(AES_BLOCK_SIZE - 1);
658
659 if (!dd->buf_in || !dd->buf_out) {
660 dev_err(dd->dev, "unable to alloc pages.\n");
661 goto err_alloc;
662 }
663
664 /* MAP here */
665 dd->dma_addr_in = dma_map_single(dd->dev, dd->buf_in,
666 dd->buflen, DMA_TO_DEVICE);
667 if (dma_mapping_error(dd->dev, dd->dma_addr_in)) {
20ecae79 668 dev_err(dd->dev, "dma %zd bytes error\n", dd->buflen);
cadc4ab8
NR		 669 err = -EINVAL;
670 goto err_map_in;
671 }
672
673 dd->dma_addr_out = dma_map_single(dd->dev, dd->buf_out,
674 dd->buflen, DMA_FROM_DEVICE);
675 if (dma_mapping_error(dd->dev, dd->dma_addr_out)) {
20ecae79 676 dev_err(dd->dev, "dma %zd bytes error\n", dd->buflen);
cadc4ab8
NR		 677 err = -EINVAL;
678 goto err_map_out;
679 }
680
681 return 0;
682
683err_map_out:
684 dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen,
685 DMA_TO_DEVICE);
686err_map_in:
088f628c 687err_alloc:
cadc4ab8
NR		 688 free_page((unsigned long)dd->buf_out);
689 free_page((unsigned long)dd->buf_in);
cadc4ab8
NR		 690 if (err)
691 pr_err("error: %d\n", err);
692 return err;
693}
694
695static void atmel_aes_buff_cleanup(struct atmel_aes_dev *dd)
696{
697 dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen,
698 DMA_FROM_DEVICE);
699 dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen,
700 DMA_TO_DEVICE);
701 free_page((unsigned long)dd->buf_out);
702 free_page((unsigned long)dd->buf_in);
703}
704
bd3c7b5c
NR		 705static int atmel_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
706{
707 struct atmel_aes_ctx *ctx = crypto_ablkcipher_ctx(
708 crypto_ablkcipher_reqtfm(req));
709 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
710 struct atmel_aes_dev *dd;
711
cadc4ab8
NR		 712 if (mode & AES_FLAGS_CFB8) {
713 if (!IS_ALIGNED(req->nbytes, CFB8_BLOCK_SIZE)) {
714 pr_err("request size is not exact amount of CFB8 blocks\n");
715 return -EINVAL;
716 }
717 ctx->block_size = CFB8_BLOCK_SIZE;
718 } else if (mode & AES_FLAGS_CFB16) {
719 if (!IS_ALIGNED(req->nbytes, CFB16_BLOCK_SIZE)) {
720 pr_err("request size is not exact amount of CFB16 blocks\n");
721 return -EINVAL;
722 }
723 ctx->block_size = CFB16_BLOCK_SIZE;
724 } else if (mode & AES_FLAGS_CFB32) {
725 if (!IS_ALIGNED(req->nbytes, CFB32_BLOCK_SIZE)) {
726 pr_err("request size is not exact amount of CFB32 blocks\n");
727 return -EINVAL;
728 }
729 ctx->block_size = CFB32_BLOCK_SIZE;
9f84951f
LZ		 730 } else if (mode & AES_FLAGS_CFB64) {
731 if (!IS_ALIGNED(req->nbytes, CFB64_BLOCK_SIZE)) {
732 pr_err("request size is not exact amount of CFB64 blocks\n");
733 return -EINVAL;
734 }
735 ctx->block_size = CFB64_BLOCK_SIZE;
cadc4ab8
NR		 736 } else {
737 if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) {
738 pr_err("request size is not exact amount of AES blocks\n");
739 return -EINVAL;
740 }
741 ctx->block_size = AES_BLOCK_SIZE;
bd3c7b5c
NR		 742 }
743
744 dd = atmel_aes_find_dev(ctx);
745 if (!dd)
746 return -ENODEV;
747
748 rctx->mode = mode;
749
750 return atmel_aes_handle_queue(dd, req);
751}
752
753static bool atmel_aes_filter(struct dma_chan *chan, void *slave)
754{
755 struct at_dma_slave *sl = slave;
756
757 if (sl && sl->dma_dev == chan->device->dev) {
758 chan->private = sl;
759 return true;
760 } else {
761 return false;
762 }
763}
764
cadc4ab8
NR		 765static int atmel_aes_dma_init(struct atmel_aes_dev *dd,
766 struct crypto_platform_data *pdata)
bd3c7b5c
NR		 767{
768 int err = -ENOMEM;
be943c7d
NF		 769 dma_cap_mask_t mask;
770
771 dma_cap_zero(mask);
772 dma_cap_set(DMA_SLAVE, mask);
773
774 /* Try to grab 2 DMA channels */
775 dd->dma_lch_in.chan = dma_request_slave_channel_compat(mask,
776 atmel_aes_filter, &pdata->dma_slave->rxdata, dd->dev, "tx");
777 if (!dd->dma_lch_in.chan)
778 goto err_dma_in;
779
780 dd->dma_lch_in.dma_conf.direction = DMA_MEM_TO_DEV;
781 dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base +
782 AES_IDATAR(0);
783 dd->dma_lch_in.dma_conf.src_maxburst = dd->caps.max_burst_size;
784 dd->dma_lch_in.dma_conf.src_addr_width =
785 DMA_SLAVE_BUSWIDTH_4_BYTES;
786 dd->dma_lch_in.dma_conf.dst_maxburst = dd->caps.max_burst_size;
787 dd->dma_lch_in.dma_conf.dst_addr_width =
788 DMA_SLAVE_BUSWIDTH_4_BYTES;
789 dd->dma_lch_in.dma_conf.device_fc = false;
790
791 dd->dma_lch_out.chan = dma_request_slave_channel_compat(mask,
792 atmel_aes_filter, &pdata->dma_slave->txdata, dd->dev, "rx");
793 if (!dd->dma_lch_out.chan)
794 goto err_dma_out;
795
796 dd->dma_lch_out.dma_conf.direction = DMA_DEV_TO_MEM;
797 dd->dma_lch_out.dma_conf.src_addr = dd->phys_base +
798 AES_ODATAR(0);
799 dd->dma_lch_out.dma_conf.src_maxburst = dd->caps.max_burst_size;
800 dd->dma_lch_out.dma_conf.src_addr_width =
801 DMA_SLAVE_BUSWIDTH_4_BYTES;
802 dd->dma_lch_out.dma_conf.dst_maxburst = dd->caps.max_burst_size;
803 dd->dma_lch_out.dma_conf.dst_addr_width =
804 DMA_SLAVE_BUSWIDTH_4_BYTES;
805 dd->dma_lch_out.dma_conf.device_fc = false;
bd3c7b5c 806
be943c7d 807 return 0;
bd3c7b5c
NR		 808
809err_dma_out:
810 dma_release_channel(dd->dma_lch_in.chan);
811err_dma_in:
be943c7d 812 dev_warn(dd->dev, "no DMA channel available\n");
bd3c7b5c
NR		 813 return err;
814}
815
816static void atmel_aes_dma_cleanup(struct atmel_aes_dev *dd)
817{
818 dma_release_channel(dd->dma_lch_in.chan);
819 dma_release_channel(dd->dma_lch_out.chan);
820}
821
822static int atmel_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
823 unsigned int keylen)
824{
825 struct atmel_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
826
827 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
828 keylen != AES_KEYSIZE_256) {
829 crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
830 return -EINVAL;
831 }
832
833 memcpy(ctx->key, key, keylen);
834 ctx->keylen = keylen;
835
836 return 0;
837}
838
839static int atmel_aes_ecb_encrypt(struct ablkcipher_request *req)
840{
841 return atmel_aes_crypt(req,
842 AES_FLAGS_ENCRYPT);
843}
844
845static int atmel_aes_ecb_decrypt(struct ablkcipher_request *req)
846{
847 return atmel_aes_crypt(req,
848 0);
849}
850
851static int atmel_aes_cbc_encrypt(struct ablkcipher_request *req)
852{
853 return atmel_aes_crypt(req,
854 AES_FLAGS_ENCRYPT | AES_FLAGS_CBC);
855}
856
857static int atmel_aes_cbc_decrypt(struct ablkcipher_request *req)
858{
859 return atmel_aes_crypt(req,
860 AES_FLAGS_CBC);
861}
862
863static int atmel_aes_ofb_encrypt(struct ablkcipher_request *req)
864{
865 return atmel_aes_crypt(req,
866 AES_FLAGS_ENCRYPT | AES_FLAGS_OFB);
867}
868
869static int atmel_aes_ofb_decrypt(struct ablkcipher_request *req)
870{
871 return atmel_aes_crypt(req,
872 AES_FLAGS_OFB);
873}
874
875static int atmel_aes_cfb_encrypt(struct ablkcipher_request *req)
876{
877 return atmel_aes_crypt(req,
cadc4ab8 878 AES_FLAGS_ENCRYPT | AES_FLAGS_CFB | AES_FLAGS_CFB128);
bd3c7b5c
NR		 879}
880
881static int atmel_aes_cfb_decrypt(struct ablkcipher_request *req)
882{
883 return atmel_aes_crypt(req,
cadc4ab8 884 AES_FLAGS_CFB | AES_FLAGS_CFB128);
bd3c7b5c
NR		 885}
886
887static int atmel_aes_cfb64_encrypt(struct ablkcipher_request *req)
888{
889 return atmel_aes_crypt(req,
890 AES_FLAGS_ENCRYPT | AES_FLAGS_CFB | AES_FLAGS_CFB64);
891}
892
893static int atmel_aes_cfb64_decrypt(struct ablkcipher_request *req)
894{
895 return atmel_aes_crypt(req,
896 AES_FLAGS_CFB | AES_FLAGS_CFB64);
897}
898
899static int atmel_aes_cfb32_encrypt(struct ablkcipher_request *req)
900{
901 return atmel_aes_crypt(req,
902 AES_FLAGS_ENCRYPT | AES_FLAGS_CFB | AES_FLAGS_CFB32);
903}
904
905static int atmel_aes_cfb32_decrypt(struct ablkcipher_request *req)
906{
907 return atmel_aes_crypt(req,
908 AES_FLAGS_CFB | AES_FLAGS_CFB32);
909}
910
911static int atmel_aes_cfb16_encrypt(struct ablkcipher_request *req)
912{
913 return atmel_aes_crypt(req,
914 AES_FLAGS_ENCRYPT | AES_FLAGS_CFB | AES_FLAGS_CFB16);
915}
916
917static int atmel_aes_cfb16_decrypt(struct ablkcipher_request *req)
918{
919 return atmel_aes_crypt(req,
920 AES_FLAGS_CFB | AES_FLAGS_CFB16);
921}
922
923static int atmel_aes_cfb8_encrypt(struct ablkcipher_request *req)
924{
925 return atmel_aes_crypt(req,
926 AES_FLAGS_ENCRYPT | AES_FLAGS_CFB | AES_FLAGS_CFB8);
927}
928
929static int atmel_aes_cfb8_decrypt(struct ablkcipher_request *req)
930{
931 return atmel_aes_crypt(req,
932 AES_FLAGS_CFB | AES_FLAGS_CFB8);
933}
934
935static int atmel_aes_ctr_encrypt(struct ablkcipher_request *req)
936{
937 return atmel_aes_crypt(req,
938 AES_FLAGS_ENCRYPT | AES_FLAGS_CTR);
939}
940
941static int atmel_aes_ctr_decrypt(struct ablkcipher_request *req)
942{
943 return atmel_aes_crypt(req,
944 AES_FLAGS_CTR);
945}
946
947static int atmel_aes_cra_init(struct crypto_tfm *tfm)
948{
949 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
950
951 return 0;
952}
953
954static void atmel_aes_cra_exit(struct crypto_tfm *tfm)
955{
956}
957
958static struct crypto_alg aes_algs[] = {
959{
960 .cra_name = "ecb(aes)",
961 .cra_driver_name = "atmel-ecb-aes",
88efd9a9 962 .cra_priority = ATMEL_AES_PRIORITY,
bd3c7b5c
NR		 963 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
964 .cra_blocksize = AES_BLOCK_SIZE,
965 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
cadc4ab8 966 .cra_alignmask = 0xf,
bd3c7b5c
NR		 967 .cra_type = &crypto_ablkcipher_type,
968 .cra_module = THIS_MODULE,
969 .cra_init = atmel_aes_cra_init,
970 .cra_exit = atmel_aes_cra_exit,
971 .cra_u.ablkcipher = {
972 .min_keysize = AES_MIN_KEY_SIZE,
973 .max_keysize = AES_MAX_KEY_SIZE,
974 .setkey = atmel_aes_setkey,
975 .encrypt = atmel_aes_ecb_encrypt,
976 .decrypt = atmel_aes_ecb_decrypt,
977 }
978},
979{
980 .cra_name = "cbc(aes)",
981 .cra_driver_name = "atmel-cbc-aes",
88efd9a9 982 .cra_priority = ATMEL_AES_PRIORITY,
bd3c7b5c
NR		 983 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
984 .cra_blocksize = AES_BLOCK_SIZE,
985 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
cadc4ab8 986 .cra_alignmask = 0xf,
bd3c7b5c
NR		 987 .cra_type = &crypto_ablkcipher_type,
988 .cra_module = THIS_MODULE,
989 .cra_init = atmel_aes_cra_init,
990 .cra_exit = atmel_aes_cra_exit,
991 .cra_u.ablkcipher = {
992 .min_keysize = AES_MIN_KEY_SIZE,
993 .max_keysize = AES_MAX_KEY_SIZE,
994 .ivsize = AES_BLOCK_SIZE,
995 .setkey = atmel_aes_setkey,
996 .encrypt = atmel_aes_cbc_encrypt,
997 .decrypt = atmel_aes_cbc_decrypt,
998 }
999},
1000{
1001 .cra_name = "ofb(aes)",
1002 .cra_driver_name = "atmel-ofb-aes",
88efd9a9 1003 .cra_priority = ATMEL_AES_PRIORITY,
bd3c7b5c
NR		 1004 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1005 .cra_blocksize = AES_BLOCK_SIZE,
1006 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
cadc4ab8 1007 .cra_alignmask = 0xf,
bd3c7b5c
NR		 1008 .cra_type = &crypto_ablkcipher_type,
1009 .cra_module = THIS_MODULE,
1010 .cra_init = atmel_aes_cra_init,
1011 .cra_exit = atmel_aes_cra_exit,
1012 .cra_u.ablkcipher = {
1013 .min_keysize = AES_MIN_KEY_SIZE,
1014 .max_keysize = AES_MAX_KEY_SIZE,
1015 .ivsize = AES_BLOCK_SIZE,
1016 .setkey = atmel_aes_setkey,
1017 .encrypt = atmel_aes_ofb_encrypt,
1018 .decrypt = atmel_aes_ofb_decrypt,
1019 }
1020},
1021{
1022 .cra_name = "cfb(aes)",
1023 .cra_driver_name = "atmel-cfb-aes",
88efd9a9 1024 .cra_priority = ATMEL_AES_PRIORITY,
bd3c7b5c
NR		 1025 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1026 .cra_blocksize = AES_BLOCK_SIZE,
1027 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
cadc4ab8 1028 .cra_alignmask = 0xf,
bd3c7b5c
NR		 1029 .cra_type = &crypto_ablkcipher_type,
1030 .cra_module = THIS_MODULE,
1031 .cra_init = atmel_aes_cra_init,
1032 .cra_exit = atmel_aes_cra_exit,
1033 .cra_u.ablkcipher = {
1034 .min_keysize = AES_MIN_KEY_SIZE,
1035 .max_keysize = AES_MAX_KEY_SIZE,
1036 .ivsize = AES_BLOCK_SIZE,
1037 .setkey = atmel_aes_setkey,
1038 .encrypt = atmel_aes_cfb_encrypt,
1039 .decrypt = atmel_aes_cfb_decrypt,
1040 }
1041},
1042{
1043 .cra_name = "cfb32(aes)",
1044 .cra_driver_name = "atmel-cfb32-aes",
88efd9a9 1045 .cra_priority = ATMEL_AES_PRIORITY,
bd3c7b5c
NR		 1046 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1047 .cra_blocksize = CFB32_BLOCK_SIZE,
1048 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
cadc4ab8 1049 .cra_alignmask = 0x3,
bd3c7b5c
NR		 1050 .cra_type = &crypto_ablkcipher_type,
1051 .cra_module = THIS_MODULE,
1052 .cra_init = atmel_aes_cra_init,
1053 .cra_exit = atmel_aes_cra_exit,
1054 .cra_u.ablkcipher = {
1055 .min_keysize = AES_MIN_KEY_SIZE,
1056 .max_keysize = AES_MAX_KEY_SIZE,
1057 .ivsize = AES_BLOCK_SIZE,
1058 .setkey = atmel_aes_setkey,
1059 .encrypt = atmel_aes_cfb32_encrypt,
1060 .decrypt = atmel_aes_cfb32_decrypt,
1061 }
1062},
1063{
1064 .cra_name = "cfb16(aes)",
1065 .cra_driver_name = "atmel-cfb16-aes",
88efd9a9 1066 .cra_priority = ATMEL_AES_PRIORITY,
bd3c7b5c
NR		 1067 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1068 .cra_blocksize = CFB16_BLOCK_SIZE,
1069 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
cadc4ab8 1070 .cra_alignmask = 0x1,
bd3c7b5c
NR		 1071 .cra_type = &crypto_ablkcipher_type,
1072 .cra_module = THIS_MODULE,
1073 .cra_init = atmel_aes_cra_init,
1074 .cra_exit = atmel_aes_cra_exit,
1075 .cra_u.ablkcipher = {
1076 .min_keysize = AES_MIN_KEY_SIZE,
1077 .max_keysize = AES_MAX_KEY_SIZE,
1078 .ivsize = AES_BLOCK_SIZE,
1079 .setkey = atmel_aes_setkey,
1080 .encrypt = atmel_aes_cfb16_encrypt,
1081 .decrypt = atmel_aes_cfb16_decrypt,
1082 }
1083},
1084{
1085 .cra_name = "cfb8(aes)",
1086 .cra_driver_name = "atmel-cfb8-aes",
88efd9a9 1087 .cra_priority = ATMEL_AES_PRIORITY,
bd3c7b5c 1088 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
e5d8c961 1089 .cra_blocksize = CFB8_BLOCK_SIZE,
bd3c7b5c
NR		 1090 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1091 .cra_alignmask = 0x0,
1092 .cra_type = &crypto_ablkcipher_type,
1093 .cra_module = THIS_MODULE,
1094 .cra_init = atmel_aes_cra_init,
1095 .cra_exit = atmel_aes_cra_exit,
1096 .cra_u.ablkcipher = {
1097 .min_keysize = AES_MIN_KEY_SIZE,
1098 .max_keysize = AES_MAX_KEY_SIZE,
1099 .ivsize = AES_BLOCK_SIZE,
1100 .setkey = atmel_aes_setkey,
1101 .encrypt = atmel_aes_cfb8_encrypt,
1102 .decrypt = atmel_aes_cfb8_decrypt,
1103 }
1104},
1105{
1106 .cra_name = "ctr(aes)",
1107 .cra_driver_name = "atmel-ctr-aes",
88efd9a9 1108 .cra_priority = ATMEL_AES_PRIORITY,
bd3c7b5c
NR		 1109 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1110 .cra_blocksize = AES_BLOCK_SIZE,
1111 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
cadc4ab8 1112 .cra_alignmask = 0xf,
bd3c7b5c
NR		 1113 .cra_type = &crypto_ablkcipher_type,
1114 .cra_module = THIS_MODULE,
1115 .cra_init = atmel_aes_cra_init,
1116 .cra_exit = atmel_aes_cra_exit,
1117 .cra_u.ablkcipher = {
1118 .min_keysize = AES_MIN_KEY_SIZE,
1119 .max_keysize = AES_MAX_KEY_SIZE,
1120 .ivsize = AES_BLOCK_SIZE,
1121 .setkey = atmel_aes_setkey,
1122 .encrypt = atmel_aes_ctr_encrypt,
1123 .decrypt = atmel_aes_ctr_decrypt,
1124 }
1125},
1126};
1127
cadc4ab8 1128static struct crypto_alg aes_cfb64_alg = {
bd3c7b5c
NR		 1129 .cra_name = "cfb64(aes)",
1130 .cra_driver_name = "atmel-cfb64-aes",
88efd9a9 1131 .cra_priority = ATMEL_AES_PRIORITY,
bd3c7b5c
NR		 1132 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1133 .cra_blocksize = CFB64_BLOCK_SIZE,
1134 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
cadc4ab8 1135 .cra_alignmask = 0x7,
bd3c7b5c
NR		 1136 .cra_type = &crypto_ablkcipher_type,
1137 .cra_module = THIS_MODULE,
1138 .cra_init = atmel_aes_cra_init,
1139 .cra_exit = atmel_aes_cra_exit,
1140 .cra_u.ablkcipher = {
1141 .min_keysize = AES_MIN_KEY_SIZE,
1142 .max_keysize = AES_MAX_KEY_SIZE,
1143 .ivsize = AES_BLOCK_SIZE,
1144 .setkey = atmel_aes_setkey,
1145 .encrypt = atmel_aes_cfb64_encrypt,
1146 .decrypt = atmel_aes_cfb64_decrypt,
1147 }
bd3c7b5c
NR		 1148};
1149
1150static void atmel_aes_queue_task(unsigned long data)
1151{
1152 struct atmel_aes_dev *dd = (struct atmel_aes_dev *)data;
1153
1154 atmel_aes_handle_queue(dd, NULL);
1155}
1156
1157static void atmel_aes_done_task(unsigned long data)
1158{
1159 struct atmel_aes_dev *dd = (struct atmel_aes_dev *) data;
1160 int err;
1161
1162 if (!(dd->flags & AES_FLAGS_DMA)) {
1163 atmel_aes_read_n(dd, AES_ODATAR(0), (u32 *) dd->buf_out,
1164 dd->bufcnt >> 2);
1165
1166 if (sg_copy_from_buffer(dd->out_sg, dd->nb_out_sg,
1167 dd->buf_out, dd->bufcnt))
1168 err = 0;
1169 else
1170 err = -EINVAL;
1171
1172 goto cpu_end;
1173 }
1174
1175 err = atmel_aes_crypt_dma_stop(dd);
1176
1177 err = dd->err ? : err;
1178
1179 if (dd->total && !err) {
cadc4ab8
NR		 1180 if (dd->flags & AES_FLAGS_FAST) {
1181 dd->in_sg = sg_next(dd->in_sg);
1182 dd->out_sg = sg_next(dd->out_sg);
1183 if (!dd->in_sg || !dd->out_sg)
1184 err = -EINVAL;
1185 }
1186 if (!err)
1187 err = atmel_aes_crypt_dma_start(dd);
bd3c7b5c
NR		 1188 if (!err)
1189 return; /* DMA started. Not fininishing. */
1190 }
1191
1192cpu_end:
1193 atmel_aes_finish_req(dd, err);
1194 atmel_aes_handle_queue(dd, NULL);
1195}
1196
1197static irqreturn_t atmel_aes_irq(int irq, void *dev_id)
1198{
1199 struct atmel_aes_dev *aes_dd = dev_id;
1200 u32 reg;
1201
1202 reg = atmel_aes_read(aes_dd, AES_ISR);
1203 if (reg & atmel_aes_read(aes_dd, AES_IMR)) {
1204 atmel_aes_write(aes_dd, AES_IDR, reg);
1205 if (AES_FLAGS_BUSY & aes_dd->flags)
1206 tasklet_schedule(&aes_dd->done_task);
1207 else
1208 dev_warn(aes_dd->dev, "AES interrupt when no active requests.\n");
1209 return IRQ_HANDLED;
1210 }
1211
1212 return IRQ_NONE;
1213}
1214
1215static void atmel_aes_unregister_algs(struct atmel_aes_dev *dd)
1216{
1217 int i;
1218
cadc4ab8
NR		 1219 if (dd->caps.has_cfb64)
1220 crypto_unregister_alg(&aes_cfb64_alg);
924a8bc7
CP		 1221
1222 for (i = 0; i < ARRAY_SIZE(aes_algs); i++)
1223 crypto_unregister_alg(&aes_algs[i]);
bd3c7b5c
NR		 1224}
1225
1226static int atmel_aes_register_algs(struct atmel_aes_dev *dd)
1227{
1228 int err, i, j;
1229
1230 for (i = 0; i < ARRAY_SIZE(aes_algs); i++) {
bd3c7b5c
NR		 1231 err = crypto_register_alg(&aes_algs[i]);
1232 if (err)
1233 goto err_aes_algs;
1234 }
1235
cadc4ab8
NR		 1236 if (dd->caps.has_cfb64) {
1237 err = crypto_register_alg(&aes_cfb64_alg);
bd3c7b5c
NR		 1238 if (err)
1239 goto err_aes_cfb64_alg;
1240 }
1241
1242 return 0;
1243
1244err_aes_cfb64_alg:
1245 i = ARRAY_SIZE(aes_algs);
1246err_aes_algs:
1247 for (j = 0; j < i; j++)
1248 crypto_unregister_alg(&aes_algs[j]);
1249
1250 return err;
1251}
1252
cadc4ab8
NR		 1253static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
1254{
1255 dd->caps.has_dualbuff = 0;
1256 dd->caps.has_cfb64 = 0;
1257 dd->caps.max_burst_size = 1;
1258
1259 /* keep only major version number */
1260 switch (dd->hw_version & 0xff0) {
973e209d
LZ		 1261 case 0x500:
1262 dd->caps.has_dualbuff = 1;
1263 dd->caps.has_cfb64 = 1;
1264 dd->caps.max_burst_size = 4;
1265 break;
cf1f0d12
LZ		 1266 case 0x200:
1267 dd->caps.has_dualbuff = 1;
1268 dd->caps.has_cfb64 = 1;
1269 dd->caps.max_burst_size = 4;
1270 break;
cadc4ab8
NR		 1271 case 0x130:
1272 dd->caps.has_dualbuff = 1;
1273 dd->caps.has_cfb64 = 1;
1274 dd->caps.max_burst_size = 4;
1275 break;
1276 case 0x120:
1277 break;
1278 default:
1279 dev_warn(dd->dev,
1280 "Unmanaged aes version, set minimum capabilities\n");
1281 break;
1282 }
1283}
1284
be943c7d
NF		 1285#if defined(CONFIG_OF)
1286static const struct of_device_id atmel_aes_dt_ids[] = {
1287 { .compatible = "atmel,at91sam9g46-aes" },
1288 { /* sentinel */ }
1289};
1290MODULE_DEVICE_TABLE(of, atmel_aes_dt_ids);
1291
1292static struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev)
1293{
1294 struct device_node *np = pdev->dev.of_node;
1295 struct crypto_platform_data *pdata;
1296
1297 if (!np) {
1298 dev_err(&pdev->dev, "device node not found\n");
1299 return ERR_PTR(-EINVAL);
1300 }
1301
1302 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1303 if (!pdata) {
1304 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
1305 return ERR_PTR(-ENOMEM);
1306 }
1307
1308 pdata->dma_slave = devm_kzalloc(&pdev->dev,
1309 sizeof(*(pdata->dma_slave)),
1310 GFP_KERNEL);
1311 if (!pdata->dma_slave) {
1312 dev_err(&pdev->dev, "could not allocate memory for dma_slave\n");
1313 devm_kfree(&pdev->dev, pdata);
1314 return ERR_PTR(-ENOMEM);
1315 }
1316
1317 return pdata;
1318}
1319#else
1320static inline struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev)
1321{
1322 return ERR_PTR(-EINVAL);
1323}
1324#endif
1325
49cfe4db 1326static int atmel_aes_probe(struct platform_device *pdev)
bd3c7b5c
NR		 1327{
1328 struct atmel_aes_dev *aes_dd;
cadc4ab8 1329 struct crypto_platform_data *pdata;
bd3c7b5c
NR		 1330 struct device *dev = &pdev->dev;
1331 struct resource *aes_res;
bd3c7b5c
NR		 1332 int err;
1333
1334 pdata = pdev->dev.platform_data;
1335 if (!pdata) {
be943c7d
NF		 1336 pdata = atmel_aes_of_init(pdev);
1337 if (IS_ERR(pdata)) {
1338 err = PTR_ERR(pdata);
1339 goto aes_dd_err;
1340 }
1341 }
1342
1343 if (!pdata->dma_slave) {
bd3c7b5c
NR		 1344 err = -ENXIO;
1345 goto aes_dd_err;
1346 }
1347
b0e8b341 1348 aes_dd = devm_kzalloc(&pdev->dev, sizeof(*aes_dd), GFP_KERNEL);
bd3c7b5c
NR		 1349 if (aes_dd == NULL) {
1350 dev_err(dev, "unable to alloc data struct.\n");
1351 err = -ENOMEM;
1352 goto aes_dd_err;
1353 }
1354
1355 aes_dd->dev = dev;
1356
1357 platform_set_drvdata(pdev, aes_dd);
1358
1359 INIT_LIST_HEAD(&aes_dd->list);
8a10eb8d 1360 spin_lock_init(&aes_dd->lock);
bd3c7b5c
NR		 1361
1362 tasklet_init(&aes_dd->done_task, atmel_aes_done_task,
1363 (unsigned long)aes_dd);
1364 tasklet_init(&aes_dd->queue_task, atmel_aes_queue_task,
1365 (unsigned long)aes_dd);
1366
1367 crypto_init_queue(&aes_dd->queue, ATMEL_AES_QUEUE_LENGTH);
1368
1369 aes_dd->irq = -1;
1370
1371 /* Get the base address */
1372 aes_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1373 if (!aes_res) {
1374 dev_err(dev, "no MEM resource info\n");
1375 err = -ENODEV;
1376 goto res_err;
1377 }
1378 aes_dd->phys_base = aes_res->start;
bd3c7b5c
NR		 1379
1380 /* Get the IRQ */
1381 aes_dd->irq = platform_get_irq(pdev, 0);
1382 if (aes_dd->irq < 0) {
1383 dev_err(dev, "no IRQ resource info\n");
1384 err = aes_dd->irq;
b0e8b341 1385 goto res_err;
bd3c7b5c
NR		 1386 }
1387
b0e8b341
LC		 1388 err = devm_request_irq(&pdev->dev, aes_dd->irq, atmel_aes_irq,
1389 IRQF_SHARED, "atmel-aes", aes_dd);
bd3c7b5c
NR		 1390 if (err) {
1391 dev_err(dev, "unable to request aes irq.\n");
b0e8b341 1392 goto res_err;
bd3c7b5c
NR		 1393 }
1394
1395 /* Initializing the clock */
b0e8b341 1396 aes_dd->iclk = devm_clk_get(&pdev->dev, "aes_clk");
bd3c7b5c 1397 if (IS_ERR(aes_dd->iclk)) {
be208356 1398 dev_err(dev, "clock initialization failed.\n");
bd3c7b5c 1399 err = PTR_ERR(aes_dd->iclk);
b0e8b341 1400 goto res_err;
bd3c7b5c
NR		 1401 }
1402
b0e8b341 1403 aes_dd->io_base = devm_ioremap_resource(&pdev->dev, aes_res);
bd3c7b5c
NR		 1404 if (!aes_dd->io_base) {
1405 dev_err(dev, "can't ioremap\n");
1406 err = -ENOMEM;
b0e8b341 1407 goto res_err;
bd3c7b5c
NR		 1408 }
1409
cadc4ab8
NR		 1410 atmel_aes_hw_version_init(aes_dd);
1411
1412 atmel_aes_get_cap(aes_dd);
1413
1414 err = atmel_aes_buff_init(aes_dd);
1415 if (err)
1416 goto err_aes_buff;
1417
1418 err = atmel_aes_dma_init(aes_dd, pdata);
bd3c7b5c
NR		 1419 if (err)
1420 goto err_aes_dma;
1421
1422 spin_lock(&atmel_aes.lock);
1423 list_add_tail(&aes_dd->list, &atmel_aes.dev_list);
1424 spin_unlock(&atmel_aes.lock);
1425
1426 err = atmel_aes_register_algs(aes_dd);
1427 if (err)
1428 goto err_algs;
1429
be943c7d
NF		 1430 dev_info(dev, "Atmel AES - Using %s, %s for DMA transfers\n",
1431 dma_chan_name(aes_dd->dma_lch_in.chan),
1432 dma_chan_name(aes_dd->dma_lch_out.chan));
bd3c7b5c
NR		 1433
1434 return 0;
1435
1436err_algs:
1437 spin_lock(&atmel_aes.lock);
1438 list_del(&aes_dd->list);
1439 spin_unlock(&atmel_aes.lock);
1440 atmel_aes_dma_cleanup(aes_dd);
1441err_aes_dma:
cadc4ab8
NR		 1442 atmel_aes_buff_cleanup(aes_dd);
1443err_aes_buff:
bd3c7b5c
NR		 1444res_err:
1445 tasklet_kill(&aes_dd->done_task);
1446 tasklet_kill(&aes_dd->queue_task);
bd3c7b5c
NR		 1447aes_dd_err:
1448 dev_err(dev, "initialization failed.\n");
1449
1450 return err;
1451}
1452
49cfe4db 1453static int atmel_aes_remove(struct platform_device *pdev)
bd3c7b5c
NR		 1454{
1455 static struct atmel_aes_dev *aes_dd;
1456
1457 aes_dd = platform_get_drvdata(pdev);
1458 if (!aes_dd)
1459 return -ENODEV;
1460 spin_lock(&atmel_aes.lock);
1461 list_del(&aes_dd->list);
1462 spin_unlock(&atmel_aes.lock);
1463
1464 atmel_aes_unregister_algs(aes_dd);
1465
1466 tasklet_kill(&aes_dd->done_task);
1467 tasklet_kill(&aes_dd->queue_task);
1468
1469 atmel_aes_dma_cleanup(aes_dd);
1470
bd3c7b5c
NR		 1471 return 0;
1472}
1473
1474static struct platform_driver atmel_aes_driver = {
1475 .probe = atmel_aes_probe,
49cfe4db 1476 .remove = atmel_aes_remove,
bd3c7b5c
NR		 1477 .driver = {
1478 .name = "atmel_aes",
be943c7d 1479 .of_match_table = of_match_ptr(atmel_aes_dt_ids),
bd3c7b5c
NR		 1480 },
1481};
1482
1483module_platform_driver(atmel_aes_driver);
1484
1485MODULE_DESCRIPTION("Atmel AES hw acceleration support.");
1486MODULE_LICENSE("GPL v2");
1487MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");
Linux kernel - Deliverables
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