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8e8ec596 KP |
1 | /* |
2 | * CAAM hardware register-level view | |
3 | * | |
4 | * Copyright 2008-2011 Freescale Semiconductor, Inc. | |
5 | */ | |
6 | ||
7 | #ifndef REGS_H | |
8 | #define REGS_H | |
9 | ||
10 | #include <linux/types.h> | |
11 | #include <linux/io.h> | |
12 | ||
13 | /* | |
14 | * Architecture-specific register access methods | |
15 | * | |
16 | * CAAM's bus-addressable registers are 64 bits internally. | |
17 | * They have been wired to be safely accessible on 32-bit | |
18 | * architectures, however. Registers were organized such | |
19 | * that (a) they can be contained in 32 bits, (b) if not, then they | |
20 | * can be treated as two 32-bit entities, or finally (c) if they | |
21 | * must be treated as a single 64-bit value, then this can safely | |
22 | * be done with two 32-bit cycles. | |
23 | * | |
24 | * For 32-bit operations on 64-bit values, CAAM follows the same | |
25 | * 64-bit register access conventions as it's predecessors, in that | |
26 | * writes are "triggered" by a write to the register at the numerically | |
27 | * higher address, thus, a full 64-bit write cycle requires a write | |
28 | * to the lower address, followed by a write to the higher address, | |
29 | * which will latch/execute the write cycle. | |
30 | * | |
31 | * For example, let's assume a SW reset of CAAM through the master | |
32 | * configuration register. | |
33 | * - SWRST is in bit 31 of MCFG. | |
34 | * - MCFG begins at base+0x0000. | |
35 | * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower) | |
36 | * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher) | |
37 | * | |
38 | * (and on Power, the convention is 0-31, 32-63, I know...) | |
39 | * | |
40 | * Assuming a 64-bit write to this MCFG to perform a software reset | |
41 | * would then require a write of 0 to base+0x0000, followed by a | |
42 | * write of 0x80000000 to base+0x0004, which would "execute" the | |
43 | * reset. | |
44 | * | |
45 | * Of course, since MCFG 63-32 is all zero, we could cheat and simply | |
46 | * write 0x8000000 to base+0x0004, and the reset would work fine. | |
47 | * However, since CAAM does contain some write-and-read-intended | |
48 | * 64-bit registers, this code defines 64-bit access methods for | |
49 | * the sake of internal consistency and simplicity, and so that a | |
50 | * clean transition to 64-bit is possible when it becomes necessary. | |
51 | * | |
52 | * There are limitations to this that the developer must recognize. | |
53 | * 32-bit architectures cannot enforce an atomic-64 operation, | |
54 | * Therefore: | |
55 | * | |
56 | * - On writes, since the HW is assumed to latch the cycle on the | |
57 | * write of the higher-numeric-address word, then ordered | |
58 | * writes work OK. | |
59 | * | |
60 | * - For reads, where a register contains a relevant value of more | |
61 | * that 32 bits, the hardware employs logic to latch the other | |
62 | * "half" of the data until read, ensuring an accurate value. | |
63 | * This is of particular relevance when dealing with CAAM's | |
64 | * performance counters. | |
65 | * | |
66 | */ | |
67 | ||
509da8fd VM |
68 | #ifdef CONFIG_ARM |
69 | /* These are common macros for Power, put here for ARM */ | |
70 | #define setbits32(_addr, _v) writel((readl(_addr) | (_v)), (_addr)) | |
71 | #define clrbits32(_addr, _v) writel((readl(_addr) & ~(_v)), (_addr)) | |
72 | ||
73 | #define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a) | |
74 | #define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a)) | |
75 | ||
76 | #define out_le32(a, v) out_arch(l, le32, a, v) | |
77 | #define in_le32(a) in_arch(l, le32, a) | |
78 | ||
79 | #define out_be32(a, v) out_arch(l, be32, a, v) | |
80 | #define in_be32(a) in_arch(l, be32, a) | |
81 | ||
82 | #define clrsetbits(type, addr, clear, set) \ | |
83 | out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) | |
84 | ||
85 | #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) | |
86 | #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) | |
87 | #endif | |
88 | ||
8e8ec596 KP |
89 | #ifdef __BIG_ENDIAN |
90 | #define wr_reg32(reg, data) out_be32(reg, data) | |
91 | #define rd_reg32(reg) in_be32(reg) | |
509da8fd | 92 | #define clrsetbits_32(addr, clear, set) clrsetbits_be32(addr, clear, set) |
8e8ec596 KP |
93 | #ifdef CONFIG_64BIT |
94 | #define wr_reg64(reg, data) out_be64(reg, data) | |
95 | #define rd_reg64(reg) in_be64(reg) | |
96 | #endif | |
97 | #else | |
98 | #ifdef __LITTLE_ENDIAN | |
f829e7a3 | 99 | #define wr_reg32(reg, data) __raw_writel(data, reg) |
8e8ec596 | 100 | #define rd_reg32(reg) __raw_readl(reg) |
509da8fd | 101 | #define clrsetbits_32(addr, clear, set) clrsetbits_le32(addr, clear, set) |
8e8ec596 | 102 | #ifdef CONFIG_64BIT |
f829e7a3 | 103 | #define wr_reg64(reg, data) __raw_writeq(data, reg) |
8e8ec596 KP |
104 | #define rd_reg64(reg) __raw_readq(reg) |
105 | #endif | |
106 | #endif | |
107 | #endif | |
108 | ||
f657f82c ST |
109 | /* |
110 | * The only users of these wr/rd_reg64 functions is the Job Ring (JR). | |
6c3af955 HG |
111 | * The DMA address registers in the JR are handled differently depending on |
112 | * platform: | |
113 | * | |
114 | * 1. All BE CAAM platforms and i.MX platforms (LE CAAM): | |
f657f82c ST |
115 | * |
116 | * base + 0x0000 : most-significant 32 bits | |
117 | * base + 0x0004 : least-significant 32 bits | |
118 | * | |
119 | * The 32-bit version of this core therefore has to write to base + 0x0004 | |
6c3af955 HG |
120 | * to set the 32-bit wide DMA address. |
121 | * | |
122 | * 2. All other LE CAAM platforms (LS1021A etc.) | |
123 | * base + 0x0000 : least-significant 32 bits | |
124 | * base + 0x0004 : most-significant 32 bits | |
f657f82c ST |
125 | */ |
126 | ||
8e8ec596 | 127 | #ifndef CONFIG_64BIT |
6c3af955 HG |
128 | #if !defined(CONFIG_CRYPTO_DEV_FSL_CAAM_LE) || \ |
129 | defined(CONFIG_CRYPTO_DEV_FSL_CAAM_IMX) | |
f657f82c ST |
130 | #define REG64_MS32(reg) ((u32 __iomem *)(reg)) |
131 | #define REG64_LS32(reg) ((u32 __iomem *)(reg) + 1) | |
6c3af955 HG |
132 | #else |
133 | #define REG64_MS32(reg) ((u32 __iomem *)(reg) + 1) | |
134 | #define REG64_LS32(reg) ((u32 __iomem *)(reg)) | |
135 | #endif | |
8e8ec596 | 136 | |
ef94b1d8 RG |
137 | static inline void wr_reg64(u64 __iomem *reg, u64 data) |
138 | { | |
f657f82c ST |
139 | wr_reg32(REG64_MS32(reg), data >> 32); |
140 | wr_reg32(REG64_LS32(reg), data); | |
ef94b1d8 RG |
141 | } |
142 | ||
143 | static inline u64 rd_reg64(u64 __iomem *reg) | |
144 | { | |
f657f82c ST |
145 | return ((u64)rd_reg32(REG64_MS32(reg)) << 32 | |
146 | (u64)rd_reg32(REG64_LS32(reg))); | |
ef94b1d8 RG |
147 | } |
148 | #endif | |
8e8ec596 KP |
149 | |
150 | /* | |
151 | * jr_outentry | |
152 | * Represents each entry in a JobR output ring | |
153 | */ | |
154 | struct jr_outentry { | |
155 | dma_addr_t desc;/* Pointer to completed descriptor */ | |
156 | u32 jrstatus; /* Status for completed descriptor */ | |
157 | } __packed; | |
158 | ||
159 | /* | |
160 | * caam_perfmon - Performance Monitor/Secure Memory Status/ | |
161 | * CAAM Global Status/Component Version IDs | |
162 | * | |
163 | * Spans f00-fff wherever instantiated | |
164 | */ | |
165 | ||
166 | /* Number of DECOs */ | |
eb1139cd RG |
167 | #define CHA_NUM_MS_DECONUM_SHIFT 24 |
168 | #define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT) | |
8e8ec596 | 169 | |
bf83490e VM |
170 | /* |
171 | * CHA version IDs / instantiation bitfields | |
172 | * Defined for use with the cha_id fields in perfmon, but the same shift/mask | |
173 | * selectors can be used to pull out the number of instantiated blocks within | |
174 | * cha_num fields in perfmon because the locations are the same. | |
175 | */ | |
eb1139cd | 176 | #define CHA_ID_LS_AES_SHIFT 0 |
bf83490e VM |
177 | #define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT) |
178 | #define CHA_ID_LS_AES_LP (0x3ull << CHA_ID_LS_AES_SHIFT) | |
179 | #define CHA_ID_LS_AES_HP (0x4ull << CHA_ID_LS_AES_SHIFT) | |
986dfbcf | 180 | |
eb1139cd | 181 | #define CHA_ID_LS_DES_SHIFT 4 |
bf83490e | 182 | #define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT) |
986dfbcf | 183 | |
eb1139cd RG |
184 | #define CHA_ID_LS_ARC4_SHIFT 8 |
185 | #define CHA_ID_LS_ARC4_MASK (0xfull << CHA_ID_LS_ARC4_SHIFT) | |
986dfbcf | 186 | |
eb1139cd RG |
187 | #define CHA_ID_LS_MD_SHIFT 12 |
188 | #define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT) | |
bf83490e VM |
189 | #define CHA_ID_LS_MD_LP256 (0x0ull << CHA_ID_LS_MD_SHIFT) |
190 | #define CHA_ID_LS_MD_LP512 (0x1ull << CHA_ID_LS_MD_SHIFT) | |
191 | #define CHA_ID_LS_MD_HP (0x2ull << CHA_ID_LS_MD_SHIFT) | |
986dfbcf | 192 | |
eb1139cd RG |
193 | #define CHA_ID_LS_RNG_SHIFT 16 |
194 | #define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT) | |
986dfbcf | 195 | |
eb1139cd RG |
196 | #define CHA_ID_LS_SNW8_SHIFT 20 |
197 | #define CHA_ID_LS_SNW8_MASK (0xfull << CHA_ID_LS_SNW8_SHIFT) | |
986dfbcf | 198 | |
eb1139cd RG |
199 | #define CHA_ID_LS_KAS_SHIFT 24 |
200 | #define CHA_ID_LS_KAS_MASK (0xfull << CHA_ID_LS_KAS_SHIFT) | |
986dfbcf | 201 | |
eb1139cd RG |
202 | #define CHA_ID_LS_PK_SHIFT 28 |
203 | #define CHA_ID_LS_PK_MASK (0xfull << CHA_ID_LS_PK_SHIFT) | |
986dfbcf | 204 | |
eb1139cd RG |
205 | #define CHA_ID_MS_CRC_SHIFT 0 |
206 | #define CHA_ID_MS_CRC_MASK (0xfull << CHA_ID_MS_CRC_SHIFT) | |
986dfbcf | 207 | |
eb1139cd RG |
208 | #define CHA_ID_MS_SNW9_SHIFT 4 |
209 | #define CHA_ID_MS_SNW9_MASK (0xfull << CHA_ID_MS_SNW9_SHIFT) | |
986dfbcf | 210 | |
eb1139cd RG |
211 | #define CHA_ID_MS_DECO_SHIFT 24 |
212 | #define CHA_ID_MS_DECO_MASK (0xfull << CHA_ID_MS_DECO_SHIFT) | |
986dfbcf | 213 | |
eb1139cd RG |
214 | #define CHA_ID_MS_JR_SHIFT 28 |
215 | #define CHA_ID_MS_JR_MASK (0xfull << CHA_ID_MS_JR_SHIFT) | |
986dfbcf | 216 | |
82c2f960 AP |
217 | struct sec_vid { |
218 | u16 ip_id; | |
219 | u8 maj_rev; | |
220 | u8 min_rev; | |
221 | }; | |
222 | ||
8e8ec596 KP |
223 | struct caam_perfmon { |
224 | /* Performance Monitor Registers f00-f9f */ | |
225 | u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */ | |
226 | u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */ | |
227 | u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests */ | |
228 | u64 ob_enc_bytes; /* PC_OB_ENCRYPT - Outbound Bytes Encrypted */ | |
229 | u64 ob_prot_bytes; /* PC_OB_PROTECT - Outbound Bytes Protected */ | |
230 | u64 ib_dec_bytes; /* PC_IB_DECRYPT - Inbound Bytes Decrypted */ | |
231 | u64 ib_valid_bytes; /* PC_IB_VALIDATED Inbound Bytes Validated */ | |
232 | u64 rsvd[13]; | |
233 | ||
234 | /* CAAM Hardware Instantiation Parameters fa0-fbf */ | |
eb1139cd RG |
235 | u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/ |
236 | u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/ | |
237 | #define CTPR_MS_QI_SHIFT 25 | |
238 | #define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT) | |
17157c90 RG |
239 | #define CTPR_MS_VIRT_EN_INCL 0x00000001 |
240 | #define CTPR_MS_VIRT_EN_POR 0x00000002 | |
fb4562b2 NNL |
241 | #define CTPR_MS_PG_SZ_MASK 0x10 |
242 | #define CTPR_MS_PG_SZ_SHIFT 4 | |
eb1139cd RG |
243 | u32 comp_parms_ms; /* CTPR - Compile Parameters Register */ |
244 | u32 comp_parms_ls; /* CTPR - Compile Parameters Register */ | |
8e8ec596 KP |
245 | u64 rsvd1[2]; |
246 | ||
247 | /* CAAM Global Status fc0-fdf */ | |
248 | u64 faultaddr; /* FAR - Fault Address */ | |
249 | u32 faultliodn; /* FALR - Fault Address LIODN */ | |
250 | u32 faultdetail; /* FADR - Fault Addr Detail */ | |
251 | u32 rsvd2; | |
252 | u32 status; /* CSTA - CAAM Status */ | |
253 | u64 rsvd3; | |
254 | ||
255 | /* Component Instantiation Parameters fe0-fff */ | |
256 | u32 rtic_id; /* RVID - RTIC Version ID */ | |
257 | u32 ccb_id; /* CCBVID - CCB Version ID */ | |
eb1139cd RG |
258 | u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/ |
259 | u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/ | |
260 | u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */ | |
261 | u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/ | |
262 | u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */ | |
263 | u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */ | |
8e8ec596 KP |
264 | }; |
265 | ||
266 | /* LIODN programming for DMA configuration */ | |
267 | #define MSTRID_LOCK_LIODN 0x80000000 | |
268 | #define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */ | |
269 | ||
270 | #define MSTRID_LIODN_MASK 0x0fff | |
271 | struct masterid { | |
272 | u32 liodn_ms; /* lock and make-trusted control bits */ | |
273 | u32 liodn_ls; /* LIODN for non-sequence and seq access */ | |
274 | }; | |
275 | ||
276 | /* Partition ID for DMA configuration */ | |
277 | struct partid { | |
278 | u32 rsvd1; | |
279 | u32 pidr; /* partition ID, DECO */ | |
280 | }; | |
281 | ||
281922a1 | 282 | /* RNGB test mode (replicated twice in some configurations) */ |
8e8ec596 KP |
283 | /* Padded out to 0x100 */ |
284 | struct rngtst { | |
285 | u32 mode; /* RTSTMODEx - Test mode */ | |
286 | u32 rsvd1[3]; | |
287 | u32 reset; /* RTSTRESETx - Test reset control */ | |
288 | u32 rsvd2[3]; | |
289 | u32 status; /* RTSTSSTATUSx - Test status */ | |
290 | u32 rsvd3; | |
291 | u32 errstat; /* RTSTERRSTATx - Test error status */ | |
292 | u32 rsvd4; | |
293 | u32 errctl; /* RTSTERRCTLx - Test error control */ | |
294 | u32 rsvd5; | |
295 | u32 entropy; /* RTSTENTROPYx - Test entropy */ | |
296 | u32 rsvd6[15]; | |
297 | u32 verifctl; /* RTSTVERIFCTLx - Test verification control */ | |
298 | u32 rsvd7; | |
299 | u32 verifstat; /* RTSTVERIFSTATx - Test verification status */ | |
300 | u32 rsvd8; | |
301 | u32 verifdata; /* RTSTVERIFDx - Test verification data */ | |
302 | u32 rsvd9; | |
303 | u32 xkey; /* RTSTXKEYx - Test XKEY */ | |
304 | u32 rsvd10; | |
305 | u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */ | |
306 | u32 rsvd11; | |
307 | u32 oscct; /* RTSTOSCCTx - Test oscillator counter */ | |
308 | u32 rsvd12; | |
309 | u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */ | |
310 | u32 rsvd13[2]; | |
311 | u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */ | |
312 | u32 rsvd14[15]; | |
313 | }; | |
314 | ||
281922a1 KP |
315 | /* RNG4 TRNG test registers */ |
316 | struct rng4tst { | |
1005bccd | 317 | #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ |
e5ffbfc1 AP |
318 | #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in |
319 | both entropy shifter and | |
320 | statistical checker */ | |
321 | #define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both | |
322 | entropy shifter and | |
323 | statistical checker */ | |
324 | #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in | |
325 | entropy shifter, raw data | |
326 | in statistical checker */ | |
327 | #define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */ | |
281922a1 KP |
328 | u32 rtmctl; /* misc. control register */ |
329 | u32 rtscmisc; /* statistical check misc. register */ | |
330 | u32 rtpkrrng; /* poker range register */ | |
331 | union { | |
332 | u32 rtpkrmax; /* PRGM=1: poker max. limit register */ | |
333 | u32 rtpkrsq; /* PRGM=0: poker square calc. result register */ | |
334 | }; | |
335 | #define RTSDCTL_ENT_DLY_SHIFT 16 | |
336 | #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) | |
eeaa1724 | 337 | #define RTSDCTL_ENT_DLY_MIN 3200 |
84cf4827 | 338 | #define RTSDCTL_ENT_DLY_MAX 12800 |
281922a1 KP |
339 | u32 rtsdctl; /* seed control register */ |
340 | union { | |
341 | u32 rtsblim; /* PRGM=1: sparse bit limit register */ | |
342 | u32 rttotsam; /* PRGM=0: total samples register */ | |
343 | }; | |
344 | u32 rtfrqmin; /* frequency count min. limit register */ | |
b061f3fe | 345 | #define RTFRQMAX_DISABLE (1 << 20) |
281922a1 KP |
346 | union { |
347 | u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */ | |
348 | u32 rtfrqcnt; /* PRGM=0: freq. count register */ | |
349 | }; | |
986dfbcf | 350 | u32 rsvd1[40]; |
1005bccd AP |
351 | #define RDSTA_SKVT 0x80000000 |
352 | #define RDSTA_SKVN 0x40000000 | |
986dfbcf | 353 | #define RDSTA_IF0 0x00000001 |
1005bccd AP |
354 | #define RDSTA_IF1 0x00000002 |
355 | #define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0) | |
986dfbcf RG |
356 | u32 rdsta; |
357 | u32 rsvd2[15]; | |
281922a1 KP |
358 | }; |
359 | ||
8e8ec596 KP |
360 | /* |
361 | * caam_ctrl - basic core configuration | |
362 | * starts base + 0x0000 padded out to 0x1000 | |
363 | */ | |
364 | ||
365 | #define KEK_KEY_SIZE 8 | |
366 | #define TKEK_KEY_SIZE 8 | |
367 | #define TDSK_KEY_SIZE 8 | |
368 | ||
369 | #define DECO_RESET 1 /* Use with DECO reset/availability regs */ | |
370 | #define DECO_RESET_0 (DECO_RESET << 0) | |
371 | #define DECO_RESET_1 (DECO_RESET << 1) | |
372 | #define DECO_RESET_2 (DECO_RESET << 2) | |
373 | #define DECO_RESET_3 (DECO_RESET << 3) | |
374 | #define DECO_RESET_4 (DECO_RESET << 4) | |
375 | ||
376 | struct caam_ctrl { | |
377 | /* Basic Configuration Section 000-01f */ | |
378 | /* Read/Writable */ | |
379 | u32 rsvd1; | |
380 | u32 mcr; /* MCFG Master Config Register */ | |
575c1bd5 VG |
381 | u32 rsvd2; |
382 | u32 scfgr; /* SCFGR, Security Config Register */ | |
8e8ec596 KP |
383 | |
384 | /* Bus Access Configuration Section 010-11f */ | |
385 | /* Read/Writable */ | |
386 | struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */ | |
17157c90 RG |
387 | u32 rsvd3[11]; |
388 | u32 jrstart; /* JRSTART - Job Ring Start Register */ | |
8e8ec596 | 389 | struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */ |
17157c90 RG |
390 | u32 rsvd4[5]; |
391 | u32 deco_rsr; /* DECORSR - Deco Request Source */ | |
392 | u32 rsvd11; | |
8e8ec596 KP |
393 | u32 deco_rq; /* DECORR - DECO Request */ |
394 | struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */ | |
395 | u32 rsvd5[22]; | |
396 | ||
397 | /* DECO Availability/Reset Section 120-3ff */ | |
398 | u32 deco_avail; /* DAR - DECO availability */ | |
399 | u32 deco_reset; /* DRR - DECO reset */ | |
400 | u32 rsvd6[182]; | |
401 | ||
402 | /* Key Encryption/Decryption Configuration 400-5ff */ | |
403 | /* Read/Writable only while in Non-secure mode */ | |
404 | u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */ | |
405 | u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */ | |
406 | u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */ | |
407 | u32 rsvd7[32]; | |
408 | u64 sknonce; /* SKNR - Secure Key Nonce */ | |
409 | u32 rsvd8[70]; | |
410 | ||
411 | /* RNG Test/Verification/Debug Access 600-7ff */ | |
412 | /* (Useful in Test/Debug modes only...) */ | |
281922a1 KP |
413 | union { |
414 | struct rngtst rtst[2]; | |
415 | struct rng4tst r4tst[2]; | |
416 | }; | |
8e8ec596 KP |
417 | |
418 | u32 rsvd9[448]; | |
419 | ||
420 | /* Performance Monitor f00-fff */ | |
421 | struct caam_perfmon perfmon; | |
422 | }; | |
423 | ||
424 | /* | |
425 | * Controller master config register defs | |
426 | */ | |
427 | #define MCFGR_SWRESET 0x80000000 /* software reset */ | |
428 | #define MCFGR_WDENABLE 0x40000000 /* DECO watchdog enable */ | |
429 | #define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */ | |
430 | #define MCFGR_DMA_RESET 0x10000000 | |
431 | #define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */ | |
575c1bd5 | 432 | #define SCFGR_RDBENABLE 0x00000400 |
17157c90 | 433 | #define SCFGR_VIRT_EN 0x00008000 |
997ad290 | 434 | #define DECORR_RQD0ENABLE 0x00000001 /* Enable DECO0 for direct access */ |
17157c90 RG |
435 | #define DECORSR_JR0 0x00000001 /* JR to supply TZ, SDID, ICID */ |
436 | #define DECORSR_VALID 0x80000000 | |
997ad290 | 437 | #define DECORR_DEN0 0x00010000 /* DECO0 available for access*/ |
8e8ec596 KP |
438 | |
439 | /* AXI read cache control */ | |
440 | #define MCFGR_ARCACHE_SHIFT 12 | |
441 | #define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT) | |
f1096749 HG |
442 | #define MCFGR_ARCACHE_BUFF (0x1 << MCFGR_ARCACHE_SHIFT) |
443 | #define MCFGR_ARCACHE_CACH (0x2 << MCFGR_ARCACHE_SHIFT) | |
444 | #define MCFGR_ARCACHE_RALL (0x4 << MCFGR_ARCACHE_SHIFT) | |
8e8ec596 KP |
445 | |
446 | /* AXI write cache control */ | |
447 | #define MCFGR_AWCACHE_SHIFT 8 | |
448 | #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT) | |
f1096749 HG |
449 | #define MCFGR_AWCACHE_BUFF (0x1 << MCFGR_AWCACHE_SHIFT) |
450 | #define MCFGR_AWCACHE_CACH (0x2 << MCFGR_AWCACHE_SHIFT) | |
451 | #define MCFGR_AWCACHE_WALL (0x8 << MCFGR_AWCACHE_SHIFT) | |
8e8ec596 KP |
452 | |
453 | /* AXI pipeline depth */ | |
454 | #define MCFGR_AXIPIPE_SHIFT 4 | |
455 | #define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT) | |
456 | ||
457 | #define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */ | |
458 | #define MCFGR_BURST_64 0x00000001 /* Max burst size */ | |
459 | ||
17157c90 RG |
460 | /* JRSTART register offsets */ |
461 | #define JRSTART_JR0_START 0x00000001 /* Start Job ring 0 */ | |
462 | #define JRSTART_JR1_START 0x00000002 /* Start Job ring 1 */ | |
463 | #define JRSTART_JR2_START 0x00000004 /* Start Job ring 2 */ | |
464 | #define JRSTART_JR3_START 0x00000008 /* Start Job ring 3 */ | |
465 | ||
8e8ec596 KP |
466 | /* |
467 | * caam_job_ring - direct job ring setup | |
468 | * 1-4 possible per instantiation, base + 1000/2000/3000/4000 | |
469 | * Padded out to 0x1000 | |
470 | */ | |
471 | struct caam_job_ring { | |
472 | /* Input ring */ | |
473 | u64 inpring_base; /* IRBAx - Input desc ring baseaddr */ | |
474 | u32 rsvd1; | |
475 | u32 inpring_size; /* IRSx - Input ring size */ | |
476 | u32 rsvd2; | |
477 | u32 inpring_avail; /* IRSAx - Input ring room remaining */ | |
478 | u32 rsvd3; | |
479 | u32 inpring_jobadd; /* IRJAx - Input ring jobs added */ | |
480 | ||
481 | /* Output Ring */ | |
482 | u64 outring_base; /* ORBAx - Output status ring base addr */ | |
483 | u32 rsvd4; | |
484 | u32 outring_size; /* ORSx - Output ring size */ | |
485 | u32 rsvd5; | |
486 | u32 outring_rmvd; /* ORJRx - Output ring jobs removed */ | |
487 | u32 rsvd6; | |
488 | u32 outring_used; /* ORSFx - Output ring slots full */ | |
489 | ||
490 | /* Status/Configuration */ | |
491 | u32 rsvd7; | |
492 | u32 jroutstatus; /* JRSTAx - JobR output status */ | |
493 | u32 rsvd8; | |
494 | u32 jrintstatus; /* JRINTx - JobR interrupt status */ | |
495 | u32 rconfig_hi; /* JRxCFG - Ring configuration */ | |
496 | u32 rconfig_lo; | |
497 | ||
498 | /* Indices. CAAM maintains as "heads" of each queue */ | |
499 | u32 rsvd9; | |
500 | u32 inp_rdidx; /* IRRIx - Input ring read index */ | |
501 | u32 rsvd10; | |
502 | u32 out_wtidx; /* ORWIx - Output ring write index */ | |
503 | ||
504 | /* Command/control */ | |
505 | u32 rsvd11; | |
506 | u32 jrcommand; /* JRCRx - JobR command */ | |
507 | ||
508 | u32 rsvd12[932]; | |
509 | ||
510 | /* Performance Monitor f00-fff */ | |
511 | struct caam_perfmon perfmon; | |
512 | }; | |
513 | ||
514 | #define JR_RINGSIZE_MASK 0x03ff | |
515 | /* | |
516 | * jrstatus - Job Ring Output Status | |
517 | * All values in lo word | |
518 | * Also note, same values written out as status through QI | |
519 | * in the command/status field of a frame descriptor | |
520 | */ | |
521 | #define JRSTA_SSRC_SHIFT 28 | |
522 | #define JRSTA_SSRC_MASK 0xf0000000 | |
523 | ||
524 | #define JRSTA_SSRC_NONE 0x00000000 | |
525 | #define JRSTA_SSRC_CCB_ERROR 0x20000000 | |
526 | #define JRSTA_SSRC_JUMP_HALT_USER 0x30000000 | |
527 | #define JRSTA_SSRC_DECO 0x40000000 | |
528 | #define JRSTA_SSRC_JRERROR 0x60000000 | |
529 | #define JRSTA_SSRC_JUMP_HALT_CC 0x70000000 | |
530 | ||
531 | #define JRSTA_DECOERR_JUMP 0x08000000 | |
532 | #define JRSTA_DECOERR_INDEX_SHIFT 8 | |
533 | #define JRSTA_DECOERR_INDEX_MASK 0xff00 | |
534 | #define JRSTA_DECOERR_ERROR_MASK 0x00ff | |
535 | ||
536 | #define JRSTA_DECOERR_NONE 0x00 | |
537 | #define JRSTA_DECOERR_LINKLEN 0x01 | |
538 | #define JRSTA_DECOERR_LINKPTR 0x02 | |
539 | #define JRSTA_DECOERR_JRCTRL 0x03 | |
540 | #define JRSTA_DECOERR_DESCCMD 0x04 | |
541 | #define JRSTA_DECOERR_ORDER 0x05 | |
542 | #define JRSTA_DECOERR_KEYCMD 0x06 | |
543 | #define JRSTA_DECOERR_LOADCMD 0x07 | |
544 | #define JRSTA_DECOERR_STORECMD 0x08 | |
545 | #define JRSTA_DECOERR_OPCMD 0x09 | |
546 | #define JRSTA_DECOERR_FIFOLDCMD 0x0a | |
547 | #define JRSTA_DECOERR_FIFOSTCMD 0x0b | |
548 | #define JRSTA_DECOERR_MOVECMD 0x0c | |
549 | #define JRSTA_DECOERR_JUMPCMD 0x0d | |
550 | #define JRSTA_DECOERR_MATHCMD 0x0e | |
551 | #define JRSTA_DECOERR_SHASHCMD 0x0f | |
552 | #define JRSTA_DECOERR_SEQCMD 0x10 | |
553 | #define JRSTA_DECOERR_DECOINTERNAL 0x11 | |
554 | #define JRSTA_DECOERR_SHDESCHDR 0x12 | |
555 | #define JRSTA_DECOERR_HDRLEN 0x13 | |
556 | #define JRSTA_DECOERR_BURSTER 0x14 | |
557 | #define JRSTA_DECOERR_DESCSIGNATURE 0x15 | |
558 | #define JRSTA_DECOERR_DMA 0x16 | |
559 | #define JRSTA_DECOERR_BURSTFIFO 0x17 | |
560 | #define JRSTA_DECOERR_JRRESET 0x1a | |
561 | #define JRSTA_DECOERR_JOBFAIL 0x1b | |
562 | #define JRSTA_DECOERR_DNRERR 0x80 | |
563 | #define JRSTA_DECOERR_UNDEFPCL 0x81 | |
564 | #define JRSTA_DECOERR_PDBERR 0x82 | |
565 | #define JRSTA_DECOERR_ANRPLY_LATE 0x83 | |
566 | #define JRSTA_DECOERR_ANRPLY_REPLAY 0x84 | |
567 | #define JRSTA_DECOERR_SEQOVF 0x85 | |
568 | #define JRSTA_DECOERR_INVSIGN 0x86 | |
569 | #define JRSTA_DECOERR_DSASIGN 0x87 | |
570 | ||
571 | #define JRSTA_CCBERR_JUMP 0x08000000 | |
572 | #define JRSTA_CCBERR_INDEX_MASK 0xff00 | |
573 | #define JRSTA_CCBERR_INDEX_SHIFT 8 | |
574 | #define JRSTA_CCBERR_CHAID_MASK 0x00f0 | |
575 | #define JRSTA_CCBERR_CHAID_SHIFT 4 | |
576 | #define JRSTA_CCBERR_ERRID_MASK 0x000f | |
577 | ||
578 | #define JRSTA_CCBERR_CHAID_AES (0x01 << JRSTA_CCBERR_CHAID_SHIFT) | |
579 | #define JRSTA_CCBERR_CHAID_DES (0x02 << JRSTA_CCBERR_CHAID_SHIFT) | |
580 | #define JRSTA_CCBERR_CHAID_ARC4 (0x03 << JRSTA_CCBERR_CHAID_SHIFT) | |
581 | #define JRSTA_CCBERR_CHAID_MD (0x04 << JRSTA_CCBERR_CHAID_SHIFT) | |
582 | #define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT) | |
583 | #define JRSTA_CCBERR_CHAID_SNOW (0x06 << JRSTA_CCBERR_CHAID_SHIFT) | |
584 | #define JRSTA_CCBERR_CHAID_KASUMI (0x07 << JRSTA_CCBERR_CHAID_SHIFT) | |
585 | #define JRSTA_CCBERR_CHAID_PK (0x08 << JRSTA_CCBERR_CHAID_SHIFT) | |
586 | #define JRSTA_CCBERR_CHAID_CRC (0x09 << JRSTA_CCBERR_CHAID_SHIFT) | |
587 | ||
588 | #define JRSTA_CCBERR_ERRID_NONE 0x00 | |
589 | #define JRSTA_CCBERR_ERRID_MODE 0x01 | |
590 | #define JRSTA_CCBERR_ERRID_DATASIZ 0x02 | |
591 | #define JRSTA_CCBERR_ERRID_KEYSIZ 0x03 | |
592 | #define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04 | |
593 | #define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05 | |
594 | #define JRSTA_CCBERR_ERRID_SEQUENCE 0x06 | |
595 | #define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07 | |
596 | #define JRSTA_CCBERR_ERRID_PKMODEVN 0x08 | |
597 | #define JRSTA_CCBERR_ERRID_KEYPARIT 0x09 | |
598 | #define JRSTA_CCBERR_ERRID_ICVCHK 0x0a | |
599 | #define JRSTA_CCBERR_ERRID_HARDWARE 0x0b | |
600 | #define JRSTA_CCBERR_ERRID_CCMAAD 0x0c | |
601 | #define JRSTA_CCBERR_ERRID_INVCHA 0x0f | |
602 | ||
603 | #define JRINT_ERR_INDEX_MASK 0x3fff0000 | |
604 | #define JRINT_ERR_INDEX_SHIFT 16 | |
605 | #define JRINT_ERR_TYPE_MASK 0xf00 | |
606 | #define JRINT_ERR_TYPE_SHIFT 8 | |
607 | #define JRINT_ERR_HALT_MASK 0xc | |
608 | #define JRINT_ERR_HALT_SHIFT 2 | |
609 | #define JRINT_ERR_HALT_INPROGRESS 0x4 | |
610 | #define JRINT_ERR_HALT_COMPLETE 0x8 | |
611 | #define JRINT_JR_ERROR 0x02 | |
612 | #define JRINT_JR_INT 0x01 | |
613 | ||
614 | #define JRINT_ERR_TYPE_WRITE 1 | |
615 | #define JRINT_ERR_TYPE_BAD_INPADDR 3 | |
616 | #define JRINT_ERR_TYPE_BAD_OUTADDR 4 | |
617 | #define JRINT_ERR_TYPE_INV_INPWRT 5 | |
618 | #define JRINT_ERR_TYPE_INV_OUTWRT 6 | |
619 | #define JRINT_ERR_TYPE_RESET 7 | |
620 | #define JRINT_ERR_TYPE_REMOVE_OFL 8 | |
621 | #define JRINT_ERR_TYPE_ADD_OFL 9 | |
622 | ||
623 | #define JRCFG_SOE 0x04 | |
624 | #define JRCFG_ICEN 0x02 | |
625 | #define JRCFG_IMSK 0x01 | |
626 | #define JRCFG_ICDCT_SHIFT 8 | |
627 | #define JRCFG_ICTT_SHIFT 16 | |
628 | ||
629 | #define JRCR_RESET 0x01 | |
630 | ||
631 | /* | |
632 | * caam_assurance - Assurance Controller View | |
633 | * base + 0x6000 padded out to 0x1000 | |
634 | */ | |
635 | ||
636 | struct rtic_element { | |
637 | u64 address; | |
638 | u32 rsvd; | |
639 | u32 length; | |
640 | }; | |
641 | ||
642 | struct rtic_block { | |
643 | struct rtic_element element[2]; | |
644 | }; | |
645 | ||
646 | struct rtic_memhash { | |
647 | u32 memhash_be[32]; | |
648 | u32 memhash_le[32]; | |
649 | }; | |
650 | ||
651 | struct caam_assurance { | |
652 | /* Status/Command/Watchdog */ | |
653 | u32 rsvd1; | |
654 | u32 status; /* RSTA - Status */ | |
655 | u32 rsvd2; | |
656 | u32 cmd; /* RCMD - Command */ | |
657 | u32 rsvd3; | |
658 | u32 ctrl; /* RCTL - Control */ | |
659 | u32 rsvd4; | |
660 | u32 throttle; /* RTHR - Throttle */ | |
661 | u32 rsvd5[2]; | |
662 | u64 watchdog; /* RWDOG - Watchdog Timer */ | |
663 | u32 rsvd6; | |
664 | u32 rend; /* REND - Endian corrections */ | |
665 | u32 rsvd7[50]; | |
666 | ||
667 | /* Block access/configuration @ 100/110/120/130 */ | |
668 | struct rtic_block memblk[4]; /* Memory Blocks A-D */ | |
669 | u32 rsvd8[32]; | |
670 | ||
671 | /* Block hashes @ 200/300/400/500 */ | |
672 | struct rtic_memhash hash[4]; /* Block hash values A-D */ | |
673 | u32 rsvd_3[640]; | |
674 | }; | |
675 | ||
676 | /* | |
677 | * caam_queue_if - QI configuration and control | |
678 | * starts base + 0x7000, padded out to 0x1000 long | |
679 | */ | |
680 | ||
681 | struct caam_queue_if { | |
682 | u32 qi_control_hi; /* QICTL - QI Control */ | |
683 | u32 qi_control_lo; | |
684 | u32 rsvd1; | |
685 | u32 qi_status; /* QISTA - QI Status */ | |
686 | u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */ | |
687 | u32 qi_deq_cfg_lo; | |
688 | u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */ | |
689 | u32 qi_enq_cfg_lo; | |
690 | u32 rsvd2[1016]; | |
691 | }; | |
692 | ||
693 | /* QI control bits - low word */ | |
694 | #define QICTL_DQEN 0x01 /* Enable frame pop */ | |
695 | #define QICTL_STOP 0x02 /* Stop dequeue/enqueue */ | |
696 | #define QICTL_SOE 0x04 /* Stop on error */ | |
697 | ||
698 | /* QI control bits - high word */ | |
699 | #define QICTL_MBSI 0x01 | |
700 | #define QICTL_MHWSI 0x02 | |
701 | #define QICTL_MWSI 0x04 | |
702 | #define QICTL_MDWSI 0x08 | |
703 | #define QICTL_CBSI 0x10 /* CtrlDataByteSwapInput */ | |
704 | #define QICTL_CHWSI 0x20 /* CtrlDataHalfSwapInput */ | |
705 | #define QICTL_CWSI 0x40 /* CtrlDataWordSwapInput */ | |
706 | #define QICTL_CDWSI 0x80 /* CtrlDataDWordSwapInput */ | |
707 | #define QICTL_MBSO 0x0100 | |
708 | #define QICTL_MHWSO 0x0200 | |
709 | #define QICTL_MWSO 0x0400 | |
710 | #define QICTL_MDWSO 0x0800 | |
711 | #define QICTL_CBSO 0x1000 /* CtrlDataByteSwapOutput */ | |
712 | #define QICTL_CHWSO 0x2000 /* CtrlDataHalfSwapOutput */ | |
713 | #define QICTL_CWSO 0x4000 /* CtrlDataWordSwapOutput */ | |
714 | #define QICTL_CDWSO 0x8000 /* CtrlDataDWordSwapOutput */ | |
715 | #define QICTL_DMBS 0x010000 | |
716 | #define QICTL_EPO 0x020000 | |
717 | ||
718 | /* QI status bits */ | |
719 | #define QISTA_PHRDERR 0x01 /* PreHeader Read Error */ | |
720 | #define QISTA_CFRDERR 0x02 /* Compound Frame Read Error */ | |
721 | #define QISTA_OFWRERR 0x04 /* Output Frame Read Error */ | |
722 | #define QISTA_BPDERR 0x08 /* Buffer Pool Depleted */ | |
723 | #define QISTA_BTSERR 0x10 /* Buffer Undersize */ | |
724 | #define QISTA_CFWRERR 0x20 /* Compound Frame Write Err */ | |
725 | #define QISTA_STOPD 0x80000000 /* QI Stopped (see QICTL) */ | |
726 | ||
727 | /* deco_sg_table - DECO view of scatter/gather table */ | |
728 | struct deco_sg_table { | |
729 | u64 addr; /* Segment Address */ | |
730 | u32 elen; /* E, F bits + 30-bit length */ | |
731 | u32 bpid_offset; /* Buffer Pool ID + 16-bit length */ | |
732 | }; | |
733 | ||
734 | /* | |
735 | * caam_deco - descriptor controller - CHA cluster block | |
736 | * | |
737 | * Only accessible when direct DECO access is turned on | |
738 | * (done in DECORR, via MID programmed in DECOxMID | |
739 | * | |
740 | * 5 typical, base + 0x8000/9000/a000/b000 | |
741 | * Padded out to 0x1000 long | |
742 | */ | |
743 | struct caam_deco { | |
744 | u32 rsvd1; | |
745 | u32 cls1_mode; /* CxC1MR - Class 1 Mode */ | |
746 | u32 rsvd2; | |
747 | u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */ | |
748 | u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */ | |
749 | u32 cls1_datasize_lo; | |
750 | u32 rsvd3; | |
751 | u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */ | |
752 | u32 rsvd4[5]; | |
753 | u32 cha_ctrl; /* CCTLR - CHA control */ | |
754 | u32 rsvd5; | |
755 | u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */ | |
756 | u32 rsvd6; | |
757 | u32 clr_written; /* CxCWR - Clear-Written */ | |
758 | u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */ | |
759 | u32 ccb_status_lo; | |
760 | u32 rsvd7[3]; | |
761 | u32 aad_size; /* CxAADSZR - Current AAD Size */ | |
762 | u32 rsvd8; | |
763 | u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */ | |
764 | u32 rsvd9[7]; | |
765 | u32 pkha_a_size; /* PKASZRx - Size of PKHA A */ | |
766 | u32 rsvd10; | |
767 | u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */ | |
768 | u32 rsvd11; | |
769 | u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */ | |
770 | u32 rsvd12; | |
771 | u32 pkha_e_size; /* PKESZRx - Size of PKHA E */ | |
772 | u32 rsvd13[24]; | |
773 | u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */ | |
774 | u32 rsvd14[48]; | |
775 | u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */ | |
776 | u32 rsvd15[121]; | |
777 | u32 cls2_mode; /* CxC2MR - Class 2 Mode */ | |
778 | u32 rsvd16; | |
779 | u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */ | |
780 | u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */ | |
781 | u32 cls2_datasize_lo; | |
782 | u32 rsvd17; | |
783 | u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */ | |
784 | u32 rsvd18[56]; | |
785 | u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */ | |
786 | u32 rsvd19[46]; | |
787 | u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */ | |
788 | u32 rsvd20[84]; | |
789 | u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */ | |
790 | u32 inp_infofifo_lo; | |
791 | u32 rsvd21[2]; | |
792 | u64 inp_datafifo; /* CxDFIFO - Input Data FIFO */ | |
793 | u32 rsvd22[2]; | |
794 | u64 out_datafifo; /* CxOFIFO - Output Data FIFO */ | |
795 | u32 rsvd23[2]; | |
796 | u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */ | |
797 | u32 jr_ctl_lo; | |
798 | u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */ | |
1005bccd | 799 | #define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF |
8e8ec596 KP |
800 | u32 op_status_hi; /* DxOPSTA - DECO Operation Status */ |
801 | u32 op_status_lo; | |
802 | u32 rsvd24[2]; | |
803 | u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */ | |
804 | u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */ | |
805 | u32 rsvd26[6]; | |
806 | u64 math[4]; /* DxMTH - Math register */ | |
807 | u32 rsvd27[8]; | |
808 | struct deco_sg_table gthr_tbl[4]; /* DxGTR - Gather Tables */ | |
809 | u32 rsvd28[16]; | |
810 | struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */ | |
811 | u32 rsvd29[48]; | |
812 | u32 descbuf[64]; /* DxDESB - Descriptor buffer */ | |
997ad290 | 813 | u32 rscvd30[193]; |
84cf4827 AP |
814 | #define DESC_DBG_DECO_STAT_HOST_ERR 0x00D00000 |
815 | #define DESC_DBG_DECO_STAT_VALID 0x80000000 | |
816 | #define DESC_DBG_DECO_STAT_MASK 0x00F00000 | |
997ad290 RG |
817 | u32 desc_dbg; /* DxDDR - DECO Debug Register */ |
818 | u32 rsvd31[126]; | |
8e8ec596 KP |
819 | }; |
820 | ||
997ad290 RG |
821 | #define DECO_JQCR_WHL 0x20000000 |
822 | #define DECO_JQCR_FOUR 0x10000000 | |
823 | ||
fb4562b2 NNL |
824 | #define JR_BLOCK_NUMBER 1 |
825 | #define ASSURE_BLOCK_NUMBER 6 | |
826 | #define QI_BLOCK_NUMBER 7 | |
827 | #define DECO_BLOCK_NUMBER 8 | |
828 | #define PG_SIZE_4K 0x1000 | |
829 | #define PG_SIZE_64K 0x10000 | |
8e8ec596 | 830 | #endif /* REGS_H */ |