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db509a45 BB |
1 | /* |
2 | * Provide TDMA helper functions used by cipher and hash algorithm | |
3 | * implementations. | |
4 | * | |
5 | * Author: Boris Brezillon <boris.brezillon@free-electrons.com> | |
6 | * Author: Arnaud Ebalard <arno@natisbad.org> | |
7 | * | |
8 | * This work is based on an initial version written by | |
9 | * Sebastian Andrzej Siewior < sebastian at breakpoint dot cc > | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License version 2 as published | |
13 | * by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include "cesa.h" | |
17 | ||
18 | bool mv_cesa_req_dma_iter_next_transfer(struct mv_cesa_dma_iter *iter, | |
19 | struct mv_cesa_sg_dma_iter *sgiter, | |
20 | unsigned int len) | |
21 | { | |
22 | if (!sgiter->sg) | |
23 | return false; | |
24 | ||
25 | sgiter->op_offset += len; | |
26 | sgiter->offset += len; | |
27 | if (sgiter->offset == sg_dma_len(sgiter->sg)) { | |
28 | if (sg_is_last(sgiter->sg)) | |
29 | return false; | |
30 | sgiter->offset = 0; | |
31 | sgiter->sg = sg_next(sgiter->sg); | |
32 | } | |
33 | ||
34 | if (sgiter->op_offset == iter->op_len) | |
35 | return false; | |
36 | ||
37 | return true; | |
38 | } | |
39 | ||
40 | void mv_cesa_dma_step(struct mv_cesa_tdma_req *dreq) | |
41 | { | |
42 | struct mv_cesa_engine *engine = dreq->base.engine; | |
43 | ||
b1508561 | 44 | writel_relaxed(0, engine->regs + CESA_SA_CFG); |
db509a45 BB |
45 | |
46 | mv_cesa_set_int_mask(engine, CESA_SA_INT_ACC0_IDMA_DONE); | |
b1508561 RK |
47 | writel_relaxed(CESA_TDMA_DST_BURST_128B | CESA_TDMA_SRC_BURST_128B | |
48 | CESA_TDMA_NO_BYTE_SWAP | CESA_TDMA_EN, | |
49 | engine->regs + CESA_TDMA_CONTROL); | |
50 | ||
51 | writel_relaxed(CESA_SA_CFG_ACT_CH0_IDMA | CESA_SA_CFG_MULTI_PKT | | |
52 | CESA_SA_CFG_CH0_W_IDMA | CESA_SA_CFG_PARA_DIS, | |
53 | engine->regs + CESA_SA_CFG); | |
54 | writel_relaxed(dreq->chain.first->cur_dma, | |
55 | engine->regs + CESA_TDMA_NEXT_ADDR); | |
db509a45 BB |
56 | writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD); |
57 | } | |
58 | ||
59 | void mv_cesa_dma_cleanup(struct mv_cesa_tdma_req *dreq) | |
60 | { | |
61 | struct mv_cesa_tdma_desc *tdma; | |
62 | ||
63 | for (tdma = dreq->chain.first; tdma;) { | |
64 | struct mv_cesa_tdma_desc *old_tdma = tdma; | |
65 | ||
66 | if (tdma->flags & CESA_TDMA_OP) | |
67 | dma_pool_free(cesa_dev->dma->op_pool, tdma->op, | |
68 | le32_to_cpu(tdma->src)); | |
69 | ||
70 | tdma = tdma->next; | |
71 | dma_pool_free(cesa_dev->dma->tdma_desc_pool, old_tdma, | |
5d754137 | 72 | old_tdma->cur_dma); |
db509a45 BB |
73 | } |
74 | ||
75 | dreq->chain.first = NULL; | |
76 | dreq->chain.last = NULL; | |
77 | } | |
78 | ||
79 | void mv_cesa_dma_prepare(struct mv_cesa_tdma_req *dreq, | |
80 | struct mv_cesa_engine *engine) | |
81 | { | |
82 | struct mv_cesa_tdma_desc *tdma; | |
83 | ||
84 | for (tdma = dreq->chain.first; tdma; tdma = tdma->next) { | |
85 | if (tdma->flags & CESA_TDMA_DST_IN_SRAM) | |
86 | tdma->dst = cpu_to_le32(tdma->dst + engine->sram_dma); | |
87 | ||
88 | if (tdma->flags & CESA_TDMA_SRC_IN_SRAM) | |
89 | tdma->src = cpu_to_le32(tdma->src + engine->sram_dma); | |
90 | ||
91 | if (tdma->flags & CESA_TDMA_OP) | |
92 | mv_cesa_adjust_op(engine, tdma->op); | |
93 | } | |
94 | } | |
95 | ||
96 | static struct mv_cesa_tdma_desc * | |
97 | mv_cesa_dma_add_desc(struct mv_cesa_tdma_chain *chain, gfp_t flags) | |
98 | { | |
99 | struct mv_cesa_tdma_desc *new_tdma = NULL; | |
100 | dma_addr_t dma_handle; | |
101 | ||
472d640b JL |
102 | new_tdma = dma_pool_zalloc(cesa_dev->dma->tdma_desc_pool, flags, |
103 | &dma_handle); | |
db509a45 BB |
104 | if (!new_tdma) |
105 | return ERR_PTR(-ENOMEM); | |
106 | ||
5d754137 | 107 | new_tdma->cur_dma = dma_handle; |
db509a45 | 108 | if (chain->last) { |
5d754137 | 109 | chain->last->next_dma = cpu_to_le32(dma_handle); |
db509a45 BB |
110 | chain->last->next = new_tdma; |
111 | } else { | |
112 | chain->first = new_tdma; | |
113 | } | |
114 | ||
115 | chain->last = new_tdma; | |
116 | ||
117 | return new_tdma; | |
118 | } | |
119 | ||
120 | struct mv_cesa_op_ctx *mv_cesa_dma_add_op(struct mv_cesa_tdma_chain *chain, | |
121 | const struct mv_cesa_op_ctx *op_templ, | |
122 | bool skip_ctx, | |
123 | gfp_t flags) | |
124 | { | |
125 | struct mv_cesa_tdma_desc *tdma; | |
126 | struct mv_cesa_op_ctx *op; | |
127 | dma_addr_t dma_handle; | |
6de59d45 | 128 | unsigned int size; |
db509a45 BB |
129 | |
130 | tdma = mv_cesa_dma_add_desc(chain, flags); | |
131 | if (IS_ERR(tdma)) | |
132 | return ERR_CAST(tdma); | |
133 | ||
134 | op = dma_pool_alloc(cesa_dev->dma->op_pool, flags, &dma_handle); | |
135 | if (!op) | |
136 | return ERR_PTR(-ENOMEM); | |
137 | ||
138 | *op = *op_templ; | |
139 | ||
6de59d45 RK |
140 | size = skip_ctx ? sizeof(op->desc) : sizeof(*op); |
141 | ||
db509a45 BB |
142 | tdma = chain->last; |
143 | tdma->op = op; | |
6de59d45 | 144 | tdma->byte_cnt = cpu_to_le32(size | BIT(31)); |
ea1f662b | 145 | tdma->src = cpu_to_le32(dma_handle); |
db509a45 BB |
146 | tdma->flags = CESA_TDMA_DST_IN_SRAM | CESA_TDMA_OP; |
147 | ||
148 | return op; | |
149 | } | |
150 | ||
151 | int mv_cesa_dma_add_data_transfer(struct mv_cesa_tdma_chain *chain, | |
152 | dma_addr_t dst, dma_addr_t src, u32 size, | |
153 | u32 flags, gfp_t gfp_flags) | |
154 | { | |
155 | struct mv_cesa_tdma_desc *tdma; | |
156 | ||
157 | tdma = mv_cesa_dma_add_desc(chain, gfp_flags); | |
158 | if (IS_ERR(tdma)) | |
159 | return PTR_ERR(tdma); | |
160 | ||
6de59d45 | 161 | tdma->byte_cnt = cpu_to_le32(size | BIT(31)); |
db509a45 BB |
162 | tdma->src = src; |
163 | tdma->dst = dst; | |
164 | ||
165 | flags &= (CESA_TDMA_DST_IN_SRAM | CESA_TDMA_SRC_IN_SRAM); | |
166 | tdma->flags = flags | CESA_TDMA_DATA; | |
167 | ||
168 | return 0; | |
169 | } | |
170 | ||
35622eae | 171 | int mv_cesa_dma_add_dummy_launch(struct mv_cesa_tdma_chain *chain, gfp_t flags) |
db509a45 BB |
172 | { |
173 | struct mv_cesa_tdma_desc *tdma; | |
174 | ||
175 | tdma = mv_cesa_dma_add_desc(chain, flags); | |
176 | if (IS_ERR(tdma)) | |
177 | return PTR_ERR(tdma); | |
178 | ||
179 | return 0; | |
180 | } | |
181 | ||
35622eae | 182 | int mv_cesa_dma_add_dummy_end(struct mv_cesa_tdma_chain *chain, gfp_t flags) |
db509a45 BB |
183 | { |
184 | struct mv_cesa_tdma_desc *tdma; | |
185 | ||
186 | tdma = mv_cesa_dma_add_desc(chain, flags); | |
187 | if (IS_ERR(tdma)) | |
188 | return PTR_ERR(tdma); | |
189 | ||
6de59d45 | 190 | tdma->byte_cnt = cpu_to_le32(BIT(31)); |
db509a45 BB |
191 | |
192 | return 0; | |
193 | } | |
194 | ||
195 | int mv_cesa_dma_add_op_transfers(struct mv_cesa_tdma_chain *chain, | |
196 | struct mv_cesa_dma_iter *dma_iter, | |
197 | struct mv_cesa_sg_dma_iter *sgiter, | |
198 | gfp_t gfp_flags) | |
199 | { | |
200 | u32 flags = sgiter->dir == DMA_TO_DEVICE ? | |
201 | CESA_TDMA_DST_IN_SRAM : CESA_TDMA_SRC_IN_SRAM; | |
202 | unsigned int len; | |
203 | ||
204 | do { | |
205 | dma_addr_t dst, src; | |
206 | int ret; | |
207 | ||
208 | len = mv_cesa_req_dma_iter_transfer_len(dma_iter, sgiter); | |
209 | if (sgiter->dir == DMA_TO_DEVICE) { | |
210 | dst = CESA_SA_DATA_SRAM_OFFSET + sgiter->op_offset; | |
211 | src = sg_dma_address(sgiter->sg) + sgiter->offset; | |
212 | } else { | |
213 | dst = sg_dma_address(sgiter->sg) + sgiter->offset; | |
214 | src = CESA_SA_DATA_SRAM_OFFSET + sgiter->op_offset; | |
215 | } | |
216 | ||
217 | ret = mv_cesa_dma_add_data_transfer(chain, dst, src, len, | |
218 | flags, gfp_flags); | |
219 | if (ret) | |
220 | return ret; | |
221 | ||
222 | } while (mv_cesa_req_dma_iter_next_transfer(dma_iter, sgiter, len)); | |
223 | ||
224 | return 0; | |
225 | } |